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| author | Stefan Roese <sr@denx.de> | 2007-07-16 10:02:12 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-16 10:02:12 +0200 |
| commit | 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf (patch) | |
| tree | ba14a7e8d8780dce329966d8432c7cfc6d8c4f81 | |
| parent | 2a49fc17d09020e7ebd9536694d99d20e419fcb8 (diff) | |
| download | u-boot-imx-8848ec858f74ed6dab06fb6d5ddc933e0a1328bf.zip u-boot-imx-8848ec858f74ed6dab06fb6d5ddc933e0a1328bf.tar.gz u-boot-imx-8848ec858f74ed6dab06fb6d5ddc933e0a1328bf.tar.bz2 | |
ppc4xx: Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/lwmon5/sdram.c | 1 | ||||
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 9a4a8ee..b6863b6 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -54,7 +54,6 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 8c18d0f..0b0c55a 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -271,7 +271,6 @@ typedef struct bank_param BANKPARMS; #ifdef CFG_SIMULATE_SPD_EEPROM extern unsigned char cfg_simulate_spd_eeprom[128]; #endif -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); static unsigned char spd_read(uchar chip, uint addr); static void get_spd_info(unsigned long *dimm_populated, |