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| author | Peter Tyser <ptyser@xes-inc.com> | 2009-05-22 10:26:37 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 17:23:47 -0500 |
| commit | 388517e4b745b00256c2fa201ce7bccb67b4f245 (patch) | |
| tree | c2614f3b64c5a881c8640017a0cacc6abee5077b | |
| parent | 25623937bb81cae788d767e6c59a11c96fc82866 (diff) | |
| download | u-boot-imx-388517e4b745b00256c2fa201ce7bccb67b4f245.zip u-boot-imx-388517e4b745b00256c2fa201ce7bccb67b4f245.tar.gz u-boot-imx-388517e4b745b00256c2fa201ce7bccb67b4f245.tar.bz2 | |
xes: Update Freescale clock code to work with 86xx processors
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | board/xes/common/Makefile | 3 | ||||
| -rw-r--r-- | board/xes/common/fsl_8xxx_clk.c (renamed from board/xes/common/fsl_8572_clk.c) | 8 |
2 files changed, 10 insertions, 1 deletions
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 6aef6f4..d022831 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -30,7 +30,8 @@ endif LIB = $(obj)lib$(VENDOR).a COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o -COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o +COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o +COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8572_clk.c b/board/xes/common/fsl_8xxx_clk.c index f5df2da..0155670 100644 --- a/board/xes/common/fsl_8572_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -27,7 +27,12 @@ */ unsigned long get_board_sys_clk(ulong dummy) { +#if defined(CONFIG_MPC85xx) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#elif defined(CONFIG_MPC86xx) + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; +#endif u32 gpporcr = gur->gpporcr; if (gpporcr & 0x10000) @@ -36,8 +41,10 @@ unsigned long get_board_sys_clk(ulong dummy) return 50000000; } +#ifdef CONFIG_MPC85xx /* * Return DDR input clock - synchronous with SYSCLK or 66 MHz + * Note: 86xx doesn't support asynchronous DDR clk */ unsigned long get_board_ddr_clk(ulong dummy) { @@ -49,3 +56,4 @@ unsigned long get_board_ddr_clk(ulong dummy) return 66666666; } +#endif |