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authorJason Liu <r64343@freescale.com>2012-12-10 13:29:05 +0800
committerJason Liu <r64343@freescale.com>2012-12-10 14:32:52 +0800
commit032d11b26bf166bd6fc00ac213291cd4be1ee949 (patch)
tree35301e1fc0d2a970c1751a09380752b3b7eda178
parent199599c21a6bddbaa105db0ab799cd4379b2b585 (diff)
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ENGR00236337: mx6/clock: emi_slow clock rate is not printed out correctly
This issue due to PODF is not used correcly, need use the following instead: ACLK_EMI_SLOW_PODF_OFFSET, the original used ACLK_EMI_PODF_OFFSET was wrong. Signed-off-by: Jason Liu <r64343@freescale.com>
-rw-r--r--cpu/arm_cortexa8/mx6/generic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c
index bb91642..c3ce97e 100644
--- a/cpu/arm_cortexa8/mx6/generic.c
+++ b/cpu/arm_cortexa8/mx6/generic.c
@@ -286,7 +286,7 @@ static u32 __get_emi_slow_clk(void)
u32 emi_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK) >>
MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
u32 podf = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
- MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
+ MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
switch (emi_clk_sel) {
default: