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| author | Bartlomiej Sieka <tur@semihalf.com> | 2007-10-23 11:36:07 +0200 |
|---|---|---|
| committer | Bartlomiej Sieka <tur@semihalf.com> | 2007-10-23 11:36:07 +0200 |
| commit | eff501904df2bf1724a750062628ba2c51dbb1f8 (patch) | |
| tree | 8a3e612edb15e91855b2d0c4abda804b413c844a | |
| parent | 5441f61a3d8b7034f19fc1361183e936198e6dbb (diff) | |
| download | u-boot-imx-eff501904df2bf1724a750062628ba2c51dbb1f8.zip u-boot-imx-eff501904df2bf1724a750062628ba2c51dbb1f8.tar.gz u-boot-imx-eff501904df2bf1724a750062628ba2c51dbb1f8.tar.bz2 | |
Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.
Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
| -rw-r--r-- | board/motionpro/motionpro.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index f83998e..68257b8 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -138,6 +138,12 @@ long int initdram(int board_type) #ifndef CFG_RAMBOOT ulong test1, test2; + /* According to AN3221 (MPC5200B SDRAM Initialization and + * Configuration), the SDelay register must be written a value of + * 0x00000004 as the first step of the SDRAM contorller configuration. + */ + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + /* configure SDRAM start/end for detection */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ |