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| author | David Saada <David.Saada@ecitele.com> | 2008-03-31 02:37:38 -0700 |
|---|---|---|
| committer | Ben Warren <biggerbadderben@gmail.com> | 2008-08-07 22:57:36 -0700 |
| commit | d5d28fe4aad5f4535400647a5617c11039506467 (patch) | |
| tree | 9991b0b1526d259cceb4d75ad3696d492afdbe3d | |
| parent | 81091f58f0c58ecd26c5b05de2ae20ca6cdb521c (diff) | |
| download | u-boot-imx-d5d28fe4aad5f4535400647a5617c11039506467.zip u-boot-imx-d5d28fe4aad5f4535400647a5617c11039506467.tar.gz u-boot-imx-d5d28fe4aad5f4535400647a5617c11039506467.tar.bz2 | |
QE UEC: Add MII Commands
Add MII commands to the UEC driver. Note that once a UEC device is selected,
any device on its MDIO bus can be addressed.
Signed-off-by: David Saada <david.saada@ecitele.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| -rw-r--r-- | drivers/qe/uec.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index d2c430b..049a74d 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -29,6 +29,7 @@ #include "uccf.h" #include "uec.h" #include "uec_phy.h" +#include "miiphy.h" #if defined(CONFIG_QE) @@ -125,6 +126,17 @@ static uec_info_t eth4_uec_info = { }; #endif +#define MAXCONTROLLERS (4) + +static struct eth_device *devlist[MAXCONTROLLERS]; + +static int uec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +static int uec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); +void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); + static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) { uec_t *uec_regs; @@ -1334,6 +1346,8 @@ int uec_initialize(int index) return -EINVAL; } + devlist[index] = dev; + uec->uec_info = uec_info; sprintf(dev->name, "FSL UEC%d", index); @@ -1356,6 +1370,45 @@ int uec_initialize(int index) return err; } +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ + && !defined(BITBANGMII) + miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); +#endif + return 1; } + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ + && !defined(BITBANGMII) + +/* + * Read a MII PHY register. + * + * Returns: + * 0 on success + */ +static int uec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + *value = uec_read_phy_reg(devlist[0], addr, reg); + + return 0; +} + +/* + * Write a MII PHY register. + * + * Returns: + * 0 on success + */ +static int uec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + uec_write_phy_reg(devlist[0], addr, reg, value); + + return 0; +} + +#endif + #endif /* CONFIG_QE */ |