* Patch by Laurent Mohin, 10 Feb 2004:

  Fix buffer overflow in common/usb.c

* Patch by Tolunay Orkun, 10 Feb 2004:
  Add support for Cogent CSB272 board

* Code cleanup

24 files changed, 1090 insertions, 125 deletions

diff --git a/CHANGELOG b/CHANGELOG
index b6eaa89..13516de 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,12 @@
 Changes for U-Boot 1.0.2:
 ======================================================================
 
+* Patch by Laurent Mohin, 10 Feb 2004:
+  Fix buffer overflow in common/usb.c
+
+* Patch by Tolunay Orkun, 10 Feb 2004:
+  Add support for Cogent CSB272 board
+
 * Patch by Thomas Elste, 10 Feb 2004:
   Add support for NET+50 CPU and ModNET50 board
 
diff --git a/MAKEALL b/MAKEALL
index c8dfb67..0705488 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -40,7 +40,7 @@ LIST_8xx="	\
 	GEN860T_SC	GENIETV		GTH		hermes		\
 	IAD210		ICU862_100MHz	IP860		IVML24		\
 	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K           LANTEC	        lwmon   	\
+	IVMS8_256	KUP4K		LANTEC		lwmon		\
 	MBX		MBX860T		MHPC		MPC86xADS	\
 	MVS1		NETVIA		NETVIA_V2	NX823		\
 	pcu_e		QS823		QS850		QS860T		\
@@ -56,15 +56,15 @@ LIST_8xx="	\
 #########################################################################
 
 LIST_4xx="	\
-	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
-	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-	DP405           DU405    	EBONY           ERIC  		\
-	EXBITGEN	HUB405          MIP405  	MIP405T		\
-	ML2		OCRTC		ORSG		PCI405		\
-	PIP405		PLU405          PMC405          PPChameleonEVB	\
-	VOH405          W7OLMC		W7OLMG          WALNUT405	\
-	XPEDITE1K							\
+	ADCIOP		AR405		ASH405		BUBINGA405EP	\
+	CANBT		CPCI405		CPCI4052	CPCI405AB	\
+	CPCI440		CPCIISER4	CRAYL1		csb272		\
+	DASA_SIM	DP405		DU405		EBONY		\
+	ERIC		EXBITGEN	HUB405		MIP405		\
+	MIP405T		ML2		OCRTC		ORSG		\
+	PCI405		PIP405		PLU405		PMC405		\
+	PPChameleonEVB	VOH405		W7OLMC		W7OLMG		\
+	WALNUT405	XPEDITE1K					\
 "
 
 #########################################################################
@@ -72,9 +72,9 @@ LIST_4xx="	\
 #########################################################################
 
 LIST_824x="	\
-	A3000           BMW		CPC45		CU824		\
-	debris		MOUSSE          MUSENKI    	MVBLUE		\
-	OXC		PN62		Sandpoint8240   Sandpoint8245	\
+	A3000		BMW		CPC45		CU824		\
+	debris		MOUSSE		MUSENKI		MVBLUE		\
+	OXC		PN62		Sandpoint8240	Sandpoint8245	\
 	SL8245		utx8245						\
 "
 
diff --git a/Makefile b/Makefile
index 3525d87..1520f57 100644
--- a/Makefile
+++ b/Makefile
@@ -558,6 +558,9 @@ CPCIISER4_config:	unconfig
 CRAYL1_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx L1 cray
 
+csb272_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx csb272
+
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
 
diff --git a/board/csb272/Makefile b/board/csb272/Makefile
new file mode 100644
index 0000000..926e065
--- /dev/null
+++ b/board/csb272/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/csb272/config.mk b/board/csb272/config.mk
new file mode 100644
index 0000000..4672f08
--- /dev/null
+++ b/board/csb272/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB272 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
new file mode 100644
index 0000000..0604189
--- /dev/null
+++ b/board/csb272/csb272.c
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <405gp_enet.h>
+
+/*
+ * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
+ *
+ * CLKA output => Epson LCD Controller
+ * CLKB output => Not Connected
+ * CLKC output => Ethernet
+ * CLKD output => UART external clock
+ *
+ * Note: these values are obtained from device after init by micromonitor
+*/
+uchar pll_fs6377_regs[16] = {
+	0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
+	0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
+
+/*
+ * pll_init: Initialize AMIS IC FS6377-01 PLL
+ *
+ * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
+ *
+ */
+int pll_init(void)
+{
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	return  i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
+		(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
+}
+
+/*
+ * board_pre_init: do any preliminary board initialization
+ *
+ */
+int board_pre_init(void)
+{
+	/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
+	(void) get_clocks();
+	pll_init();
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB272\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset(CONFIG_PHY_ADDR);
+	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
+	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+
+	return 0; /* success */
+}
diff --git a/board/csb272/init.S b/board/csb272/init.S
new file mode 100644
index 0000000..e00ebf8
--- /dev/null
+++ b/board/csb272/init.S
@@ -0,0 +1,216 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x007000c0)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x02869200)*/
+	WDCR_EBC(pb0ap, 0x07869200)
+	WDCR_EBC(pb0cr, 0xfe0bc000)
+	/********************************************************************
+	 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0x1f869200)
+	WDCR_EBC(pb1cr, 0xf0818000)
+	/********************************************************************
+	 * Memory Bank 2 (Epson S1D13506) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb2ap, 0x05860300)
+	WDCR_EBC(pb2cr, 0xf045a000)
+	/********************************************************************
+	 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb3ap, 0x0387d200)
+	WDCR_EBC(pb3cr, 0xf021c000)
+	/********************************************************************
+	 * Memory Bank 4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00084001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds
new file mode 100644
index 0000000..8dbc592
--- /dev/null
+++ b/board/csb272/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb272/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c
index fc04d91..a50639e 100644
--- a/board/modnet50/flash.c
+++ b/board/modnet50/flash.c
@@ -312,7 +312,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		case (FLASH_AM160LV | FLASH_AM160B):
 			setup_offset = UNLOCK_ADDR1;	/* just the adress for setup_cmd differs */
 		case FLASH_AMDL323B:
-			/* 
+			/*
 			 * Disable interrupts which might cause a timeout
 			 * here. Remember that our exception vectors are
 			 * at address 0 in the flash, and we don't want a
@@ -416,7 +416,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data)
 	if ((*(__u16 *) (dest) & data) != data)
 		return ERR_NOT_ERASED;
 
-	/* 
+	/*
 	 * Disable interrupts which might cause a timeout
 	 * here. Remember that our exception vectors are
 	 * at address 0 in the flash, and we don't want a
diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds
index ac09f5f..9899790 100644
--- a/board/modnet50/u-boot.lds
+++ b/board/modnet50/u-boot.lds
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -29,7 +29,7 @@ SECTIONS
 	. = 0x00000000;
 
 	. = ALIGN(4);
-	.text      :
+	.text	   :
 	{
 	  cpu/arm720t/start.o	(.text)
 	  *(.text)
@@ -52,17 +52,17 @@ SECTIONS
 	__bss_start = .;
 	.bss : { *(.bss) }
 	_end = .;
-                                  /* Stabs debugging sections.    */
-        .stab 0 : { *(.stab) }
-        .stabstr 0 : { *(.stabstr) }
-        .stab.excl 0 : { *(.stab.excl) }
-        .stab.exclstr 0 : { *(.stab.exclstr) }
-        .stab.index 0 : { *(.stab.index) }
-        .stab.indexstr 0 : { *(.stab.indexstr) }
-        .comment 0 : { *(.comment) }
-        .debug_abbrev 0 : { *(.debug_abbrev) }
-        .debug_info 0 : { *(.debug_info) }
-        .debug_line 0 : { *(.debug_line) }
-        .debug_pubnames 0 : { *(.debug_pubnames) }
-        .debug_aranges 0 : { *(.debug_aranges) }
+				  /* Stabs debugging sections.	  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/common/cmd_ace.c b/common/cmd_ace.c
index ee77f13..555fbe3 100644
--- a/common/cmd_ace.c
+++ b/common/cmd_ace.c
@@ -195,11 +195,4 @@ static unsigned long systemace_read(int dev,
 
       return blkcnt;
 }
-
-
 #endif
-
-/*
- * $Log: $
- */
-
diff --git a/common/cmd_itest.c b/common/cmd_itest.c
index 9e920c9..87260b0 100644
--- a/common/cmd_itest.c
+++ b/common/cmd_itest.c
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -159,13 +159,13 @@ int binary_test (char *op, char *arg1, char *arg2, int w)
 /* command line interface to the shell test */
 int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 {
-        int	value, w;
+	int	value, w;
 
-        /* Validate arguments */
-        if ((argc != 4)){
+	/* Validate arguments */
+	if ((argc != 4)){
 		printf("Usage:\n%s\n", cmdtp->usage);
-        	return 1;
-        }
+		return 1;
+	}
 
 	/* Check for a data width specification.
 	 * Defaults to long (4) if no specification.
@@ -192,6 +192,6 @@ int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 
 U_BOOT_CMD(
 	itest, 4, 0, do_itest,
-	"itest   - return true/false on integer compare\n",
+	"itest	 - return true/false on integer compare\n",
 	"[.b, .w, .l, .s] [*]value1 <op> [*]value2\n"
 );
diff --git a/common/usb.c b/common/usb.c
index a96052a..1bb9438 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -25,7 +25,6 @@
  *
  */
 
-
 /*
  * How it works:
  *
@@ -47,7 +46,7 @@
 #endif
 
 
-#undef USB_DEBUG
+/* #define USB_DEBUG */
 
 #ifdef	USB_DEBUG
 #define	USB_PRINTF(fmt,args...)	printf (fmt ,##args)
@@ -55,6 +54,8 @@
 #define USB_PRINTF(fmt,args...)
 #endif
 
+#define USB_BUFSIZ	512
+
 static struct usb_device usb_dev[USB_MAX_DEVICE];
 static int dev_index;
 static int running;
@@ -387,6 +388,12 @@ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cf
 	}
 	tmp=swap_16(config->wTotalLength);
 
+	if (tmp > USB_BUFSIZ) {
+		USB_PRINTF("usb_get_configuration_no: failed to get descriptor - too long: %d\n",
+			tmp);
+		return -1;
+	}
+
 	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp);
 	USB_PRINTF("get_conf_no %d Result %d, wLength %d\n",cfgno,result,tmp);
 	return result;
@@ -516,8 +523,7 @@ int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char
  */
 int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
 {
-
-	unsigned char mybuf[256];
+	unsigned char mybuf[USB_BUFSIZ];
 	unsigned char *tbuf;
 	int err;
 	unsigned int u, idx;
@@ -551,6 +557,12 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
 		return err;
 	u=tbuf[0];
 	USB_PRINTF("Strn Len %d, index %d\n",u,index);
+
+	if (u > USB_BUFSIZ) {
+		USB_PRINTF("usb_string: failed to get string - too long: %d\n", u);
+		return -1;
+	}
+
 	err = usb_get_string(dev, dev->string_langid, index, tbuf, u);
 	if (err < 0)
 		return err;
@@ -619,7 +631,7 @@ int usb_new_device(struct usb_device *dev)
 {
 	int addr, err;
 	int tmp;
-	unsigned char tmpbuf[256];
+	unsigned char tmpbuf[USB_BUFSIZ];
 
 	dev->descriptor.bMaxPacketSize0 = 8;  /* Start off at 8 bytes  */
 	dev->maxpacketsize = 0;		/* Default to 8 byte max packet size */
@@ -895,7 +907,7 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port)
 
 int usb_hub_configure(struct usb_device *dev)
 {
-	unsigned char buffer[256], *bitmap;
+	unsigned char buffer[USB_BUFSIZ], *bitmap;
 	struct usb_hub_descriptor *descriptor;
 	struct usb_hub_status *hubsts;
 	int i;
@@ -912,6 +924,13 @@ int usb_hub_configure(struct usb_device *dev)
 		return -1;
 	}
 	descriptor = (struct usb_hub_descriptor *)buffer;
+
+	if (descriptor->bLength > USB_BUFSIZ) {
+		USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor - too long: %d\N",
+			descriptor->bLength);
+		return -1;
+	}
+
 	if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) {
 		USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor 2nd giving up %lX\n",dev->status);
 		return -1;
@@ -968,6 +987,12 @@ int usb_hub_configure(struct usb_device *dev)
 	for (i = 0; i < dev->maxchild; i++)
 		USB_HUB_PRINTF("port %d is%s removable\n", i + 1,
 			hub->desc.DeviceRemovable[(i + 1)/8] & (1 << ((i + 1)%8)) ? " not" : "");
+	if (sizeof(struct usb_hub_status) > USB_BUFSIZ) {
+		USB_HUB_PRINTF("usb_hub_configure: failed to get Status - too long: %d\n",
+			descriptor->bLength);
+		return -1;
+	}
+
 	if (usb_get_hub_status(dev, buffer) < 0) {
 		USB_HUB_PRINTF("usb_hub_configure: failed to get Status %lX\n",dev->status);
 		return -1;
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 0291193..67e581a 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -17,7 +17,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -43,8 +43,8 @@ extern void reset_cpu(ulong addr);
 #define READ_TIMER (IO_TC1D & 0xffff)
 #else
 #define IRQEN	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
-#define TM2CTRL	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
-#define TM2STAT	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
+#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
+#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
 #endif
@@ -112,15 +112,15 @@ void show_regs (struct pt_regs *regs)
 
 	flags = condition_codes (regs);
 
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-			"sp : %08lx  ip : %08lx  fp : %08lx\n",
+	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
+			"sp : %08lx  ip : %08lx	 fp : %08lx\n",
 			instruction_pointer (regs),
 			regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
 			regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
 			regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
 			regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
 	printf ("Flags: %c%c%c%c",
 			flags & CC_N_BIT ? 'N' : 'n',
@@ -188,7 +188,7 @@ static ulong lastdec;
 int interrupt_init (void)
 {
 #ifdef CONFIG_NETARM
-        /* disable all interrupts */
+	/* disable all interrupts */
 	IRQEN = 0;
 
 	/* operate timer 2 in non-prescale mode */
diff --git a/doc/README.commands.itest b/doc/README.commands.itest
index db54160..5e0fe86 100644
--- a/doc/README.commands.itest
+++ b/doc/README.commands.itest
@@ -1,12 +1,12 @@
-A slow day today so here is a revised itest command with provisional 
+A slow day today so here is a revised itest command with provisional
 support for comparing strings as well :-))
 
 Now table driven to allow the operators
 -eq, -ne, -lt, -gt, -le, -ge, ==, !=, <>, <, >, <=, >=
 
-Uses the expected command modifier for integer compares of width 1, 2 or 
-4 bytes of .b, .w, .l and the new modifer of .s for a string compare. 
-String comparison is over the length of the shorter, this hopefully 
+Uses the expected command modifier for integer compares of width 1, 2 or
+4 bytes of .b, .w, .l and the new modifer of .s for a string compare.
+String comparison is over the length of the shorter, this hopefully
 avoids missing terminators when using an indirect pointer.
 
 eg.
diff --git a/doc/README.modnet50 b/doc/README.modnet50
index de7165c..d8d9c9d 100644
--- a/doc/README.modnet50
+++ b/doc/README.modnet50
@@ -2,7 +2,7 @@ U-BOOT Port for FSForth ModNET50 Board
 --------------------------------------
 
 author: Thomas Elste <info@elste.org>
-        IMMS gGmbH <www.imms.de>
+	IMMS gGmbH <www.imms.de>
 
 The port based upon an early (partial complete)
 armboot-port from Stephan Linz for the ModNET50 Board.
@@ -19,7 +19,7 @@ Overview:
 Current Configuration (include/configs/modnet50.h):
 
 Memory Map: 0x00000000 - 0x00FFFFFF 16M SDRAM
-            0x10000000 - 0x101FFFFF  2M Flash
+	    0x10000000 - 0x101FFFFF  2M Flash
 
 The Flash uses a BB-Architectur with 35 sectors
 (0:16K; 1,2:8K; 3:32K; 4-34:64K). U-Boot is located in
@@ -48,15 +48,15 @@ Files:
 cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
 
 board/modnet50/memsetup.S   .. memory setup for ModNET50
-board/modnet50/flash.c      .. flash routines
+board/modnet50/flash.c	    .. flash routines
 board/modnet50/modnet50.c   .. some board init stuff
 
-drivers/netarm_eth.c        .. ethernet driver for the NET+50 CPU
-drivers/netarm_eth.h        .. header for ethernet driver
+drivers/netarm_eth.c	    .. ethernet driver for the NET+50 CPU
+drivers/netarm_eth.h	    .. header for ethernet driver
 
 include/configs/modnet50.h  .. configuration file for ModNET50
 
-include/netarm_*.h          .. register and macro definitions for
-                               the NETARM CPU family
+include/netarm_*.h	    .. register and macro definitions for
+			       the NETARM CPU family
 
-doc/README.modnet50         .. this readme
+doc/README.modnet50	    .. this readme
diff --git a/drivers/netarm_eth.c b/drivers/netarm_eth.c
index a15b653..89b3a83 100644
--- a/drivers/netarm_eth.c
+++ b/drivers/netarm_eth.c
@@ -22,12 +22,13 @@
 
 
 #include <common.h>
+
+#ifdef CONFIG_DRIVER_NETARMETH
 #include <command.h>
 #include <net.h>
 #include "netarm_eth.h"
 #include <asm/arch/netarm_registers.h>
 
-#ifdef CONFIG_DRIVER_NETARMETH
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 
diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/include/asm-arm/arch-arm720t/netarm_dma_module.h
index c517035..328eaf0 100644
--- a/include/asm-arm/arch-arm720t/netarm_dma_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_dma_module.h
@@ -1,5 +1,4 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_dma_module.h
+/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
  *
  * Copyright (C) 2000 NETsilicon, Inc.
  * Copyright (C) 2000 WireSpeed Communications Corporation
@@ -181,4 +180,3 @@ typedef	struct __NETARM_DMA_Buff_Desc_M_to_M
 #endif
 
 #endif
-
diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h
index 6ab5cc1..90d9da8 100644
--- a/include/asm-arm/arch-arm720t/netarm_gen_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h
@@ -34,32 +34,32 @@
 
 /* GEN unit register offsets */
 
-#define	NETARM_GEN_MODULE_BASE		(0xFFB00000)
+#define NETARM_GEN_MODULE_BASE		(0xFFB00000)
 
 #define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
 
-#define	NETARM_GEN_SYSTEM_CONTROL	(0x00)
-#define	NETARM_GEN_STATUS_CONTROL	(0x04)
-#define	NETARM_GEN_PLL_CONTROL		(0x08)
-#define	NETARM_GEN_SOFTWARE_SERVICE	(0x0c)
+#define NETARM_GEN_SYSTEM_CONTROL	(0x00)
+#define NETARM_GEN_STATUS_CONTROL	(0x04)
+#define NETARM_GEN_PLL_CONTROL		(0x08)
+#define NETARM_GEN_SOFTWARE_SERVICE	(0x0c)
 
-#define	NETARM_GEN_TIMER1_CONTROL	(0x10)
-#define	NETARM_GEN_TIMER1_STATUS	(0x14)
-#define	NETARM_GEN_TIMER2_CONTROL	(0x18)
-#define	NETARM_GEN_TIMER2_STATUS	(0x1c)
+#define NETARM_GEN_TIMER1_CONTROL	(0x10)
+#define NETARM_GEN_TIMER1_STATUS	(0x14)
+#define NETARM_GEN_TIMER2_CONTROL	(0x18)
+#define NETARM_GEN_TIMER2_STATUS	(0x1c)
 
-#define	NETARM_GEN_PORTA		(0x20)
-#define	NETARM_GEN_PORTB		(0x24)
-#define	NETARM_GEN_PORTC		(0x28)
+#define NETARM_GEN_PORTA		(0x20)
+#define NETARM_GEN_PORTB		(0x24)
+#define NETARM_GEN_PORTC		(0x28)
 
-#define	NETARM_GEN_INTR_ENABLE		(0x30)
-#define	NETARM_GEN_INTR_ENABLE_SET	(0x34)
-#define	NETARM_GEN_INTR_ENABLE_CLR	(0x38)
-#define	NETARM_GEN_INTR_STATUS_EN	(0x34)
-#define	NETARM_GEN_INTR_STATUS_RAW	(0x38)
+#define NETARM_GEN_INTR_ENABLE		(0x30)
+#define NETARM_GEN_INTR_ENABLE_SET	(0x34)
+#define NETARM_GEN_INTR_ENABLE_CLR	(0x38)
+#define NETARM_GEN_INTR_STATUS_EN	(0x34)
+#define NETARM_GEN_INTR_STATUS_RAW	(0x38)
 
-#define	NETARM_GEN_CACHE_CONTROL1	(0x40)
-#define	NETARM_GEN_CACHE_CONTROL2	(0x44)
+#define NETARM_GEN_CACHE_CONTROL1	(0x40)
+#define NETARM_GEN_CACHE_CONTROL2	(0x44)
 
 /* select bitfield definitions */
 
@@ -72,7 +72,7 @@
 #define NETARM_GEN_SYS_CFG_BUSHALF	(0x20000000)
 #define NETARM_GEN_SYS_CFG_BUSFULL	(0x40000000)
 
-#define NETARM_GEN_SYS_CFG_BCLK_DISABLE	(0x10000000)
+#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
 
 #define NETARM_GEN_SYS_CFG_WDOG_EN	(0x01000000)
 #define NETARM_GEN_SYS_CFG_WDOG_IRQ	(0x00000000)
@@ -112,57 +112,57 @@
 #define NETARM_GEN_PLL_CTL_PLLCNT_MASK	(0x0F000000)
 
 #define NETARM_GEN_PLL_CTL_PLLCNT(x)	(((x)<<24) & \
-                                         NETARM_GEN_PLL_CTL_PLLCNT_MASK)
+					 NETARM_GEN_PLL_CTL_PLLCNT_MASK)
 
 /* Defaults for POLTST and ICP Fields in PLL CTL */
-#define NETARM_GEN_PLL_CTL_OUTDIV(x)    (x)
-#define NETARM_GEN_PLL_CTL_INDIV(x)     ((x)<<6)
-#define NETARM_GEN_PLL_CTL_POLTST_DEF   (0x00000E00)
-#define NETARM_GEN_PLL_CTL_ICP_DEF      (0x0000003C)
+#define NETARM_GEN_PLL_CTL_OUTDIV(x)	(x)
+#define NETARM_GEN_PLL_CTL_INDIV(x)	((x)<<6)
+#define NETARM_GEN_PLL_CTL_POLTST_DEF	(0x00000E00)
+#define NETARM_GEN_PLL_CTL_ICP_DEF	(0x0000003C)
 
 
 /* Software Service Register ( 0xFFB0_000C ) */
 
-#define	NETARM_GEN_SW_SVC_RESETA	(0x123)
-#define	NETARM_GEN_SW_SVC_RESETB	(0x321)
+#define NETARM_GEN_SW_SVC_RESETA	(0x123)
+#define NETARM_GEN_SW_SVC_RESETB	(0x321)
 
 /* PORT C Register ( 0xFFB0_0028 ) */
 
-#define	NETARM_GEN_PORT_MODE(x)		(((x)<<24) + (0xFF00))
-#define	NETARM_GEN_PORT_DIR(x)		(((x)<<16) + (0xFF00))
+#define NETARM_GEN_PORT_MODE(x)		(((x)<<24) + (0xFF00))
+#define NETARM_GEN_PORT_DIR(x)		(((x)<<16) + (0xFF00))
 
 /* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
 
-#define	NETARM_GEN_TCTL_ENABLE		(0x80000000)
-#define	NETARM_GEN_TCTL_INT_ENABLE	(0x40000000)
+#define NETARM_GEN_TCTL_ENABLE		(0x80000000)
+#define NETARM_GEN_TCTL_INT_ENABLE	(0x40000000)
 
-#define	NETARM_GEN_TCTL_USE_IRQ		(0x00000000)
-#define	NETARM_GEN_TCTL_USE_FIQ		(0x20000000)
+#define NETARM_GEN_TCTL_USE_IRQ		(0x00000000)
+#define NETARM_GEN_TCTL_USE_FIQ		(0x20000000)
 
-#define	NETARM_GEN_TCTL_USE_PRESCALE	(0x10000000)
-#define	NETARM_GEN_TCTL_INIT_COUNT(x)	((x) & 0x1FF)
+#define NETARM_GEN_TCTL_USE_PRESCALE	(0x10000000)
+#define NETARM_GEN_TCTL_INIT_COUNT(x)	((x) & 0x1FF)
 
-#define	NETARM_GEN_TSTAT_INTPEN		(0x40000000)
-#define	NETARM_GEN_TSTAT_CTC_MASK	(0x000001FF)
+#define NETARM_GEN_TSTAT_INTPEN		(0x40000000)
+#define NETARM_GEN_TSTAT_CTC_MASK	(0x000001FF)
 
 /* prescale to msecs conversion */
 
-#define	NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 20480 ) * ( 0x1FF - ( (x) &	    \
-                                            NETARM_GEN_TSTAT_CTC_MASK ) +   \
+#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 20480 ) * ( 0x1FF - ( (x) &	    \
+					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
 					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
 
-#define	NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
+#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
 					  NETARM_GEN_TSTAT_CTC_MASK ) | \
 					  NETARM_GEN_TCTL_USE_PRESCALE )
 
 #if 0
 /* ifdef CONFIG_NETARM_PLL_BYPASS else */
 #error test
-#define	NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
-                                            NETARM_GEN_TSTAT_CTC_MASK ) +   \
+#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
+					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
 					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
 
-#define	NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
+#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
 					  NETARM_GEN_TSTAT_CTC_MASK ) | \
 					  NETARM_GEN_TCTL_USE_PRESCALE )
 #endif
diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h
index 02ca9fb..7c63d17 100644
--- a/include/asm-arm/arch-arm720t/netarm_mem_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h
@@ -155,4 +155,3 @@
 #define NETARM_MEM_OPT_WRITE_SYNC	(0x00000001)
 
 #endif
-
diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h
index 231a378..029c7f4 100644
--- a/include/asm-arm/arch-arm720t/netarm_registers.h
+++ b/include/asm-arm/arch-arm720t/netarm_registers.h
@@ -77,4 +77,3 @@
 #include <asm/arch/netarm_eth_module.h>
 
 #endif
-
diff --git a/include/bmp_logo.h b/include/bmp_logo.h
index 265f744..9c924b8 100644
--- a/include/bmp_logo.h
+++ b/include/bmp_logo.h
@@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = {
 	0x0343,  0x0454,  0x0565,  0x0565,  0x0676,  0x0787,  0x0898,  0x0999,
 	0x0AAA,  0x0ABA,  0x0BCB,  0x0CCC,  0x0DDD,  0x0EEE,  0x0FFF,  0x0FB3,
 	0x0FB4,  0x0FC4,  0x0FC5,  0x0FC6,  0x0FD7,  0x0FD8,  0x0FD9,  0x0FDA,
-	0x0FEA,  0x0FEB,  0x0FEC,  0x0FFD,  0x0FFE,  0x0FFF,  0x0FFF,  
+	0x0FEA,  0x0FEB,  0x0FEC,  0x0FFD,  0x0FFE,  0x0FFF,  0x0FFF,
 };
 
 unsigned char bmp_logo_bitmap[] = {
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
new file mode 100644
index 0000000..7457760
--- /dev/null
+++ b/include/configs/csb272.h
@@ -0,0 +1,313 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
+#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init()	*/
+#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
+#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+
+/*
+ * OS Bootstrap configuration
+ *
+ */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
+#endif
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
+
+#if 1
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/ram rw ramdisk_size=4096 " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+	"bootm fe000000 fe100000"
+#endif
+
+#if 0
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"bootp; " \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+	"bootm"
+#endif
+
+/*
+ * BOOTP/DHCP protocol configuration
+ *
+ */
+#define CONFIG_BOOTP_MASK	( CONFIG_BOOTP_DEFAULT		| \
+				  CONFIG_BOOTP_DNS2		| \
+				  CONFIG_BOOTP_BOOTFILESIZE	)
+/*
+ * U-Boot Monitor Command Line Functions Configuration
+ *
+ */
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_ASKENV	| \
+				  CFG_CMD_BEDBUG	| \
+				  CFG_CMD_ELF		| \
+				  CFG_CMD_IRQ		| \
+				  CFG_CMD_I2C		| \
+				  CFG_CMD_PCI		| \
+				  CFG_CMD_DATE		| \
+				  CFG_CMD_MII		| \
+				  CFG_CMD_PING		| \
+				  CFG_CMD_DHCP		 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Serial download configuration
+ *
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * KGDB Configuration
+ *
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ *
+ */
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser */
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
+#endif
+
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CFG_LOAD_ADDR		0x100000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * watchdog configuration
+ *
+ */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * UART configuration
+ *
+ */
+#define CFG_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
+#undef  CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59 */
+#undef  CFG_BASE_BAUD
+#define CONFIG_BAUDRATE		38400	/* Default baud rate */
+#define CFG_BAUDRATE_TABLE      \
+    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * I2C configuration
+ *
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+
+/*
+ * MII PHY configuration
+ *
+ */
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay 		*/
+					/* 32usec min. for LXT971A	*/
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * RTC configuration
+ *
+ * Note that DS1307 RTC is limited to 100Khz I2C bus.
+ *
+ */
+#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
+
+/*
+ * PCI stuff
+ *
+ */
+#define CONFIG_PCI			/* include pci support	        */
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
+
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * IDE stuff
+ *
+ */
+#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+
+/*
+ * Environment configuration
+ *
+ */
+#define CFG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+
+/*
+ * General Memory organization
+ *
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMSTART
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
+#define CFG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
+#define	CFG_ENV_SIZE		0x00001000 /* Size of Environment */
+#define CFG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
+#endif
+
+/*
+ * FLASH Device configuration
+ *
+ */
+#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CFG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CFG_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
+#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+/*
+ * On Chip Memory location/size
+ *
+ */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/*
+ * Global info and initial stack
+ *
+ */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Cache configuration
+ *
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's */
+					/* have only 8kB, 16kB is save here  */
+#define CFG_CACHELINE_SIZE	32
+
+/*
+ * Miscellaneous board specific definitions
+ *
+ */
+#define CFG_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ *
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#endif	/* __CONFIG_H */
diff --git a/net/tftp.c b/net/tftp.c
index 3ba15ab..fdf1770 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -205,10 +205,10 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
 		TftpBlock = ntohs(*(ushort *)pkt);
 
 		/*
-                 * RFC1350 specifies that the first data packet will
-                 * have sequence number 1. If we receive a sequence
-                 * number of 0 this means that there was a wrap
-                 * around of the (16 bit) counter.
+		 * RFC1350 specifies that the first data packet will
+		 * have sequence number 1. If we receive a sequence
+		 * number of 0 this means that there was a wrap
+		 * around of the (16 bit) counter.
 		 */
 		if (TftpBlock == 0) {
 			TftpBlockWrap++;