diff options
author | Jon Loeliger <jdl@freescale.com> | 2006-07-31 09:53:08 -0500 |
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committer | Jon Loeliger <jdl@freescale.com> | 2006-07-31 09:53:08 -0500 |
commit | 3aeec2860471f12f17aa19ce4799ff7f3d335b05 (patch) | |
tree | 49aeccfae1a1870c260fbe44db121bd1fbd90b31 | |
parent | 12d1ff4c18832d26d2bb8aaab240aaa06c2a83eb (diff) | |
parent | 71748af833ca1017edf1415be376366ff2937d17 (diff) | |
download | u-boot-imx-3aeec2860471f12f17aa19ce4799ff7f3d335b05.zip u-boot-imx-3aeec2860471f12f17aa19ce4799ff7f3d335b05.tar.gz u-boot-imx-3aeec2860471f12f17aa19ce4799ff7f3d335b05.tar.bz2 |
Merge branch 'mpc86xx'
-rw-r--r-- | board/mpc8641hpcn/mpc8641hpcn.c | 64 | ||||
-rw-r--r-- | board/mpc8641hpcn/oftree.dts | 2 | ||||
-rw-r--r-- | cpu/mpc86xx/speed.c | 66 | ||||
-rw-r--r-- | doc/README.mpc8641hpcn | 4 |
4 files changed, 67 insertions, 69 deletions
diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 2626ccc..5023c1c 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -359,3 +359,67 @@ my_usage: puts("For example: reset cf 40 2.5 10\n"); puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} + diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index e3f5efa..742a140 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <1c 2>; interrupt-parent = <40000>; }; diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 8088b87..e130705 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,72 +30,6 @@ #include <asm/processor.h> -#ifdef MPC8641HPCN -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); - else - i = in8(PIXIS_BASE + PIXIS_SPD); - } else { - i = in8(PIXIS_BASE + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} - -#endif - void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 907a911..8ea0b1e 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -117,7 +117,7 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): 0xf800_0000 0xf80f_ffff CCSR 1M 0xf810_0000 0xf81f_ffff PIXIS 1M 0xf840_0000 0xf840_3fff Stack space 32K - 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M - 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M + 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M + 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M 0xfe00_0000 0xfeff_ffff Flash(alternate)16M 0xff00_0000 0xffff_ffff Flash(boot bank)16M |