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| author | Fugang Duan <B38611@freescale.com> | 2012-03-13 19:40:17 +0800 |
|---|---|---|
| committer | Fugang Duan <B38611@freescale.com> | 2012-03-20 13:36:56 +0800 |
| commit | 34bd725fcc22e8e2435bbb7b3b51c05376ea9619 (patch) | |
| tree | b577aae1ff4433ab076673e4204dafe14835f2e4 | |
| parent | 5ec7e8338acc96768faa3e9b983e05989e4b99da (diff) | |
| download | u-boot-imx-34bd725fcc22e8e2435bbb7b3b51c05376ea9619.zip u-boot-imx-34bd725fcc22e8e2435bbb7b3b51c05376ea9619.tar.gz u-boot-imx-34bd725fcc22e8e2435bbb7b3b51c05376ea9619.tar.bz2 | |
ENGR00176834-3 - i.MX6DL sabresd : DDR init script update
Use the ddr init script “MX6DL_init_DDR3_400MHz_64bit_1.2.inc”
for SD revB with Rigel mounted, and update the calibration parameters
(write leveling, DQS gating, read delay, write delay),
which is located at:
http://compass.freescale.net/livelink/livelink?func=ll&
objid=225128962&objAction=browse&sort=name
Signed-off-by: Fugang Duan <B38611@freescale.com>
| -rw-r--r-- | board/freescale/mx6q_sabresd/flash_header.S | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/board/freescale/mx6q_sabresd/flash_header.S b/board/freescale/mx6q_sabresd/flash_header.S index 8be2198..13678b0 100644 --- a/board/freescale/mx6q_sabresd/flash_header.S +++ b/board/freescale/mx6q_sabresd/flash_header.S @@ -114,18 +114,18 @@ MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003) # write leveling MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F) MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F) -MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x00370037) -MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x00370037) +MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F) +MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F) # DQS gating, read delay, write delay calibration values # based on calibration compare of 0x00ffff00 -MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x422f0220) -MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x021f0219) -MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x422f0220) -MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x022d022f) -MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x47494b49) -MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x48484c47) -MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x39382b2f) -MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x2f35312c) +MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x420E020E) +MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02000200) +MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x42020202) +MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x01720172) +MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x494C4F4C) +MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x4A4C4C49) +MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3133) +MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x39373F2E) # read data bit delay MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) |