* Add support for PPChameleon Eval Board

* Add support for P3G4 board

* Fix problem with MGT5100 FEC driver: add "early" MAC address
  initialization

31 files changed, 4146 insertions, 34 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 259bc2e..1d46615 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,13 @@
 Changes for U-Boot 0.4.7:
 ======================================================================
 
+* Add support for PPChameleon Eval Board
+
+* Add support for P3G4 board
+
+* Fix problem with MGT5100 FEC driver: add "early" MAC address
+  initialization
+
 * Patch by Yuli Barcohen, 7 Aug 2003:
   check BCSR to detect if the board is configured in PCI mode
 
diff --git a/MAINTAINERS b/MAINTAINERS
index 16240a8..2e748ef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -92,6 +92,8 @@ Wolfgang Denk <wd@denx.de>
 	PM826			MPC8260
 	TQM8260			MPC8260
 
+	P3G4			MPC7410
+
 	PCIPPC2			MPC750
 	PCIPPC6			MPC750
 
diff --git a/MAKEALL b/MAKEALL
index d6547ee..0dbcf72 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -59,7 +59,7 @@ LIST_4xx="	\
 	DU405    	EBONY           ERIC  		EXBITGEN	\
 	MIP405  	MIP405T		ML2		OCRTC		\
 	ORSG		PCI405		PIP405		PMC405          \
-	W7OLMC		W7OLMG          WALNUT405			\
+	PPChameleonEVB	W7OLMC		W7OLMG          WALNUT405	\
 "
 
 #########################################################################
@@ -89,7 +89,8 @@ LIST_8260="	\
 #########################################################################
 
 LIST_74xx="	\
-	EVB64260	PCIPPC2		PCIPPC6		ZUMA		\
+	EVB64260	P3G4		PCIPPC2		PCIPPC6		\
+	ZUMA								\
 "
 
 LIST_7xx="	\
diff --git a/Makefile b/Makefile
index 122fee6..e755928 100644
--- a/Makefile
+++ b/Makefile
@@ -539,6 +539,9 @@ PIP405_config:unconfig
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
 
+PPChameleonEVB_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx PPChameleonEVB dave
+
 W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o
@@ -751,6 +754,9 @@ BAB7xx_config: unconfig
 ELPPC_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
 
+P3G4_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
+
 #========================================================================
 # ARM
 #========================================================================
diff --git a/README b/README
index 26127fa..3fb97e3 100644
--- a/README
+++ b/README
@@ -306,6 +306,7 @@ The following options need to be configured:
 	or	CONFIG_MPC824X, CONFIG_MPC8260
 	or	CONFIG_IOP480
 	or	CONFIG_405GP
+	or	CONFIG_405EP
 	or	CONFIG_440
 	or	CONFIG_MPC74xx
 	or	CONFIG_750FX
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
new file mode 100644
index 0000000..39d2fec
--- /dev/null
+++ b/board/dave/PPChameleonEVB/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
new file mode 100644
index 0000000..04b7cd7
--- /dev/null
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, int *);
+
+
+int board_pre_init (void)
+{
+	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
+        out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+#if 1 /* test-only */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+#else
+	mtebc (epcr, 0x28400000); /* ebc in high-z */
+#endif
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+#if 0 /* test-only */
+	DECLARE_GLOBAL_DATA_PTR;
+#if 0
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned char *duart0_mcr =
+		(unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr =
+		(unsigned char *)((ulong)DUART1_BA + 4);
+
+	bd_t *bd = gd->bd;
+	char *	tmp;                    /* Temporary char pointer      */
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long cntrl0Reg;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+#endif
+
+#if 0
+	/*
+	 * Enable power on PS/2 interface
+	 */
+	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+#endif
+#endif
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PPChameleonEVB");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0 /* test-only */
+	for (;;) {
+		NAND_DISABLE_CE(1);
+		udelay(100);
+		NAND_ENABLE_CE(1);
+		udelay(100);
+	}
+#endif
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern void
+nand_probe(ulong physadr);
+
+void
+nand_init(void)
+{
+	printf("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+	nand_probe(CFG_NAND0_BASE);
+	printf("Probing at 0x%.8x\n", CFG_NAND1_BASE);
+	nand_probe(CFG_NAND1_BASE);
+}
+#endif
diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk
new file mode 100644
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/dave/PPChameleonEVB/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
new file mode 100644
index 0000000..110e021
--- /dev/null
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+	return CFG_DUMMY_FLASH_SIZE;
+#else
+	unsigned long size_b0;
+	int i;
+        uint pbcr;
+        unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+        /* Setup offsets */
+        flash_get_offsets (-size_b0, &flash_info[0]);
+
+        /* Re-do sizing to get full correct info */
+        mtdcr(ebccfga, pb0cr);
+        pbcr = mfdcr(ebccfgd);
+        mtdcr(ebccfga, pb0cr);
+        base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+        mtdcr(ebccfgd, pbcr);
+
+        /* Monitor protection ON by default */
+        (void)flash_protect(FLAG_PROTECT_SET,
+                            -CFG_MONITOR_LEN,
+                            0xffffffff,
+                            &flash_info[0]);
+
+        flash_info[0].size = size_b0;
+
+	return (size_b0);
+#endif
+}
diff --git a/board/dave/PPChameleonEVB/fpgadata.c b/board/dave/PPChameleonEVB/fpgadata.c
new file mode 100644
index 0000000..f5e30dd
--- /dev/null
+++ b/board/dave/PPChameleonEVB/fpgadata.c
@@ -0,0 +1,1139 @@
+  0x1f,0x8b,0x08,0x08,0x80,0xb0,0xc0,0x3e,0x00,0x03,0x61,0x73,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x70,0x14,0x65,
+  0x9a,0xc7,0x9f,0xe9,0xee,0x24,0x9d,0x99,0x4e,0xa6,0x0d,0x84,0x42,0xe5,0x47,0xe7,
+  0xc7,0xba,0xa3,0x37,0x0c,0x63,0x82,0x9a,0x05,0x32,0x69,0x03,0x7f,0xe4,0x84,0x2d,
+  0xd9,0xbd,0xba,0xaa,0xdb,0x5a,0x6b,0x1d,0x5d,0xbc,0xe2,0xb6,0xd0,0xca,0xea,0x55,
+  0x1d,0x67,0x6d,0xdd,0xbd,0x24,0x39,0x08,0x07,0x2b,0x01,0xb9,0x23,0xee,0x51,0x5c,
+  0xf3,0x63,0xcb,0xa8,0xa9,0xad,0x11,0x76,0x0d,0x0a,0xa5,0x4d,0x2e,0x8b,0x21,0x44,
+  0xc8,0xb1,0xd6,0x6e,0x44,0x97,0x1d,0x34,0xab,0x23,0x72,0x18,0xd1,0x92,0x44,0x20,
+  0xb9,0xf7,0xed,0xee,0xf7,0xed,0x9f,0x33,0xc9,0x8e,0x7f,0xf8,0xe4,0x9d,0xd7,0xf6,
+  0x7d,0x9e,0x79,0xfb,0x79,0x3e,0xfd,0x7d,0xde,0x86,0xd2,0xe8,0xb8,0xf9,0x0f,0x40,
+  0xe8,0x31,0x90,0x1f,0x7b,0x66,0xc3,0xb2,0xe4,0x7d,0x8f,0xde,0xfb,0x68,0x32,0x99,
+  0x78,0xea,0xc7,0xeb,0xe1,0x71,0x88,0xd4,0x3d,0x73,0x5f,0xf2,0x89,0x7f,0xfc,0xe9,
+  0xbd,0xcb,0x96,0xc1,0x8f,0xf1,0x5f,0xc9,0x64,0xfd,0xd2,0xe4,0x7d,0x4b,0xef,0xad,
+  0x87,0xf5,0x50,0x7a,0x6f,0x72,0xf9,0xb2,0x65,0xcb,0x97,0x35,0xc0,0x13,0x10,0xaa,
+  0x3f,0x3c,0x8d,0x3f,0x2f,0xbf,0xf0,0xb7,0x7f,0x9f,0x04,0x14,0x02,0x80,0x92,0x64,
+  0x28,0x4d,0xfe,0x1d,0x49,0x86,0x94,0x10,0xa0,0xa6,0x25,0x49,0xd0,0xc9,0xdf,0x60,
+  0x7d,0x5f,0x9a,0x04,0xc5,0xf9,0x77,0x28,0x09,0x2a,0xac,0x03,0x75,0x07,0x54,0x24,
+  0x61,0xe6,0x8f,0x2a,0x20,0x6a,0xfe,0x85,0xf3,0xa7,0x87,0x50,0xde,0x59,0xf6,0xa7,
+  0xe9,0x9a,0x46,0x4d,0x6e,0x16,0xd7,0x0f,0xa9,0xc0,0xae,0x7f,0x61,0x56,0xd7,0xff,
+  0x9a,0x5e,0xff,0x2f,0x9d,0x0f,0x15,0xb3,0x98,0x0e,0x20,0xb0,0xf5,0x58,0xf3,0x11,
+  0xc4,0x20,0x0c,0x1c,0x02,0x0d,0x14,0x6c,0x78,0xaf,0x3f,0x40,0xad,0x93,0x45,0x53,
+  0x70,0x03,0x35,0x65,0xa3,0xa3,0xfc,0x3c,0x38,0x87,0x9a,0x40,0x9a,0xe0,0x53,0x30,
+  0x4d,0x46,0x8e,0xf1,0x57,0x4d,0x63,0x82,0x1f,0x87,0x56,0x6b,0x7e,0xff,0xfc,0x5f,
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+  0x0b,0x7f,0x96,0x4a,0xae,0x8e,0xac,0x83,0x43,0x85,0xf6,0x54,0x83,0x00,0x37,0x20,
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+  0x02,0x1c,0xe1,0xc4,0xa0,0x97,0x81,0xfb,0x8c,0x7f,0x90,0xfb,0xbf,0x7e,0x65,0xfa,
+  0xe7,0xb9,0x17,0x76,0x5d,0x5b,0xcb,0xc1,0xf7,0x77,0x5d,0xbb,0xa2,0x7e,0xed,0xca,
+  0xe9,0x1d,0x2f,0x2c,0xfa,0xe7,0xda,0xfa,0xf4,0xca,0x43,0x1c,0xc8,0xed,0x59,0xf6,
+  0xe0,0xed,0x17,0xfe,0x7d,0xcf,0x99,0x77,0xcf,0x71,0xf0,0xe2,0x99,0xf7,0xcf,0x2d,
+  0xfb,0x64,0xcd,0xd1,0x6f,0x5d,0x38,0x71,0xfe,0xdc,0xb2,0x07,0xd6,0x5c,0xe0,0x00,
+  0x3e,0x83,0xdc,0xfa,0x44,0xed,0x55,0xe9,0x15,0xb9,0x1d,0x9b,0x3a,0xcf,0x35,0x7e,
+  0xb7,0xfb,0x42,0xee,0xb7,0x7f,0x7b,0xeb,0x53,0x2b,0x1e,0x7c,0x73,0x45,0xee,0xf1,
+  0xf3,0x9d,0x17,0x56,0x5c,0xfd,0xe6,0x8a,0x33,0x8f,0x9f,0x97,0xeb,0x77,0x3e,0x70,
+  0xfb,0xd1,0x6f,0xbd,0x78,0xe2,0xdd,0x73,0x9d,0x4e,0x33,0xce,0x77,0xf2,0x86,0x9d,
+  0x78,0x1f,0xeb,0xdf,0x7e,0x94,0xb5,0x30,0x50,0x7f,0xe1,0xe5,0xfd,0x47,0x77,0xdc,
+  0x74,0xe2,0xd1,0x8d,0xcb,0xd8,0x1f,0x3e,0x8b,0x7f,0x88,0xe0,0xed,0xe6,0x17,0x47,
+  0xdf,0x3d,0xb7,0x30,0xc9,0xc1,0xa9,0xbf,0x0e,0x34,0xa8,0x75,0x8b,0xf9,0xa4,0x7e,
+  0xb5,0x9e,0x2d,0x28,0x08,0xe0,0x6a,0x5a,0x3b,0x09,0x5b,0xb1,0x64,0x4e,0xbc,0x76,
+  0x9f,0x82,0x20,0x73,0x35,0x25,0x72,0x7f,0x52,0x97,0x1f,0x8e,0x5e,0xe9,0xb0,0x41,
+  0xe4,0x87,0x30,0x64,0xce,0xe7,0xc0,0xe1,0x87,0x52,0xfd,0x62,0x7e,0xe8,0x01,0x5c,
+  0x91,0x19,0x51,0xe4,0xfc,0x30,0xd0,0x20,0xa4,0x6d,0x50,0x13,0xcb,0xd9,0x02,0x30,
+  0xda,0xb6,0x91,0x01,0x8d,0x6c,0x47,0x46,0xc4,0x4a,0x02,0xe3,0x59,0xeb,0xd9,0x46,
+  0xa2,0xc3,0xdd,0x0d,0xf6,0x58,0x4f,0x07,0x59,0x30,0xba,0xdc,0x88,0x1d,0xa0,0xdb,
+  0xc8,0x02,0x1b,0xc1,0xeb,0x74,0x5b,0x96,0x83,0x42,0xf0,0xf9,0x0e,0x3f,0xb4,0x0c,
+  0x48,0xea,0xec,0xf9,0xde,0x7f,0xc4,0x80,0xc1,0x81,0x2f,0x51,0xa4,0x85,0x38,0xad,
+  0x32,0x7c,0x7e,0x21,0x2d,0xb4,0xf4,0x1c,0xbd,0x6a,0x12,0xc1,0x16,0x7d,0x9c,0x5e,
+  0x45,0x6a,0xed,0xb4,0x19,0xd8,0xa3,0x7d,0x89,0xae,0xcc,0xce,0xcb,0xf7,0x8e,0xc1,
+  0x75,0xf4,0xae,0x6c,0xd3,0x44,0xcf,0xd3,0xb1,0x56,0x58,0x95,0x6d,0xca,0x23,0xb8,
+  0x0e,0x7f,0x42,0x30,0x2e,0xe9,0x4f,0xad,0xd0,0x08,0xcd,0x10,0x2f,0xa8,0x39,0x98,
+  0x8b,0x4a,0x2b,0x8e,0xdc,0x87,0xaf,0x36,0x58,0xb2,0xd4,0x07,0xa6,0xff,0x07,0xb8,
+  0x55,0xd5,0x71,0xb5,0xa7,0x5b,0x74,0x36,0x8b,0x70,0xd9,0x37,0x51,0xa5,0xf5,0xb2,
+  0xdd,0x6d,0x86,0xc4,0xf5,0x1e,0x64,0x8b,0x74,0x0b,0xf1,0xcc,0xe7,0xf8,0x7c,0xd3,
+  0xb1,0xbc,0x25,0xf9,0x06,0x53,0x17,0x76,0x3a,0xb6,0x25,0x35,0xc7,0xf4,0x56,0xaa,
+  0x65,0x15,0x56,0x22,0xd7,0x47,0xd2,0xcb,0x95,0x24,0x53,0xf4,0x49,0x48,0x63,0x6f,
+  0xd7,0xb0,0x92,0x7b,0x10,0xec,0x12,0x3f,0x5d,0x62,0x7b,0xf5,0x75,0x62,0x2a,0x16,
+  0x8c,0xc3,0x55,0x06,0xea,0x2c,0x0e,0xa0,0x76,0x0c,0x36,0x31,0xc0,0xae,0x32,0xb1,
+  0x9c,0xf6,0x57,0x19,0xb8,0x02,0xba,0x62,0x32,0x7e,0xc8,0x49,0x91,0x2e,0xf3,0xc3,
+  0x31,0x06,0x72,0x7b,0x97,0x88,0x92,0x9c,0xbf,0x9e,0xb2,0x37,0x2f,0xe1,0x87,0x66,
+  0x11,0x30,0x0b,0x9e,0x7d,0xde,0xc4,0xb7,0x4c,0x71,0x92,0xa6,0x0f,0x3b,0x00,0x5e,
+  0xa1,0x0e,0xd8,0x2b,0x4a,0xa2,0x92,0xfe,0x37,0x7b,0x4d,0xc1,0xdf,0xd8,0xd1,0x25,
+  0x02,0x40,0xfe,0x36,0xc2,0x7a,0xc0,0x60,0x44,0x4c,0xfc,0x44,0x91,0xbf,0x79,0xed,
+  0x21,0x12,0x3f,0xf4,0x40,0xaa,0xa8,0xc4,0x7f,0x7e,0x86,0xa4,0xc5,0x43,0x18,0x7b,
+  0x14,0x20,0xc6,0x5e,0xdc,0x01,0xa2,0xa4,0xa8,0x3d,0xf8,0x21,0xf1,0x8b,0x02,0x38,
+  0x20,0x86,0xdb,0x00,0x07,0xb8,0x3f,0xa5,0xbd,0xf6,0xf4,0xe3,0xb8,0xed,0xb2,0xe3,
+  0x96,0xca,0x06,0xf0,0x56,0x5b,0xb7,0x68,0x92,0xb0,0x92,0x20,0xf0,0x87,0x4f,0x3f,
+  0xb0,0x91,0xef,0xf1,0x5b,0x6f,0xaf,0x14,0x04,0x20,0xb5,0x67,0x03,0xb2,0x41,0xe4,
+  0x87,0x83,0xda,0x06,0x25,0x66,0xff,0xcc,0xe5,0x87,0x03,0x2e,0x10,0xfc,0xd0,0x5f,
+  0xdf,0x09,0xe3,0x6f,0x0b,0xac,0xe5,0x7a,0x6c,0xbf,0x00,0xc9,0xd8,0xfe,0x9a,0xbf,
+  0x22,0x08,0x32,0xb1,0x43,0x74,0x2b,0x59,0x60,0x2e,0x1f,0xbc,0x44,0x7a,0x5f,0xd2,
+  0x87,0xb4,0xf0,0x49,0xeb,0xea,0x24,0xd9,0xaf,0x08,0x50,0xbb,0x1f,0x5c,0xe0,0x94,
+  0x48,0xfa,0x27,0xd3,0xdb,0xa7,0xb6,0x73,0xda,0x09,0x12,0xff,0xbc,0xc1,0x66,0x8c,
+  0x31,0xf1,0xf3,0x84,0xa0,0x8e,0xfa,0x5e,0x69,0xfc,0x34,0x11,0x8b,0x69,0x1b,0xc6,
+  0x87,0x0d,0x7b,0x85,0xd0,0x3f,0x9b,0x78,0x89,0xab,0x88,0xfa,0xd5,0x82,0xd7,0x43,
+  0x26,0x0e,0xe0,0x8d,0x76,0xd2,0xaa,0x19,0xd7,0xbf,0x8b,0xe0,0x52,0xab,0x26,0x49,
+  0xb6,0xab,0xbc,0x04,0x81,0xf8,0x29,0x29,0xeb,0x9f,0x5e,0x8b,0xde,0xdf,0x32,0x17,
+  0x77,0x68,0x90,0x1f,0x5d,0x4a,0x2e,0x47,0x10,0x3b,0xb6,0xe8,0x7e,0x04,0xcb,0x11,
+  0x50,0x07,0x48,0xe3,0x99,0xac,0x45,0x36,0x88,0xfd,0x8f,0xed,0xc1,0xd1,0x72,0x09,
+  0x7e,0x08,0x9c,0x1d,0x9b,0x18,0x2d,0xec,0x27,0x3b,0x04,0x51,0xec,0x97,0xf4,0x0f,
+  0x8e,0x37,0x64,0x83,0x7c,0xfc,0x7c,0x83,0xb1,0xc1,0x7c,0x5f,0x80,0x1f,0x3a,0x40,
+  0xaa,0x8f,0xf3,0xcb,0xec,0x8a,0xeb,0xbd,0x38,0x5d,0x68,0x26,0xab,0x1b,0xbd,0x1a,
+  0x72,0x29,0x13,0x41,0x0f,0x02,0x2a,0x00,0x01,0xa9,0x7f,0x70,0xbe,0x14,0xe2,0x1d,
+  0xb8,0xf3,0xa8,0xc3,0x09,0x15,0x9f,0x20,0x51,0xd2,0x0d,0x99,0x42,0x3c,0xa5,0x22,
+  0x30,0x1c,0x60,0xfa,0xcf,0x47,0x65,0xa1,0xeb,0x9c,0x1f,0xda,0x66,0x2b,0xaa,0x1d,
+  0x82,0xfc,0xd0,0x74,0x89,0xa2,0x0b,0xe4,0xf1,0x93,0x6e,0x6d,0x62,0xfc,0x50,0x1b,
+  0x57,0x5a,0x91,0x93,0x75,0xb4,0x70,0x7e,0x38,0x06,0x86,0x51,0x37,0x86,0x25,0x79,
+  0xc6,0x0f,0xc7,0xa4,0xf6,0x10,0x57,0xff,0x24,0x85,0xfe,0xe9,0x73,0xf5,0x0f,0x03,
+  0x8b,0x70,0x9c,0x2b,0x4c,0xff,0x48,0xfd,0x63,0x72,0x25,0x53,0x63,0x8e,0xe5,0x50,
+  0x7b,0x3f,0x21,0xd4,0xce,0x16,0x6d,0x9c,0xa0,0x22,0xca,0x39,0x1a,0xa9,0x4b,0x9e,
+  0x5f,0x16,0x7e,0x26,0x54,0xb5,0xd8,0x26,0x1b,0x81,0x86,0x5b,0xeb,0x63,0x70,0xaf,
+  0x86,0x5f,0x70,0x38,0x77,0x6c,0xd1,0xd2,0xda,0xb9,0x0a,0x7e,0x41,0x7f,0xbe,0x67,
+  0x80,0xc0,0x57,0xac,0xb9,0x5b,0x22,0x2c,0x8c,0x54,0xca,0x8c,0xea,0x11,0x0a,0xaf,
+  0x22,0x31,0xe3,0x60,0x9f,0x21,0x4a,0x6c,0xa9,0x3d,0xc8,0xdf,0x96,0x98,0x0d,0x99,
+  0x48,0x26,0xb7,0x13,0xda,0xcd,0x06,0x33,0x32,0x00,0x3f,0xa3,0xed,0xfd,0xd1,0x4c,
+  0x24,0x0e,0xbf,0xc0,0x12,0x06,0xf4,0xbd,0x52,0x7b,0xba,0x29,0xee,0x46,0x53,0x7d,
+  0x49,0x40,0xb5,0x33,0x99,0x4c,0xf5,0x45,0x63,0x7f,0xef,0x82,0xc7,0x5d,0x20,0xeb,
+  0x1f,0x13,0xf9,0x61,0xb2,0xe0,0x1e,0x9e,0x54,0xb2,0x23,0xfa,0xfd,0xd3,0x8f,0xfc,
+  0x50,0x43,0x7e,0x68,0xdb,0x9b,0xee,0x66,0x44,0xd1,0x88,0x8d,0x53,0x87,0x16,0x7a,
+  0x40,0x1e,0x3f,0x66,0xaf,0x1a,0x4b,0xd4,0xf4,0x22,0x5d,0xee,0xc9,0xc4,0xe2,0xb4,
+  0x97,0xc4,0x4c,0x13,0xd5,0x0e,0x15,0xfa,0x87,0x95,0x00,0x31,0xa5,0xf1,0xa3,0x31,
+  0x96,0xea,0x6a,0x3e,0x7d,0x58,0xc5,0x61,0x60,0xe0,0x30,0x18,0x16,0x1b,0x07,0x3e,
+  0x1e,0xb2,0x20,0x09,0xa3,0x85,0x90,0x37,0x83,0xfc,0x90,0x83,0x1e,0xaf,0x44,0x1e,
+  0x3f,0xb7,0x2d,0x5c,0x67,0x8e,0x4e,0x6f,0x5c,0x32,0x7e,0x5b,0xcd,0x3a,0xf3,0xd0,
+  0xb4,0xb1,0xa4,0xe1,0x36,0xb2,0xce,0x1c,0x98,0xbe,0x01,0x41,0x84,0x95,0x20,0x90,
+  0xda,0x43,0xfa,0xe9,0xb6,0xae,0x05,0x39,0x5c,0xf4,0x7f,0xf2,0xb0,0x43,0x03,0x3c,
+  0x3e,0xc0,0x01,0x2c,0x37,0x24,0xfd,0x83,0xeb,0xb5,0xcf,0x0f,0x57,0xca,0xfc,0x70,
+  0x57,0x05,0x7e,0xd8,0xe9,0xf3,0xc3,0x35,0x32,0x3f,0x3c,0xf3,0x3b,0xe2,0x87,0x57,
+  0x32,0x5a,0xf8,0xcb,0xdc,0x85,0xf3,0x9d,0xe7,0x38,0x51,0x44,0x7e,0xf8,0x44,0x6d,
+  0x90,0x1f,0x9e,0x90,0xeb,0xf3,0xff,0xfd,0xc3,0x13,0x58,0xff,0x13,0x4e,0x14,0x91,
+  0x1f,0x3e,0x50,0xc4,0x0f,0x03,0xed,0x59,0xe6,0xf2,0xc3,0x85,0x97,0xdf,0x7e,0x74,
+  0x47,0x3b,0x23,0x96,0xf7,0x17,0xd5,0x3f,0xfe,0xe9,0x5b,0x9f,0x02,0x83,0xe0,0xfc,
+  0xc6,0x7f,0xbb,0xa3,0x9f,0xfe,0x29,0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0x4a,
+  0x28,0xa1,0x84,0x12,0xca,0xef,0xbb,0xf0,0xbd,0x03,0x0d,0xf7,0x0e,0xa1,0x84,0x12,
+  0x4a,0x28,0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0x4a,0x75,0xe1,0x7b,0x87,0x9a,
+  0x70,0xef,0x10,0x4a,0x28,0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0x4a,0x28,0xa1,
+  0x54,0x17,0xbe,0x77,0xd0,0xf8,0xde,0xe1,0xff,0xba,0x29,0xa1,0x84,0x12,0x4a,0x28,
+  0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0xca,0x17,0x28,0x29,0x16,0x72,0x19,0x5e,
+  0xf9,0x20,0x05,0x36,0xf3,0x62,0x8a,0xa4,0xc0,0xbc,0xe8,0xf3,0x04,0xe7,0x6f,0xd5,
+  0x14,0xe4,0x89,0xff,0xcc,0xe3,0x77,0x15,0xd7,0xfb,0x5f,0x2b,0x92,0xad,0x46,0xf1,
+  0x33,0x01,0x00,
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
new file mode 100644
index 0000000..1ba6d17
--- /dev/null
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c
new file mode 100644
index 0000000..3cdbaa9
--- /dev/null
+++ b/board/dave/common/flash.c
@@ -0,0 +1,681 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	/* set up sector start address table */
+        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+        } else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+        int k;
+        int size;
+        int erased;
+        volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("ST  ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_STMW320DT:	printf ("M29W320DT (32 M, top sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+                /*
+                 * Check if whole sector is erased
+                 */
+                if (i != (info->sector_count-1))
+                  size = info->start[i+1] - info->start[i];
+                else
+                  size = info->start[0] + info->size - info->start[i];
+                erased = 1;
+                flash = (volatile unsigned long *)info->start[i];
+                size = size >> 2;        /* divide by 4 for longword access */
+                for (k=0; k<size; k++)
+                  {
+                    if (*flash++ != 0xffffffff)
+                      {
+                        erased = 0;
+                        break;
+                      }
+                  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+                /* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+        volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CFG_FLASH_READ0];
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+	        info->flash_id += FLASH_STMW320DT;
+	        info->sector_count = 67;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+	        info->flash_id += FLASH_AM320T;
+	        info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+	        info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+	        info->flash_id += FLASH_AMDL322T;
+	        info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+	        info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+	        info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+	        info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+	        info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;  break;	/* => 8 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+        } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+                /*  1 x 16k boot sector */
+		base -= 16 << 10;
+                --i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n=0; n<2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+                /*  1 x 32k boot sector */
+		base -= 32 << 10;
+                --i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+        } else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+                if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+                  info->protect[i] = 0;
+                else
+                  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+        int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+                    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+                        addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+                        addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+                        addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+                        for (i=0; i<50; i++)
+                          udelay(1000);  /* wait 1 ms */
+                    } else {
+                        if (sect == s_first) {
+                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+                            addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+                            addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+                        }
+                        addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+                    }
+		    l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+        volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+        volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+        volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+        int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
+             (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+        for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+          {
+            addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+            addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+            addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+            dest2[i] = data2[i];
+
+            /* re-enable interrupts if necessary */
+            if (flag)
+              enable_interrupts();
+
+            /* data polling for D7 */
+            start = get_timer (0);
+            while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+                   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+              if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+                return (1);
+              }
+            }
+          }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c
new file mode 100644
index 0000000..9547325
--- /dev/null
+++ b/board/dave/common/fpga.c
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2001-2003
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES               226
+
+#ifdef CFG_FPGA_PRG
+# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CFG_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CFG_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CFG_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CFG_FPGA_INIT /* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000  /* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000  /* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000  /* FPGA init pin (ppc input)     */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+
+#define SET_FPGA(data)         out32(GPIO0_OR, data)
+
+#define FPGA_WRITE_1 {                                                    \
+        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+        SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+        SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#if 0
+static int fpga_boot (unsigned char *fpgadata, int size)
+{
+	int i, index, len;
+	int count;
+
+#ifdef CFG_FPGA_SPARTAN2
+	int j;
+#else
+	unsigned char b;
+	int bit;
+#endif
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+#ifdef CFG_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	DBG ("FPGA: configdata starts at position 0x%x\n", index);
+	DBG ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	out32 (GPIO0_ODR, 0x00000000);	/* no open drain pins */
+	out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* setup for output */
+	out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* set pins to high */
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (in32 (GPIO0_IR) & FPGA_INIT) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	DBG ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CFG_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+		for (j = 0; j < 8; j++) {
+			if ((fpgadata[i] & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			fpgadata[i] <<= 1;
+		}
+	}
+#else	/* ! CFG_FPGA_SPARTAN2 */
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif	/* CFG_FPGA_SPARTAN2 */
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG ("FPGA: Booting successful!\n");
+	return 0;
+}
+#endif	/* 0 */
diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c
new file mode 100644
index 0000000..f8f180c
--- /dev/null
+++ b/board/dave/common/pci.c
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
+
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_read_config_dword
+|  Description: Read a PCI configuration register
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               value           Address of the configuration register value
+|  Return value:
+|               0               Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+  unsigned long      conAdrVal;
+  unsigned long      val;
+
+  /* generate coded value for CON_ADR register */
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  /* Note: *pResult comes back as -1 if machine check happened */
+  val = in32r(PCI_PRIMARY_CDR);
+
+  *value = (unsigned long) val;
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  if ((*(unsigned long *)0x50000304) & 0x60000000)
+    {
+      /* clear pci master/target abort bits */
+      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_write_config_dword
+|  Description: Write a PCI configuration register.
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               Value           Configuration register value
+|  Return value:
+|               0               Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 value)
+{
+  unsigned long      conAdrVal;
+
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  out32r(PCI_PRIMARY_CDR, value);
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  /* clear pci master/target abort bits */
+  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+					struct pci_config_table *_)
+{
+  unsigned int iobase;
+  unsigned short status = 0;
+  unsigned char timer;
+
+  /*
+   * Configure PLX PCI9054
+   */
+  pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+  pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+  /* Check the latency timer for values >= 0x60.
+   */
+  pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  if (timer < 0x60)
+    {
+      pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+    }
+
+  /* Set I/O base register.
+   */
+  pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
+  pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+  pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  if (pci9054_iobase == 0xffffffff)
+    {
+      printf("Error: Can not set I/O base register.\n");
+      return;
+    }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
+				 CFG_ETH_IOBASE,
+				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
+    pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+  { }
+};
+
+static struct pci_controller pci9054_hose = {
+  config_table: pci9054_config_table,
+};
+
+void pci_init(void)
+{
+  struct pci_controller *hose = &pci9054_hose;
+
+  /*
+   * Register the hose
+   */
+  hose->first_busno = 0;
+  hose->last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(hose->regions + 0,
+		 0x00000000, 0x00000000, 0x01000000,
+		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+  /* PCI Memory space */
+  pci_set_region(hose->regions + 1,
+		 0x00000000, 0xc0000000, 0x10000000,
+		 PCI_REGION_MEM);
+
+  pci_set_ops(hose,
+	      pci_hose_read_config_byte_via_dword,
+	      pci_hose_read_config_word_via_dword,
+	      pci9054_read_config_dword,
+	      pci_hose_write_config_byte_via_dword,
+	      pci_hose_write_config_word_via_dword,
+	      pci9054_write_config_dword);
+
+  hose->region_count = 2;
+
+  pci_register_hose(hose);
+
+  hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
index 4f3032e..99717be 100644
--- a/board/evb64260/evb64260.c
+++ b/board/evb64260/evb64260.c
@@ -237,7 +237,7 @@ int board_pre_init (void)
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-#ifdef CONFIG_ZUMA_V2
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
 	/* Zuma has no SRAM */
 	sram_boot = 0;
 #else
@@ -265,6 +265,7 @@ int board_pre_init (void)
 	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
 #endif
 
+#ifdef CONFIG_EVB64260
 #ifdef CFG_32BIT_BOOT_PAR
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
@@ -280,6 +281,11 @@ int board_pre_init (void)
 	/* 8 bit boot flash only */
 	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
 #endif
+#else /* CONFIG_EVB64260 not defined */
+		/* We are booting from 16-bit flash.
+		 */
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR);
+#endif
 
 	gt_cpu_config();
 
@@ -351,7 +357,7 @@ checkboard (void)
 void
 debug_led(int led, int mode)
 {
-#ifndef CONFIG_ZUMA_V2
+#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
 	volatile int *addr = NULL;
 	int dummy;
 
diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
index c897393..e6cf8eb 100644
--- a/board/evb64260/flash.c
+++ b/board/evb64260/flash.c
@@ -54,6 +54,7 @@ flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
 static int write_word (flash_info_t *info, ulong dest, ulong data);
 static void flash_get_offsets (ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
 
 /*-----------------------------------------------------------------------
  */
@@ -72,7 +73,11 @@ flash_init (void)
 
 	/* the boot flash */
 	base = CFG_FLASH_BASE;
-	size_b0 = flash_get_size(1, (vu_long *)base, &flash_info[0]);
+#ifndef CFG_BOOT_FLASH_WIDTH
+#define CFG_BOOT_FLASH_WIDTH	1
+#endif
+	size_b0 = flash_get_size(CFG_BOOT_FLASH_WIDTH, (vu_long *)base,
+	                         &flash_info[0]);
 
 	printf("[%ldkB@%lx] ", size_b0/1024, base);
 
@@ -98,6 +103,22 @@ flash_init (void)
 	    base+=size;
 	}
 
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+	              CFG_MONITOR_BASE,
+	              CFG_MONITOR_BASE + monitor_flash_len - 1,
+	              flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef  CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+	              CFG_ENV_ADDR,
+	              CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+	              flash_get_info(CFG_ENV_ADDR));
+#endif
+
 	flash_size = size_b0 + size_b1;
 	return flash_size;
 }
@@ -148,6 +169,23 @@ flash_get_offsets (ulong base, flash_info_t *info)
 
 /*-----------------------------------------------------------------------
  */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
 void
 flash_print_info  (flash_info_t *info)
 {
@@ -247,8 +285,11 @@ static inline void flash_cmd(int width, volatile unsigned char *addr, int offset
 	    /* 2x16 */
 	    unsigned long cmd32=(cmd<<16)|cmd;
 	    *(volatile unsigned long *)(addr+offset*2)=cmd32;
+	} else if (width == 2) {
+	    /* 1x16 */
+	    *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd;
 	} else {
-	    /* 1x16 or 1x8 */
+	    /* 1x8 */
 	    *(volatile unsigned char *)(addr+offset)=cmd;
 	}
 }
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index 718fe05..ee623ca 100644
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -273,7 +273,7 @@ mpsc_init(int baud)
 
 	/* BRG CONFIG */
 	galbrg_set_baudrate(CHANNEL, baud);
-#ifdef CONFIG_ZUMA_V2
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
 	galbrg_set_clksrc(CHANNEL,0x8);	/* connect TCLK -> BRG */
 #else
 	galbrg_set_clksrc(CHANNEL,0);
@@ -387,7 +387,7 @@ galbrg_set_baudrate(int channel, int rate)
 
 	galbrg_disable(channel);
 
-#ifdef CONFIG_ZUMA_V2
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
 	/* from tclk */
 	clock = (CFG_BUS_HZ/(16*rate)) - 1;
 #else
@@ -803,6 +803,7 @@ static int
 galmpsc_shutdown(int mpsc)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+#if 0
 	unsigned int temp;
 
 	/* cause RX abort (clears RX) */
@@ -810,9 +811,11 @@ galmpsc_shutdown(int mpsc)
 	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
 	temp &= ~MPSC_ENTER_HUNT;
 	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp);
+#endif
 
-	GT_REG_WRITE(GALSDMA_0_COM_REG, 0);
-	GT_REG_WRITE(GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
+	             SDMA_TX_ABORT | SDMA_RX_ABORT);
 
 	/* shut down the MPSC */
 	GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
@@ -823,14 +826,15 @@ galmpsc_shutdown(int mpsc)
 
 	/* shut down the sdma engines. */
 	/* reset config to default */
-	GT_REG_WRITE(GALSDMA_0_CONF_REG, 0x000000fc);
+	GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
+	             0x000000fc);
 
 	udelay(100);
 
 	/* clear the SDMA current and first TX and RX pointers */
-	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR, 0);
-	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR, 0);
-	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR, 0);
+	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
 
 	udelay(100);
 
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
index 3616565..d019d22 100644
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -175,7 +175,30 @@ check_dimm(uchar slot, sdram_info_t *info)
 	return 0;
 }
 
-#else /* ! CONFIG_ZUMA_V2 */
+#elif defined(CONFIG_P3G4)
+
+static int
+check_dimm(uchar slot, sdram_info_t *info)
+{
+	memset(info, 0, sizeof(*info));
+
+	if (slot)
+		return 0;
+
+	info->slot = slot;
+	info->banks = 1;
+	info->registered = 0;
+	info->drb_size = 4;
+	info->tpar = 3;
+	info->tras_clocks = 6;
+	info->burst_len = 4;
+#ifdef CONFIG_ECC
+	info->ecc = 2;
+#endif
+	return 0;
+}
+
+#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4*/
 
 /* This code reads the SPD chip on the sdram and populates
  * the array which is passed in with the relevant information */
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index f1adeaa..dd9a489 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -81,7 +81,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
-#ifdef CONFIG_PN62
+#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB)
 	printf ("\neth1addr    =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index ec76aa3..26cbe5d 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -520,7 +520,7 @@ static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
 	else
 		udelay(10);
 #else	/* has functional r/b signal */
-    NAND_WAIT_READY(nand);
+	NAND_WAIT_READY(nand);
 #endif
 	return ret;
 }
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index b01e44c..557355f 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -809,9 +809,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 {
 	mpc5xxx_fec_priv *fec;
 	struct eth_device *dev;
+	char *tmp, *end;
+	char env_enetaddr[6];
+	int i;
 
 	fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
 	dev = (struct eth_device *)malloc(sizeof(*dev));
+   	memset(dev, 0, sizeof *dev);
 
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
@@ -830,6 +834,21 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	sprintf(dev->name, "FEC ETHERNET");
 	eth_register(dev);
 
+	/*
+	 * Try to set the mac address now. The fec mac address is
+	 * a garbage after reset. When not using fec for booting 
+	 * the Linux fec driver will try to work with this garbage.
+	 */
+	tmp = getenv("ethaddr");
+	if (tmp) {
+		for (i=0; i<6; i++) {
+			env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+			if (tmp)
+				tmp = (*end) ? end+1 : end;
+		}
+		mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
+	}
+
 	return 1;
 }
 
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 1d7c0c9..ab9b2e5 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -50,15 +50,15 @@ int checkcpu (void)
 {
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_405CR) || \
-    defined(CONFIG_IOP480) || \
-    defined(CONFIG_440) || \
-    defined(CONFIG_405EP)
+    defined(CONFIG_405EP) || \
+    defined(CONFIG_440)   || \
+    defined(CONFIG_IOP480)
 	uint pvr = get_pvr();
 #endif
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_405CR) || \
-    defined(CONFIG_IOP480) || \
-    defined(CONFIG_405EP)
+    defined(CONFIG_405EP) || \
+    defined(CONFIG_IOP480)
 	DECLARE_GLOBAL_DATA_PTR;
 
 	ulong clock = gd->cpu_clk;
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index 0606ebe..e719a33 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -101,6 +101,7 @@ int miiphy_read (unsigned char addr, unsigned char reg,
 	sta_reg = reg;				/* reg address */
 	/* set clock (50Mhz) and read flags */
 	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
 	sta_reg = sta_reg | (addr << 5);	/* Phy address */
 
 	out32 (EMAC_STACR, sta_reg);
@@ -156,6 +157,7 @@ int miiphy_write (unsigned char addr, unsigned char reg,
 	sta_reg = reg;				/* reg address */
 	/* set clock (50Mhz) and read flags */
 	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
 	sta_reg = sta_reg | ((unsigned long) addr << 5);	/* Phy address */
 	memcpy (&sta_reg, &value, 2);	/* put in data */
 
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index e3e92af..215a925 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -702,7 +702,8 @@ _start:
 	/* NEVER RETURNS! */
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 
-#endif	/* CONFIG_405GP || CONFIG_405CR */
+#endif	/* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
+	/*----------------------------------------------------------------------- */
 
 
 /*****************************************************************************/
diff --git a/drivers/pci.c b/drivers/pci.c
index b9a1b9a..c91c992 100644
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -428,7 +428,7 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 	     dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 	     dev += PCI_BDF(0,0,1))
 	{
-#ifndef CONFIG_405GP /* don't skip host bridge on ppc405gp */
+#if ((!defined(CONFIG_405GP)) && (!defined(CONFIG_405EP)))	/* don't skip host bridge on ppc405gp and 405ep */
 		/* Skip our host bridge */
 		if ( dev == PCI_BDF(hose->first_busno,0,0) )
 			continue;
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 8ebaa17..f17a764 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -60,7 +60,7 @@ typedef	struct	global_data {
 	unsigned int	dp_alloc_base;
 	unsigned int	dp_alloc_top;
 #endif
-#if defined(CONFIG_EVB64260)
+#if defined(CFG_GT_6426x)
 	unsigned int	mirror_hack[16];
 #endif
 #if defined(CONFIG_SANDPOINT) ||  \
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 726102d..feaff94 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -494,6 +494,7 @@
 #define	PVR_405CR_RA	0x40110041
 #define	PVR_405CR_RB	0x401100C5
 #define	PVR_405CR_RC	0x40110145  /* same as pc405gp rev e */
+#define	PVR_405EP_RA	0x51210950
 #define	PVR_405GPR_RB	0x50910951
 #define	PVR_440GP_RB	0x40120440
 #define	PVR_440GP_RC	0x40120481
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 8014225..9f861ac 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -61,11 +61,11 @@ typedef struct bd_info {
 	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
 #endif
 	unsigned long	bi_baudrate;	/* Console Baudrate */
-#if defined(CONFIG_405GP) || \
+#if defined(CONFIG_405)   || \
+    defined(CONFIG_405GP) || \
     defined(CONFIG_405CR) || \
-    defined(CONFIG_440)   || \
-    defined(CONFIG_405)   || \
-    defined(CONFIG_405EP)
+    defined(CONFIG_405EP) || \
+    defined(CONFIG_440)
 	unsigned char	bi_s_version[4];	/* Version of this structure */
 	unsigned char	bi_r_version[32];	/* Version of the ROM (IBM) */
 	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
@@ -76,14 +76,15 @@ typedef struct bd_info {
 #if defined(CONFIG_HYMOD)
 	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
 #endif
-#if defined(CONFIG_EVB64260)	|| \
-    defined(CONFIG_PN62)	|| \
-    defined(CONFIG_SXNI855T)	|| \
+#if defined(CFG_GT_6426x)		|| \
+    defined(CONFIG_PN62)		|| \
+    defined(CONFIG_PPCHAMELEONEVB)	|| \
+    defined(CONFIG_SXNI855T)		|| \
     defined(CONFIG_SVM_SC8xx)
 	/* second onboard ethernet port */
 	unsigned char   bi_enet1addr[6];
 #endif
-#if defined(CONFIG_EVB64260) || defined(CONFIG_SVM_SC8xx)
+#if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx)
 	/* third onboard ethernet port */
 	unsigned char	bi_enet2addr[6];
 #endif
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
new file mode 100644
index 0000000..d7bfe81
--- /dev/null
+++ b/include/configs/P3G4.h
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/processor.h>
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+#include "../board/evb64260/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_P3G4		1	/* this is a P3G4  board	*/
+#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+
+#define CONFIG_BAUDRATE		115200 	/* console baudrate = 115200	*/
+
+#undef	CONFIG_ECC			/* enable ECC support */
+/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_BOARD_PRE_INIT	1
+
+#define CFG_BOARD_NAME		"P3G4"
+
+#undef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define	CONFIG_MPSC
+#define CONFIG_MPSC_PORT	1
+
+#define CONFIG_NET_MULTI        /* attempt all available adapters */
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND						     \
+	"bootp && " 						     \
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
+	"ip=$ipaddr:$serverip:$gatewayip:" \
+	"$netmask:$hostname:eth0:none; && " \
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ASKENV)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CFG_BUS_HZ		133000000	/* 133 MHz		*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define	CFG_INIT_RAM_END	0x1000
+#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_LOCK
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xff800000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		1
+#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+#define CFG_GT_REGS		0xf8000000
+#define CFG_DEV_BASE		0xff000000
+
+#define CFG_DEV0_SPACE		CFG_DEV_BASE
+#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
+#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
+#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+
+#define CFG_DEV0_SIZE		 _8M /* Flash bank */
+#define CFG_DEV1_SIZE		 0   /* unused */
+#define CFG_DEV2_SIZE		 0   /* unused */
+#define CFG_DEV3_SIZE		 0   /* unused */
+
+#define CFG_16BIT_BOOT_PAR	0xc01b5e7c
+#define CFG_DEV0_PAR		CFG_16BIT_BOOT_PAR
+
+#if 0 /* Wrong?? NTL */
+#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* DMAAck[1:0] GNT0[1:0] */
+#else
+#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* REQ0[1:0] GNT0[1:0] */
+#endif
+#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+						/* DMAReq[4] DMAAck[4] WDNMI WDE */
+#if 0 /* Wrong?? NTL */
+#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+						/* DMAAck[1:0] GNT1[1:0] */
+#else
+#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+						/* GPP[22] (RS232IntB or PCI1Int) */
+						/* GPP[21] (RS323IntA) */
+						/* BClkIn */
+						/* REQ1[1:0] GNT1[1:0] */
+#endif
+
+#if 0 /* Wrong?? NTL */
+# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+						/* GPP[27:26] Int[1:0] */
+#else
+# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+						/* GPP[29]    (PCI1Int) */
+						/* BClkOut0 */
+						/* GPP[27]    (PCI0Int) */
+						/* GPP[26]    (RtcInt or PCI1Int) */
+						/* CPUInt[25:24] */
+#endif
+
+#define CFG_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
+
+#if 0 /* Wrong?? - NTL */
+# define CFG_GPP_LEVEL_CONTROL	0x000002c6
+#else
+# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+						/* gpp[29] */
+						/* gpp[27:26] */
+						/* gpp[22:21] */
+
+# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+				/* idmas use buffer 1,1
+				   comm use buffer 0
+				   pci use buffer 1,1
+				   cpu use buffer 0
+				   normal load (see also ifdef HVL)
+				   standard SDRAM (see also ifdef REG)
+				   non staggered refresh */
+				/* 31:26  25 23  20 19 18 16 */
+				/* 110110 00 111 0  0  00 1 */
+				/* refresh_count=0x200
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 1  0  0x200 */
+#endif
+
+#if 0
+#define CFG_DUART_IO		CFG_DEV2_SPACE
+#define CFG_DUART_CHAN		1		/* channel to use for console */
+#endif
+#undef CFG_INIT_CHAN1
+#undef CFG_INIT_CHAN2
+#if 0
+#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                      /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* I2C speed and slave address (for compatability) defaults */
+#define CFG_I2C_SPEED	400000
+#define CFG_I2C_SLAVE	0x7F
+
+/* I2C addresses for the two DIMM SPD chips */
+#ifndef CONFIG_EVB64260_750CX
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
+#define DIMM0_I2C_ADDR  0x54
+#define DIMM1_I2C_ADDR	0x54
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CFG_EXTRA_FLASH_DEVICE	DEVICE0	/* extra flash at device 0 */
+#define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_CFI		1
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		0xFFFE0000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT      1
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
new file mode 100644
index 0000000..967a2d0
--- /dev/null
+++ b/include/configs/PPChameleonEVB.h
@@ -0,0 +1,734 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Debug stuff
+ */
+#undef __DEBUG_START_FROM_SRAM__
+#define __DISABLE_MACHINE_EXCEPTION__
+
+#ifdef __DEBUG_START_FROM_SRAM__
+#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board 	*/
+
+#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#if 1
+#define CONFIG_BAUDRATE		9600
+#else
+#define CONFIG_BAUDRATE		115200
+#endif
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#if 0
+#define CONFIG_PREBOOT                                                          \
+        "crc32 f0207004 ffc 0;"                                                 \
+        "if cmp 0 f0207000 1;"                                                  \
+        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+        "else;echo Old CRC is bad;fi"
+#endif
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND							\
+	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
+	"bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND							\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
+	"bootm ffc00000"
+
+#define CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND				\
+	"setenv ipaddr 192.168.10.203;"						\
+    "setenv serverip 192.168.10.6;"						\
+	"setenv netmask 255.255.255.0;"						\
+	"setenv bootargs root=/dev/ram rw console=ttyS0,9600;"			\
+	"setenv autostart yes;"							\
+	"bootm ffc00000 ffd00000"
+/*
+	"setenv ethaddr 00:50:c2:1e:af:fe;"						\
+	"setenv eth1addr 00:50:c2:1e:af:fd;"						\
+*/
+
+#define CONFIG_BOOTCOMMAND CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+
+/* EThernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
+#define CONFIG_ETH1ADDR	00:50:c2:1e:af:fd
+
+#undef CONFIG_EXT_PHY
+/*#define CONFIG_EXT_PHY*/
+#define CONFIG_MII		1	/* MII PHY management		*/
+#ifndef  CONFIG_EXT_PHY
+#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
+#else
+#define	CONFIG_PHY_ADDR		2	/* PHY address			*/
+#endif
+#define	CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+#if 0 /* test-only */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM  )
+#else
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_MII		| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM  )
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+
+#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NAND0_BASE 0xFF400000
+#define CFG_NAND1_BASE 0xFF000000
+
+#define CFG_MAX_NAND_DEVICE	2	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND0_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
+#define CFG_NAND0_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
+#define CFG_NAND0_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+
+#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+        { \
+            case CFG_NAND0_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+                break; \
+            case CFG_NAND1_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+                break; \
+        } \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+        { \
+            case CFG_NAND0_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+                break; \
+            case CFG_NAND1_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+                break; \
+        } \
+} while(0)
+
+
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+        { \
+            case CFG_NAND0_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+                break; \
+            case CFG_NAND1_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+                break; \
+        } \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+        { \
+            case CFG_NAND0_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+                break; \
+            case CFG_NAND1_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+                break; \
+        } \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+        { \
+            case CFG_NAND0_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+                break; \
+            case CFG_NAND1_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+                break; \
+        } \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do { \
+	switch((unsigned long)nandptr) { \
+        case CFG_NAND0_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+                break; \
+        case CFG_NAND1_BASE: \
+                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+                break; \
+        } \
+} while(0)
+
+#define NAND_WAIT_READY(nand) do { \
+	ulong mask = 0; \
+	switch ((ulong)(((struct nand_chip *)nand)->IO_ADDR)) { \
+	case CFG_NAND0_BASE: \
+		mask = CFG_NAND0_RDY; \
+		break; \
+	case CFG_NAND1_BASE: \
+		mask = CFG_NAND1_RDY; \
+		break; \
+	} \
+	while (!(in32(GPIO0_IR) & mask)) \
+		; \
+} while (0)
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
+                                        /* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+                                   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
+                                        /* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
+#define CFG_EBC_PB0AP           0x92015480
+#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (External SRAM) initialization                      		*/
+/* Since this must replace NOR Flash, we use the same settings for CS0		*/
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
+#define CFG_EBC_PB2AP           0x92015480
+#define CFG_EBC_PB2CR           0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
+#define CFG_EBC_PB3AP           0x92015480
+#define CFG_EBC_PB3CR           0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
+
+
+#if 0 /* Roese */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xFF858000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (CAN0, 1) initialization                                       */
+#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (CompactFlash IDE) initialization                              */
+#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
+#define CFG_EBC_PB4AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
+#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE           0x00
+#define CFG_FPGA_STATUS         0x02
+#define CFG_FPGA_TS             0x04
+#define CFG_FPGA_TS_LOW         0x06
+#define CFG_FPGA_TS_CAP0        0x10
+#define CFG_FPGA_TS_CAP0_LOW    0x12
+#define CFG_FPGA_TS_CAP1        0x14
+#define CFG_FPGA_TS_CAP1_LOW    0x16
+#define CFG_FPGA_TS_CAP2        0x18
+#define CFG_FPGA_TS_CAP2_LOW    0x1a
+#define CFG_FPGA_TS_CAP3        0x1c
+#define CFG_FPGA_TS_CAP3_LOW    0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET  0x0001
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR  0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0    0x0001
+#define CFG_FPGA_STATUS_DIP1    0x0002
+#define CFG_FPGA_STATUS_DIP2    0x0004
+#define CFG_FPGA_STATUS_FLASH   0x0008
+#define CFG_FPGA_STATUS_TS_IRQ  0x1000
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#if 0 /* test-only */
+#define CFG_INIT_DCACHE_CS      4       /* use cs # 4 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
+#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#else
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#endif
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30]    - EMAC0 input
+ * GPIO0[31]    - EMAC1 reject packet as output
+ */
+#define CFG_GPIO0_OSRH          0x40000550
+#define CFG_GPIO0_OSRL          0x00000110
+#define CFG_GPIO0_ISR1H         0x00000000
+/*#define CFG_GPIO0_ISR1L         0x15555445*/
+#define CFG_GPIO0_ISR1L         0x15555444
+#define CFG_GPIO0_TSRH          0x00000000
+#define CFG_GPIO0_TSRL          0x00000000
+#define CFG_GPIO0_TCR           0xF7FF8014
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if 1 /* test-only */
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+/*----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+
+/*
+!-------------------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!       are plugged in the board will be utilized as non-ECC DIMMs.
+!-------------------------------------------------------------------------------
+*/
+#undef        AUTO_MEMORY_CONFIG
+#define        DIMM_READ_ADDR 0xAB
+#define        DIMM_WRITE_ADDR 0xAA
+
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE                 0x80000000
+#define CPC0_PLLMR1_SSCS           0x80000000
+#define PLL_RESET                  0x40000000
+#define CPC0_PLLMR1_PLLR           0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV                 0x00F00000
+#define CPC0_PLLMR1_FBDV           0x00F00000
+#define PLL_FBKDIV_16              0x00000000
+#define PLL_FBKDIV_1               0x00100000
+#define PLL_FBKDIV_2               0x00200000
+#define PLL_FBKDIV_3               0x00300000
+#define PLL_FBKDIV_4               0x00400000
+#define PLL_FBKDIV_5               0x00500000
+#define PLL_FBKDIV_6               0x00600000
+#define PLL_FBKDIV_7               0x00700000
+#define PLL_FBKDIV_8               0x00800000
+#define PLL_FBKDIV_9               0x00900000
+#define PLL_FBKDIV_10              0x00A00000
+#define PLL_FBKDIV_11              0x00B00000
+#define PLL_FBKDIV_12              0x00C00000
+#define PLL_FBKDIV_13              0x00D00000
+#define PLL_FBKDIV_14              0x00E00000
+#define PLL_FBKDIV_15              0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA                0x00070000
+#define CPC0_PLLMR1_FWDVA          0x00070000
+#define PLL_FWDDIVA_8              0x00000000
+#define PLL_FWDDIVA_7              0x00010000
+#define PLL_FWDDIVA_6              0x00020000
+#define PLL_FWDDIVA_5              0x00030000
+#define PLL_FWDDIVA_4              0x00040000
+#define PLL_FWDDIVA_3              0x00050000
+#define PLL_FWDDIVA_2              0x00060000
+#define PLL_FWDDIVA_1              0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB                0x00007000
+#define CPC0_PLLMR1_FWDVB          0x00007000
+#define PLL_FWDDIVB_8              0x00000000
+#define PLL_FWDDIVB_7              0x00001000
+#define PLL_FWDDIVB_6              0x00002000
+#define PLL_FWDDIVB_5              0x00003000
+#define PLL_FWDDIVB_4              0x00004000
+#define PLL_FWDDIVB_3              0x00005000
+#define PLL_FWDDIVB_2              0x00006000
+#define PLL_FWDDIVB_1              0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK            0x000003FF
+#define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
+#define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
+#define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
+#define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
+#define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
+#define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
+#define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV                 0x00300000
+#define CPC0_PLLMR0_CCDV           0x00300000
+#define PLL_CPUDIV_1               0x00000000
+#define PLL_CPUDIV_2               0x00100000
+#define PLL_CPUDIV_3               0x00200000
+#define PLL_CPUDIV_4               0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV                 0x00030000
+#define CPC0_PLLMR0_CBDV           0x00030000
+#define PLL_PLBDIV_1               0x00000000
+#define PLL_PLBDIV_2               0x00010000
+#define PLL_PLBDIV_3               0x00020000
+#define PLL_PLBDIV_4               0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV                 0x00003000
+#define CPC0_PLLMR0_OPDV           0x00003000
+#define PLL_OPBDIV_1               0x00000000
+#define PLL_OPBDIV_2               0x00001000
+#define PLL_OPBDIV_3               0x00002000
+#define PLL_OPBDIV_4               0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV              0x00000300
+#define CPC0_PLLMR0_EPDV           0x00000300
+#define PLL_EXTBUSDIV_2            0x00000000
+#define PLL_EXTBUSDIV_3            0x00000100
+#define PLL_EXTBUSDIV_4            0x00000200
+#define PLL_EXTBUSDIV_5            0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV                 0x00000030
+#define CPC0_PLLMR0_MPDV           0x00000030
+#define PLL_MALDIV_1               0x00000000
+#define PLL_MALDIV_2               0x00000010
+#define PLL_MALDIV_3               0x00000020
+#define PLL_MALDIV_4               0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV                 0x00000003
+#define CPC0_PLLMR0_PPFD           0x00000003
+#define PLL_PCIDIV_1               0x00000000
+#define PLL_PCIDIV_2               0x00000001
+#define PLL_PCIDIV_3               0x00000002
+#define PLL_PCIDIV_4               0x00000003
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+! assuming a 33.3MHz input clock to the 405EP.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
+                              PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+                              PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
+                              PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+                              PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+                              PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+                              PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+                              PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+                              PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
+                              PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#if 0 /* test-only */
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#endif
+#if 0 /* test-only */
+#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#endif
+#if 1 /* test-only */
+#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#endif
+
+#endif
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 8308969..5cf74a2 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -722,7 +722,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	load_sernum_ethaddr ();
 #endif
 
-#if defined(CFG_GT_6426x) || defined(CONFIG_PN62)
+#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB)
 	/* handle the 2nd ethernet address */
 
 	s = getenv ("eth1addr");