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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-10-23 01:47:38 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-10-24 15:10:47 -0500 |
| commit | 0f060c3bf82832331a509f2e5d2442539e7aad09 (patch) | |
| tree | 08d890ed38595a17dc4b126847a7dce31c69cd5d | |
| parent | a38a5b6edd30f29fd5fdb1d7f674521906c0e677 (diff) | |
| download | u-boot-imx-0f060c3bf82832331a509f2e5d2442539e7aad09.zip u-boot-imx-0f060c3bf82832331a509f2e5d2442539e7aad09.tar.gz u-boot-imx-0f060c3bf82832331a509f2e5d2442539e7aad09.tar.bz2 | |
85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 4 | ||||
| -rw-r--r-- | cpu/mpc85xx/release.S | 8 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 2 | ||||
| -rw-r--r-- | include/asm-ppc/cache.h | 2 |
4 files changed, 16 insertions, 0 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b8f9125..c780687 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -134,6 +134,10 @@ int checkcpu (void) puts("Unknown"); break; } + + if (PVR_MEM(pvr) == 0x03) + puts("MC"); + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index ec5e4da..7c3e8a1 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -24,14 +24,18 @@ __secondary_start_page: /* First do some preliminary setup */ lis r3, HID0_EMCP@h /* enable machine check */ +#ifndef CONFIG_E500MC ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#endif #ifdef CONFIG_PHYS_64BIT ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ #endif mtspr SPRN_HID0,r3 +#ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr SPRN_HID1,r3 +#endif /* Enable branch prediction */ li r3,0x201 @@ -64,7 +68,11 @@ __secondary_start_page: /* r10 has the base address for the entry */ mfspr r0,SPRN_PIR +#ifdef CONFIG_E500MC + rlwinm r4,r0,27,27,31 +#else mr r4,r0 +#endif slwi r8,r4,5 add r10,r3,r8 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index f16d4c0..651ff1c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -163,8 +163,10 @@ _start_e500: ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0 +#ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0 +#endif /* Enable Branch Prediction */ #if defined(CONFIG_BTB) diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 7252be7..53e8d05 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -12,6 +12,8 @@ #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 +#elif defined(CONFIG_E500MC) +#define L1_CACHE_SHIFT 6 #else #define L1_CACHE_SHIFT 5 #endif |