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| author | Marian Balakowicz <m8@semihalf.com> | 2005-11-27 20:15:41 +0100 |
|---|---|---|
| committer | Marian Balakowicz <m8@semihalf.com> | 2005-11-27 20:15:41 +0100 |
| commit | 0a69b26ed6fe3184cab86872589c27b076e6cb8e (patch) | |
| tree | 8e1c16f232bc41516985dc8101b426220d67fae0 | |
| parent | f08abe311b41633b550520de50d4c0ff1fbf2800 (diff) | |
| download | u-boot-imx-0a69b26ed6fe3184cab86872589c27b076e6cb8e.zip u-boot-imx-0a69b26ed6fe3184cab86872589c27b076e6cb8e.tar.gz u-boot-imx-0a69b26ed6fe3184cab86872589c27b076e6cb8e.tar.bz2 | |
Increase IPB and PCI clocks for O2DNT board.
| -rw-r--r-- | include/configs/o2dnt.h | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 325f654..981651a 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -137,8 +137,20 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif #endif + /* * I2C configuration */ @@ -263,7 +275,16 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 + +#ifdef CFG_PCISPEED_66 +/* + * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). + */ +#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ +#endif + #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE |