diff options
author | wdenk <wdenk> | 2004-03-25 19:29:38 +0000 |
---|---|---|
committer | wdenk <wdenk> | 2004-03-25 19:29:38 +0000 |
commit | 0608e04da9d0df5d00cf48a1d9141e2ea1bc9635 (patch) | |
tree | 28fa0ea5f1d70d9bae2eaca42643804235141d12 | |
parent | b79a11cc2bda7a4d5e00444427a0d06b4e86a990 (diff) | |
download | u-boot-imx-0608e04da9d0df5d00cf48a1d9141e2ea1bc9635.zip u-boot-imx-0608e04da9d0df5d00cf48a1d9141e2ea1bc9635.tar.gz u-boot-imx-0608e04da9d0df5d00cf48a1d9141e2ea1bc9635.tar.bz2 |
* Patch by Klaus Heydeck, 13 Mar 2003:
Add support for KUP4X Board
-rw-r--r-- | CHANGELOG | 3 | ||||
-rw-r--r-- | MAINTAINERS | 1 | ||||
-rw-r--r-- | MAKEALL | 18 | ||||
-rw-r--r-- | Makefile | 5 | ||||
-rw-r--r-- | board/kup/Makefile (renamed from board/kup4k/Makefile) | 4 | ||||
-rw-r--r-- | board/kup/common/flash.c (renamed from board/kup4k/flash.c) | 10 | ||||
-rw-r--r-- | board/kup/common/kup.c | 72 | ||||
-rw-r--r-- | board/kup/common/kup.h | 44 | ||||
-rw-r--r-- | board/kup/kup4k/Makefile | 40 | ||||
-rw-r--r-- | board/kup/kup4k/config.mk (renamed from board/kup4k/config.mk) | 2 | ||||
-rw-r--r-- | board/kup/kup4k/kup4k.c (renamed from board/kup4k/kup4k.c) | 260 | ||||
-rw-r--r-- | board/kup/kup4k/s1d13706.h | 174 | ||||
-rw-r--r-- | board/kup/kup4k/u-boot.lds (renamed from board/kup4k/u-boot.lds) | 14 | ||||
-rw-r--r-- | board/kup/kup4k/u-boot.lds.debug (renamed from board/kup4k/u-boot.lds.debug) | 2 | ||||
-rw-r--r-- | board/kup/kup4x/Makefile | 40 | ||||
-rw-r--r-- | board/kup/kup4x/config.mk | 28 | ||||
-rw-r--r-- | board/kup/kup4x/kup4x.c | 311 | ||||
-rw-r--r-- | board/kup/kup4x/u-boot.lds | 141 | ||||
-rw-r--r-- | board/kup/kup4x/u-boot.lds.debug | 135 | ||||
-rw-r--r-- | board/kup/kup4x/usb.c | 81 | ||||
-rw-r--r-- | board/kup4k/s1d13706.h | 113 | ||||
-rw-r--r-- | common/cmd_ide.c | 8 | ||||
-rw-r--r-- | common/cmd_pcmcia.c | 8 | ||||
-rw-r--r-- | include/commproc.h | 6 | ||||
-rw-r--r-- | include/configs/KUP4K.h | 150 | ||||
-rw-r--r-- | include/configs/KUP4X.h | 389 | ||||
-rw-r--r-- | include/status_led.h | 4 | ||||
-rw-r--r-- | lib_ppc/board.c | 1 |
28 files changed, 1727 insertions, 337 deletions
@@ -2,6 +2,9 @@ Changes for U-Boot 1.0.2: ====================================================================== +* Patch by Klaus Heydeck, 13 Mar 2003: + Add support for KUP4X Board + * Patch by Pavel Bartusek, 21 Mar 2004 Add Reiserfs support diff --git a/MAINTAINERS b/MAINTAINERS index 6f8383e..0a1b55a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -146,6 +146,7 @@ Bill Hargen <Bill_Hargen@Jabil.com> Klaus Heydeck <heydeck@kieback-peter.de> KUP4K MPC855 + KUP4X MPC859 Murray Jensen <Murray.Jensen@cmst.csiro.au> @@ -40,15 +40,15 @@ LIST_8xx=" \ GEN860T_SC GENIETV GTH hermes \ IAD210 ICU862_100MHz IP860 IVML24 \ IVML24_128 IVML24_256 IVMS8 IVMS8_128 \ - IVMS8_256 KUP4K LANTEC lwmon \ - MBX MBX860T MHPC MPC86xADS \ - MVS1 NETVIA NETVIA_V2 NX823 \ - pcu_e QS823 QS850 QS860T \ - R360MPI RBC823 rmu RPXClassic \ - RPXlite RRvision SM850 SPD823TS \ - svm_sc8xx SXNI855T TOP860 TQM823L \ - TQM823L_LCD TQM850L TQM855L TQM860L \ - v37 \ + IVMS8_256 KUP4K KUP4X LANTEC \ + lwmon MBX MBX860T MHPC \ + MPC86xADS MVS1 NETVIA NETVIA_V2 \ + NX823 pcu_e QS823 QS850 \ + QS860T R360MPI RBC823 rmu \ + RPXClassic RPXlite RRvision SM850 \ + SPD823TS svm_sc8xx SXNI855T TOP860 \ + TQM823L TQM823L_LCD TQM850L TQM855L \ + TQM860L v37 \ " ######################################################################### @@ -358,7 +358,10 @@ IVMS8_config: unconfig @./mkconfig -a IVMS8 ppc mpc8xx ivm KUP4K_config : unconfig - @./mkconfig $(@:_config=) ppc mpc8xx kup4k + @./mkconfig $(@:_config=) ppc mpc8xx kup4k kup + +KUP4X_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx kup4x kup LANTEC_config : unconfig @./mkconfig $(@:_config=) ppc mpc8xx lantec diff --git a/board/kup4k/Makefile b/board/kup/Makefile index fdc6fd5..071f0d2 100644 --- a/board/kup4k/Makefile +++ b/board/kup/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2002 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o kup.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/kup4k/flash.c b/board/kup/common/flash.c index 619ccb9..903c88f 100644 --- a/board/kup4k/flash.c +++ b/board/kup/common/flash.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -197,13 +197,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) case AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ + info->size = 0x00100000; + break; /* => 1 MB */ case AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ + info->size = 0x00100000; + break; /* => 1 MB */ default: info->flash_id = FLASH_UNKNOWN; return (0); /* => no or unknown flash */ diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c new file mode 100644 index 0000000..69ffa2c --- /dev/null +++ b/board/kup/common/kup.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> +#include "kup.h" + +int misc_init_f (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile sysconf8xx_t *siu = &immap->im_siu_conf; + + while (siu->sc_sipend & 0x20000000) { + /* printf("waiting for 5V VCC\n"); */ + ; + } + + /* RS232 / RS485 default is RS232 */ + immap->im_ioport.iop_padat &= ~(PA_RS485); + immap->im_ioport.iop_papar &= ~(PA_RS485); + immap->im_ioport.iop_paodr &= ~(PA_RS485); + immap->im_ioport.iop_padir |= (PA_RS485); + return (0); +} + + +#ifdef CONFIG_IDE_LED +void ide_led (uchar led, uchar status) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* We have one led for both pcmcia slots */ + if (status) { /* led on */ + immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW); + } else { + immap->im_ioport.iop_padat |= (PA_LED_YELLOW); + } +} +#endif + +void poweron_key (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); + immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); + + if (immap->im_ioport.iop_pcdat & (PC_SWITCH1)) + setenv ("key1", "off"); + else + setenv ("key1", "on"); +} diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h new file mode 100644 index 0000000..70d7f01 --- /dev/null +++ b/board/kup/common/kup.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KUP_H +#define __KUP_H + +#define PA_8 0x0080 +#define PA_11 0x0010 +#define PA_12 0x0008 + +#define PB_14 0x00020000 +#define PB_17 0x00004000 + +#define PC_9 0x0040 + +#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ +#define PA_LED_YELLOW PA_8 +#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ +#define PB_LCD_PWM PB_17 /* PB 17 */ +#define PC_SWITCH1 PC_9 /* Reboot switch */ + +extern void poweron_key (void); + +#endif /* __KUP_H */ diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile new file mode 100644 index 0000000..5732044 --- /dev/null +++ b/board/kup/kup4k/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/kup4k/config.mk b/board/kup/kup4k/config.mk index 10e0fd4..22e30b2 100644 --- a/board/kup4k/config.mk +++ b/board/kup/kup4k/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2002 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this diff --git a/board/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index abf5294..8bed3d5 100644 --- a/board/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000, 2001, 2002 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de * @@ -24,16 +24,23 @@ #include <common.h> #include <mpc8xx.h> +#include "../common/kup.h" #ifdef CONFIG_KUP4K_LOGO #include "s1d13706.h" #endif +#undef DEBUG +#ifdef DEBUG +# define debugk(fmt,args...) printf(fmt ,##args) +#else +# define debugk(fmt,args...) +#endif + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; -typedef struct -{ - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -}FB_INFO_S1D13xxx; /* ------------------------------------------------------------------------- */ @@ -42,15 +49,15 @@ static long int dram_size (long int, long int *, long int); #endif #ifdef CONFIG_KUP4K_LOGO - void lcd_logo(bd_t *bd); +void lcd_logo(bd_t *bd); #endif + /* ------------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF -const uint sdram_table[] = -{ +const uint sdram_table[] = { /* * Single Read. (Offset 0 in UPMA RAM) */ @@ -114,8 +121,19 @@ const uint sdram_table[] = int checkboard (void) { + volatile immap_t *immap = (immap_t *) CFG_IMMR; + uchar *latch,rev,mod; - printf ("### No HW ID - assuming KUP4K-Color\n"); + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + immap->im_memctl.memc_or4 = 0xFFFF8926; + immap->im_memctl.memc_br4 = 0x90000401; + + latch=(uchar *)0x90000200; + rev = (*latch & 0xF8) >> 3; + mod=(*latch & 0x03); + printf ("Board: KUP4K Rev %d.%d SN: %s\n",rev,mod,getenv("ethaddr")); return (0); } @@ -230,10 +248,42 @@ static long int dram_size (long int mamr_value, long int *base, { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; memctl->memc_mamr = mamr_value; - return(get_ram_size(base, maxsize)); + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof (long)); + } + } + return (maxsize); } #endif @@ -247,7 +297,6 @@ int misc_init_r (void) #ifdef CONFIG_KUP4K_LOGO bd_t *bd = gd->bd; - lcd_logo (bd); #endif /* CONFIG_KUP4K_LOGO */ #ifdef CONFIG_IDE_LED @@ -257,14 +306,14 @@ int misc_init_r (void) immap->im_ioport.iop_papar &= ~0x80; immap->im_ioport.iop_padat |= 0x80; /* turn it off */ #endif + setenv("hw","4k"); + poweron_key(); return (0); } #ifdef CONFIG_KUP4K_LOGO -#define PB_LCD_PWM ((uint)0x00004000) /* PB 17 */ - void lcd_logo (bd_t * bd) { FB_INFO_S1D13xxx fb_info; @@ -277,104 +326,117 @@ void lcd_logo (bd_t * bd) int rs, gs, bs; int r = 8, g = 8, b = 4; int r1, g1, b1; + int n; + uchar tmp[64]; /* long enough for environment variables */ + int tft = 0; - immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM; - immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM; - immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM; /* set to 0 = enabled */ - immr->im_cpm.cp_pbdir |= PB_LCD_PWM; - + immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ + immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); /*----------------------------------------------------------------------------- */ - /**/ /* Initialize the chip and the frame buffer driver. */ - /**/ /*----------------------------------------------------------------------------- */ - memctl = &immr->im_memctl; -/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */ -/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */ + memctl = &immr->im_memctl; - memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */ - memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ + /* + * Init ChipSelect #5 (S1D13768) + */ + memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ + memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) - || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { + || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { printf ("Warning:LCD Controller S1D13706 not found\n"); + setenv ("lcd", "none"); return; } - /* init controller */ - for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) { - s1dReg = aS1DRegs[i].Index; - s1dValue = aS1DRegs[i].Value; -/* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */ + + for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { + s1dReg = aS1DRegs_prelimn[i].Index; + s1dValue = aS1DRegs_prelimn[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; + s1dValue; } -#undef MONOCHROME -#ifdef MONOCHROME - switch (bd->bi_busfreq) { -#if 0 - case 24000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28; - break; - case 32000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33; - break; -#endif - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", - bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69; - break; + + n = getenv_r ("lcd", tmp, sizeof (tmp)); + if (n > 0) { + if (!strcmp ("tft", tmp)) + tft = 1; + else + tft = 0; } - ((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00; -#else - switch (bd->bi_busfreq) { #if 0 - case 24000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - case 32000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; -#endif - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", - bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; - break; - } + if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) + tft = 0; + else + tft = 1; #endif + debugk ("Port=0x%02x -> TFT=%d\n", tft, + ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); + + /* init controller */ + if (!tft) { + for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { + s1dReg = aS1DRegs_stn[i].Index; + s1dValue = aS1DRegs_stn[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_stn[i].Index, + aS1DRegs_stn[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = + s1dValue; + } + n = getenv_r ("contrast", tmp, sizeof (tmp)); + ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = + (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; + switch (bd->bi_busfreq) { + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; + break; + case 48000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + default: + printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 64000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; + break; + } + /* setenv("lcd","stn"); */ + } else { + for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { + s1dReg = aS1DRegs_tft[i].Index; + s1dValue = aS1DRegs_tft[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_tft[i].Index, + aS1DRegs_tft[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = + s1dValue; + } + + switch (bd->bi_busfreq) { + default: + printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; + break; + } + /* setenv("lcd","tft"); */ + } /* create and set colormap */ rs = 256 / (r - 1); @@ -384,27 +446,13 @@ void lcd_logo (bd_t * bd) r1 = (rs * ((i / (g * b)) % r)) * 255; g1 = (gs * ((i / b) % g)) * 255; b1 = (bs * ((i) % b)) * 255; -/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */ + debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), - (b1 >> 4)); + (b1 >> 4)); } /* copy bitmap */ fb = (char *) (fb_info.VmemAddr); memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); } -#endif /* CONFIG_KUP4K_LOGO */ - -#ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat &= ~0x80; - } else { - immap->im_ioport.iop_padat |= 0x80; - } -} -#endif +#endif /* CONFIG_KUP4K_LOGO */ diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h new file mode 100644 index 0000000..cd5eccc --- /dev/null +++ b/board/kup/kup4k/s1d13706.h @@ -0,0 +1,174 @@ +/*---------------------------------------------------------------------------- */ +/* */ +/* File generated by S1D13706CFG.EXE */ +/* */ +/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ +/* All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------- */ + +/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ + +#define S1D_DISPLAY_WIDTH 320 +#define S1D_DISPLAY_HEIGHT 240 +#define S1D_DISPLAY_BPP 8 +#define S1D_DISPLAY_SCANLINE_BYTES 320 +#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L +#define S1D_PHYSICAL_VMEM_SIZE 0x14000L +#define S1D_PHYSICAL_REG_ADDR 0x80080000L +#define S1D_PHYSICAL_REG_SIZE 0x100 +#define S1D_DISPLAY_PCLK 6250 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ + ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ + ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ + ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ +} + +#define S1D_READ_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ + g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ + b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ +} + +typedef unsigned short S1D_INDEX; +typedef unsigned char S1D_VALUE; + + +typedef struct +{ + S1D_INDEX Index; + S1D_VALUE Value; +} S1D_REGS; + + +static S1D_REGS aS1DRegs_prelimn[] = +{ + {0x10,0x00}, /* PANEL Type Register */ + {0xA8,0x00}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + +}; + +static S1D_REGS aS1DRegs_stn[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x10,0xD0}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xF0}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x80}, /* Vertical Sync Pulse Width Register */ + {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x83}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xA8,0x01}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + {0xAC,0x01}, /* GPIO Status Control Register 0 */ + {0xAD,0x00}, /* GPIO Status Control Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + +static S1D_REGS aS1DRegs_tft[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x05,0x42}, /* PCLK Config Register */ + {0x10,0x61}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x12,0x30}, /* Horizontal Total Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xFA}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x00}, /* Vertical Sync Pulse Width Register */ + {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x03}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xA8,0x01}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + {0xAC,0x01}, /* GPIO Status Control Register 0 */ + {0xAD,0x00}, /* GPIO Status Control Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; diff --git a/board/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index f81a10e..2339136 100644 --- a/board/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -57,17 +57,17 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) lib_generic/vsprintf.o (.text) lib_generic/crc32.o (.text) lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) . = env_offset; - common/environment.o (.ppcenv) + common/environment.o(.text) +*/ *(.text) *(.fixup) diff --git a/board/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 87f704a..4e369d5 100644 --- a/board/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile new file mode 100644 index 0000000..3fed0f0 --- /dev/null +++ b/board/kup/kup4x/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o usb.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/kup/kup4x/config.mk b/board/kup/kup4x/config.mk new file mode 100644 index 0000000..61d4e09 --- /dev/null +++ b/board/kup/kup4x/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# KUP4X board +# + +TEXT_BASE = 0x40000000 diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c new file mode 100644 index 0000000..86b749d --- /dev/null +++ b/board/kup/kup4x/kup4x.c @@ -0,0 +1,311 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> +#include "../common/kup.h" +#ifdef CONFIG_KUP4K_LOGO +/* #include "s1d13706.h" */ +#endif + +#define KUP4X_USB + + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; + +/* ------------------------------------------------------------------------- */ + +int usb_init_kup4x (void); + + +#ifdef CONFIG_KUP4K_LOGO +void lcd_logo (bd_t * bd); +#endif + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + uchar *latch, rev, mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + memctl->memc_or4 = 0xFFFF8926; + memctl->memc_br4 = 0x90000401; + + latch = (uchar *) 0x90000200; + rev = (*latch & 0xF8) >> 3; + mod = (*latch & 0x03); + printf ("Board: KUP4X Rev %d.%d SN: %s\n", rev, mod, + getenv ("ethaddr")); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0 = 0; + long int size_b1 = 0; + long int size_b2 = 0; + long int size_b3 = 0; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ +/* memctl->memc_or1 = CFG_OR1_PRELIM; */ +/* memctl->memc_br1 = CFG_BR1_PRELIM; */ + +/* memctl->memc_or2 = CFG_OR2_PRELIM; */ +/* memctl->memc_br2 = CFG_BR2_PRELIM; */ + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ + udelay (1); + memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */ + udelay (1); + memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + udelay (1000); +#if 0 /* 4 x 8MB */ + size_b0 = 0x00800000; + size_b1 = 0x00800000; + size_b2 = 0x00800000; + size_b3 = 0x00800000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF800A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFF000A00; + memctl->memc_br2 = 0x00800081; + memctl->memc_or3 = 0xFE000A00; + memctl->memc_br3 = 0x01000081; + memctl->memc_or6 = 0xFE000A00; + memctl->memc_br6 = 0x01800081; +#else /* 4 x 16 MB */ + size_b0 = 0x01000000; + size_b1 = 0x01000000; + size_b2 = 0x01000000; + size_b3 = 0x01000000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF000A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFE000A00; + memctl->memc_br2 = 0x01000081; + memctl->memc_or3 = 0xFD000A00; + memctl->memc_br3 = 0x02000081; + memctl->memc_or6 = 0xFC000A00; + memctl->memc_br6 = 0x03000081; +#endif + udelay (10000); + + return (size_b0 + size_b1 + size_b2 + size_b3); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +#if 0 +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof (long)); + } + } + return (maxsize); +} +#endif + +int misc_init_r (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#ifdef CONFIG_IDE_LED + /* Configure PA8 as output port */ + immap->im_ioport.iop_padir |= 0x80; + immap->im_ioport.iop_paodr |= 0x80; + immap->im_ioport.iop_papar &= ~0x80; + immap->im_ioport.iop_padat |= 0x80; /* turn it off */ +#endif +#ifdef KUP4X_USB + usb_init_kup4x (); +#endif + setenv ("hw", "4x"); + poweron_key (); + return (0); +} diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds new file mode 100644 index 0000000..2339136 --- /dev/null +++ b/board/kup/kup4x/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) +*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug new file mode 100644 index 0000000..4e369d5 --- /dev/null +++ b/board/kup/kup4x/u-boot.lds.debug @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kup/kup4x/usb.c b/board/kup/kup4x/usb.c new file mode 100644 index 0000000..5444008 --- /dev/null +++ b/board/kup/kup4x/usb.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> +#include "../common/kup.h" + + +#define SL811_ADR (0x50000000) +#define SL811_DAT (0x50000001) + + +static void sl811_write_index_data (__u8 index, __u8 data) +{ + *(volatile unsigned char *) (SL811_ADR) = index; + __asm__ ("eieio"); + *(volatile unsigned char *) (SL811_DAT) = data; + __asm__ ("eieio"); +} + +static __u8 sl811_read_index_data (__u8 index) +{ + __u8 data; + + *(volatile unsigned char *) (SL811_ADR) = index; + __asm__ ("eieio"); + data = *(volatile unsigned char *) (SL811_DAT); + __asm__ ("eieio"); + return (data); +} + +int usb_init_kup4x (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + int i; + unsigned char tmp; + + memctl = &immap->im_memctl; + memctl->memc_or7 = 0xFFFF8726; + memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ + /* BP 14 low = USB ON */ + immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); + /* PB 14 nomal port */ + immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); + /* output */ + immap->im_cpm.cp_pbdir |= (BP_USB_VCC); + + puts ("USB: "); + + for (i = 0x10; i < 0xff; i++) { + sl811_write_index_data (i, i); + tmp = (sl811_read_index_data (i)); + if (tmp != i) { + printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); + return (-1); + } + } + printf ("SL811 ready\n"); + return (0); +} diff --git a/board/kup4k/s1d13706.h b/board/kup4k/s1d13706.h deleted file mode 100644 index 90027bf..0000000 --- a/board/kup4k/s1d13706.h +++ /dev/null @@ -1,113 +0,0 @@ -/*---------------------------------------------------------------------------- */ -/* */ -/* File generated by S1D13706CFG.EXE */ -/* */ -/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ -/* All rights reserved. */ -/* */ -/*---------------------------------------------------------------------------- */ - -/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ - -#define S1D_DISPLAY_WIDTH 320 -#define S1D_DISPLAY_HEIGHT 240 -#define S1D_DISPLAY_BPP 8 -#define S1D_DISPLAY_SCANLINE_BYTES 320 -#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L -#define S1D_PHYSICAL_VMEM_SIZE 0x14000L -#define S1D_PHYSICAL_REG_ADDR 0x80080000L -#define S1D_PHYSICAL_REG_SIZE 0x100 -#define S1D_DISPLAY_PCLK 6250 -#define S1D_PALETTE_SIZE 256 -#define S1D_REGDELAYOFF 0xFFFE -#define S1D_REGDELAYON 0xFFFF - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ - ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ - ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ - ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ -} - -#define S1D_READ_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ - r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ - g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ - b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ -} - -typedef unsigned short S1D_INDEX; -typedef unsigned char S1D_VALUE; - - -typedef struct -{ - S1D_INDEX Index; - S1D_VALUE Value; -} S1D_REGS; - -static S1D_REGS aS1DRegs[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ -#if 0 - {0x05,0x32}, /* PCLK Config Register */ -#endif - {0x10,0xD0}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ -#if 0 - {0x12,0x34}, /* Horizontal Total Register */ -#endif - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xF0}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x80}, /* Vertical Sync Pulse Width Register */ - {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x83}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xB3,0xA0}, /* PWM Clock Duty Cycle Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, /* */ -}; diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 842a2fd..aad6127 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -139,7 +139,7 @@ static block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; /* ------------------------------------------------------------------------- */ #ifdef CONFIG_IDE_LED -#if !defined(CONFIG_KUP4K) && !defined(CONFIG_HMI10) +#if !defined(CONFIG_KUP4K) && !defined(CONFIG_KUP4X) &&!defined(CONFIG_BMS2003) static void ide_led (uchar led, uchar status); #else extern void ide_led (uchar led, uchar status); @@ -1537,7 +1537,11 @@ static void ide_reset (void) /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_IDE_LED) && !defined(CONFIG_AMIGAONEG3SE) && !defined(CONFIG_KUP4K) && !defined(CONFIG_HMI10) +#if defined(CONFIG_IDE_LED) && \ + !defined(CONFIG_AMIGAONEG3SE) && \ + !defined(CONFIG_KUP4K) && \ + !defined(CONFIG_KUP4X) && \ + !defined(CONFIG_HMI10) static uchar led_buffer = 0; /* Buffer for current LED status */ diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index cb4e4c6..963f98f 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -2125,11 +2125,11 @@ done: #endif /* R360MPI */ /* -------------------------------------------------------------------- */ -/* KUP4K Board */ +/* KUP4K and KUP4X Boards */ /* -------------------------------------------------------------------- */ -#if defined(CONFIG_KUP4K) +#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) -#define PCMCIA_BOARD_MSG "KUP4K" +#define PCMCIA_BOARD_MSG "KUP" #define KUP4K_PCMCIA_B_3V3 (0x00020000) @@ -2337,7 +2337,7 @@ static int voltage_set(int slot, int vcc, int vpp) return (0); } -#endif /* KUP4K */ +#endif /* KUP4K || KUP4X */ /* -------------------------------------------------------------------- */ diff --git a/include/commproc.h b/include/commproc.h index 11f31e9..9facd77 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -980,10 +980,10 @@ typedef struct scc_enet { #endif /* CONFIG_IVMS8, CONFIG_IVML24 */ -/*** KUP4K *********************************************************/ -/* The KUP4K uses the FEC on a MPC855T for Ethernet */ +/*** KUP4K, KUP4X ****************************************************/ +/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ -#if defined(CONFIG_KUP4K) +#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) #define FEC_ENET /* use FEC for EThernet */ #undef SCC_ENET diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index 962a468..d6aa8e1 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000, 2001, 2002 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de * @@ -13,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -38,7 +38,7 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_KUP4K 1 /* ...on a KUP4K module */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 /* console baudrate */ @@ -48,7 +48,7 @@ #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ #endif -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_BOARD_TYPES 1 /* support board types */ @@ -56,35 +56,38 @@ #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\ - diskboot 200000 0:1; bootm 200000\0" \ -"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\ - diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip; bootm 200000\0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath)\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsip):$(gatewayip)\ -:$(netmask):$(hostname):$(netdev):off panic=1\0" \ -"netdev=eth0\0" \ -"load=tftp 200000 bootloader.bitmap;tftp 100000 u-boot.bin\0" \ -"update=protect off 1:0-8;era 1:0-8;cp.b 100000 40000000 $(filesize);\ -cp.b 200000 40040000 14000\0" \ -"nfsip=192.168.2.19\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ +"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw; diskboot 200000 0:1; bootm 200000\0" \ +"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw; diskboot 200000 2:1; bootm 200000\0" \ +"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ +"panic_boot=echo No Bootdevice !!! reset\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ +"ramargs=setenv bootargs root=/dev/ram rw\0" \ +"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \ + ":$(netmask):$(hostname):$(netdev):off\0" \ +"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \ +"netdev=eth0\0" \ +"contrast=55\0" \ +"silent=1\0" \ +"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ +"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \ + "cp.b 200000 40040000 14000\0" #define CONFIG_BOOTCOMMAND \ "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" -#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_F 1 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ @@ -93,10 +96,14 @@ cp.b 200000 40040000 14000\0" #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ -#define CONFIG_KUP4K_LOGO 0x40040000 /* Address of logo bitmap */ +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 40000 +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ +#define CONFIG_KUP4K_LOGO 0x40040000 /* Address of logo bitmap */ /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -104,6 +111,7 @@ cp.b 200000 40040000 14000\0" #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ CFG_CMD_IDE | \ + CFG_CMD_I2C | \ CFG_CMD_DATE ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -112,25 +120,25 @@ cp.b 200000 40040000 14000\0" /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ -#define CFG_LOAD_ADDR 0x200000 /* default load address */ +#define CFG_LOAD_ADDR 0x200000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } #define CFG_CONSOLE_INFO_QUIET 1 @@ -148,42 +156,42 @@ cp.b 200000 40040000 14000\0" * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x8000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Address and size of Redundant Environment Sector */ #if 0 @@ -195,7 +203,7 @@ cp.b 200000 40040000 14000\0" */ #if 0 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ #endif /*----------------------------------------------------------------------- @@ -275,7 +283,7 @@ cp.b 200000 40040000 14000\0" */ /* KUP4K use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 +#define CONFIG_PCMCIA_SLOT_A 1 #define CFG_PCMCIA_MEM_ADDR (0xE0000000) #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) @@ -293,10 +301,10 @@ cp.b 200000 40040000 14000\0" *----------------------------------------------------------------------- */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#define CONFIG_IDE_LED 1 /* LED for ide supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_IDE_MAXBUS 2 @@ -323,7 +331,7 @@ cp.b 200000 40040000 14000\0" *----------------------------------------------------------------------- * */ -#define CFG_DER 0 +#define CFG_DER 0 /* * Init Memory Controller: @@ -350,29 +358,9 @@ cp.b 200000 40040000 14000\0" #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_BASE3_PRELIM 0x30000000 /* SDRAM bank #2 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 648 MB per bank */ - /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SDRAM 0x00000A00 -#if 0 -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#endif - /* * Memory Periodic Timer Prescaler @@ -388,11 +376,11 @@ cp.b 200000 40040000 14000\0" * gclk CPU clock (not bus clock!) * Trefresh Refresh cycle * 4 (four word bursts used) * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows * -------------------------------------------- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 * @@ -428,7 +416,7 @@ cp.b 200000 40040000 14000\0" * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ @@ -437,6 +425,6 @@ cp.b 200000 40040000 14000\0" #define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" #endif #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ - +#define CONFIG_SILENT_CONSOLE 1 #endif /* __CONFIG_H */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h new file mode 100644 index 0000000..4451f2a --- /dev/null +++ b/include/configs/KUP4X.h @@ -0,0 +1,389 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + * Derived from ../tqm8xx/tqm8xx.c + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ +#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CFG_8XX_FACT 8 /* Multiply by 8 */ +#define CFG_8XX_XIN 16000000 /* 16 MHz in */ + + +#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) + +/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ +/* in general, we always know this for FADS+new ADS anyway */ +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + + +#undef CONFIG_BOOTARGS + + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw;diskboot 200000 0:1;bootm 200000\0" \ +"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw;diskboot 200000 2:1;bootm 200000\0" \ +"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ +"panic_boot=echo No Bootdevice !!! reset\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ +"ramargs=setenv bootargs root=/dev/ram rw\0" \ +"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \ + ":$(netmask):$(hostname):$(netdev):off\0" \ +"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \ +"netdev=eth0\0" \ +"silent=1\0" \ +"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \ +"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \ + "cp.b 200000 40040000 14000\0" + +#define CONFIG_BOOTCOMMAND \ + "run slot_a_boot;run nfs_boot;run panic_boot" + + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_F 1 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 40000 +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ +#undef CONFIG_KUP4K_LOGO + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } + +#define CFG_CONSOLE_INFO_QUIET 1 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 + +/* Address and size of Redundant Environment Sector */ +#if 0 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#if 0 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS) + + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ + +/* KUP4K use both slots, SLOT_A as "primary". */ +#define CONFIG_PCMCIA_SLOT_A 1 + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +#define PCMCIA_SOCKETS_NO 1 +#define PCMCIA_MEM_WIN_NO 8 +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#define CONFIG_IDE_LED 1 /* LED for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + + +#define CFG_MPTPR 0x400 + +/* + * MAMR settings for SDRAM + */ +#define CFG_MAMR 0x80802114 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#if 0 +#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" +#endif +#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ +#define CONFIG_SILENT_CONSOLE 1 + +#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index 4840c49..441b0c2 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -269,8 +269,8 @@ void status_led_set (int led, int state); # define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */ # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** KUP4K ********************************************************/ -#elif defined(CONFIG_KUP4K) +/***** KUP4K, KUP4X ****************************************************/ +#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM) # define STATUS_LED_PAR im_ioport.iop_papar # define STATUS_LED_DIR im_ioport.iop_padir diff --git a/lib_ppc/board.c b/lib_ppc/board.c index cae7775..15cf67a 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -839,6 +839,7 @@ void board_init_r (gd_t *id, ulong dest_addr) defined(CONFIG_CPCI405) || \ defined(CONFIG_EVB64260) || \ defined(CONFIG_KUP4K) || \ + defined(CONFIG_KUP4X) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_PCU_E) || \ defined(CONFIG_W7O) || \ |