Merge git://www.denx.de/git/u-boot

168 files changed, 7639 insertions, 1221 deletions

diff --git a/CHANGELOG b/CHANGELOG
index b77eec7..e3c21f9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,201 @@
+commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9
+Author: Igor Lisitsin <igor@emcraft.com>
+Date:	Wed Apr 18 14:55:19 2007 +0400
+
+    Adapt log buffer code to support Linux 2.6
+
+    A new environment variable, "logversion", selects the log buffer
+    behaviour. If it is not set or set to a value other than 2, then the
+    old, Linux 2.4.4, behaviour is selected.
+
+    Signed-off-by: Igor Lisitsin <igor@emcraft.com>
+    --
+
+commit a11e06965ec91270c51853407ff1261d3c740386
+Author: Igor Lisitsin <igor@emcraft.com>
+Date:	Wed Mar 28 19:06:19 2007 +0400
+
+    Extend POST support for PPC440
+
+    Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
+
+    Signed-off-by: Igor Lisitsin <igor@emcraft.com>
+    --
+
+commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Fri Jun 22 14:58:04 2007 +0200
+
+    [ppc] Fix build breakage for all non-4xx PowerPC variants.
+
+    - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
+    - minor 4xx cleanup
+
+commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jun 20 18:14:24 2007 +0200
+
+    Coding style cleanup. Refresh CHANGELOG.
+
+commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jun 19 17:22:44 2007 +0200
+
+    ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board
+
+    This patch adds a board command to configure the I2C bootstrap EEPROM
+    values. Right now 533 and 667MHz are supported for booting either via NOR
+    or NAND FLASH. Here the usage:
+
+    => bootstrap 533 nor	;to configure the board for 533MHz NOR booting
+    => bootstrap 667 nand	;to configure the board for 667MHz NNAND booting
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit df8a24cdd30151505cf57bbee5289e91bf53bd1b
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jun 19 16:42:31 2007 +0200
+
+    [ppc4xx] Fix problem with NAND booting on AMCC Acadia
+
+    The latest changes showed a problem with the location of the NAND-SPL
+    image in the OCM and the init-data area (incl. cache). This patch
+    fixes this problem.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 86ba99e34194394052d24c04dc40d1263d29a26f
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jun 19 16:40:58 2007 +0200
+
+    [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 15 11:33:41 2007 +0200
+
+    [ppc4xx] Change lwmon5 port to work with recent 440 exception rework
+
+    Now CONFIG_440 has to be defined in all PPC440 board config files.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit efa35cf12d914d4caba942acd5a6c45f217de302
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Fri Jun 15 11:19:28 2007 +0200
+
+    ppc4xx: Clean up 440 exceptions handling
+
+    - Introduced dedicated switches for building 440 and 405 images required
+      for 440-specific machine instructions like 'rfmci' etc.
+
+    - Exception vectors moved to the proper location (_start moved away from
+      the critical exception handler space, which it occupied)
+
+    - CriticalInput now serviced (with default handler)
+
+    - MachineCheck properly serviced (added a dedicated handler and return
+      subroutine)
+
+    - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
+      unhandled and those not relevant for 4xx were eliminated)
+
+    - Eliminated Linux leftovers, removed dead code
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 15 08:18:01 2007 +0200
+
+    [ppc4xx] Add initial lwmon5 board support
+
+    This patch adds initial support for the Liebherr lwmon5 board euqipped
+    with an AMCC 440EPx PowerPC.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 85f737376d5ff3d5f0d45a8b657686326d175307
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 15 07:39:43 2007 +0200
+
+    [ppc4xx] Extend 44x GPIO setup with default output state
+
+    The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
+    is extended with the default GPIO output state (level).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit dbca208518e5e7f01a6420588d1cd6e60db74c2b
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jun 14 11:14:32 2007 +0200
+
+    [ppc4xx] Extend program_tlb() with virtual & physical addresses
+
+    Now program_tlb() allows to program a TLB (or multiple) with
+    different virtual and physical addresses. With this change, now one
+    physical region (e.g. SDRAM) can be mapped 2 times, once with caches
+    diabled and once with caches enabled.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9912121f7ed804ea58fd62f3f230b5dcfc357d88
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Wed May 23 19:02:41 2007 +0200
+
+    Change 'repeatable' attribute of some commands to sensible values.
+
+    Most prominently this changes 'erase' to be non-repeatable.
+
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 5afb202093f6a001797db92cf695b93a70ea9ab4
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Wed May 23 18:47:48 2007 +0200
+
+    Fix 'run' not to continue after interrupted command
+
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 8f8416fada9faf94b9a92f21fe6000643cb521d5
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Fri Jun 8 14:52:22 2007 +0200
+
+    TQM5200: Add Flat Device Tree support, update default env. accordingly.
+
+    Signed-off-by: Jan Wrobel <wrr@semihalf.com>
+    Acked-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 9045f33c023f698660a2e45d1b2194c0711abebc
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Jun 8 10:24:58 2007 +0200
+
+    Fix config problems on SC3 board; make ide_reset_timeout work.
+
+commit fba3fb0449b8a54542aed1e729de76e7f5a2ff1b
+Author: Benoît Monin <bmonin@adeneo.eu>
+Date:	Fri Jun 8 09:55:24 2007 +0200
+
+    [PATCH] fix gpio setting when using CFG_440_GPIO_TABLE
+
+    Set the correct value in GPIOx_TCR when configuring the gpio
+    with CFG_440_GPIO_TABLE.
+
+    Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jun 6 16:26:56 2007 +0200
+
+    Coding Style cleanup; generate new CHANGELOG file.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit c440bfe6d6d92d66478a7e84402b31f48413617b
 Author: Stefan Roese <sr@denx.de>
 Date:	Wed Jun 6 11:42:13 2007 +0200
diff --git a/MAINTAINERS b/MAINTAINERS
index 2eaef17..693b115 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -282,6 +282,7 @@ Stefan Roese <sr@denx.de>
 	bunbinga		PPC405EP
 	ebony			PPC440GP
 	katmai			PPC440SPe
+	lwmon5			PPC440EPx
 	ocotea			PPC440GX
 	p3p440			PPC440GP
 	pcs440ep		PPC440EP
diff --git a/MAKEALL b/MAKEALL
index 0e4e744..f931e1d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -83,15 +83,15 @@ LIST_4xx="	\
 	csb272		csb472		DASA_SIM	DP405		\
 	DU405		ebony		ERIC		EXBITGEN	\
 	G2000		HH405		HUB405		JSE		\
-	KAREF		katmai		luan		METROBOX	\
-	MIP405		MIP405T		ML2		ml300		\
-	ocotea		OCRTC		ORSG		p3p440		\
-	PCI405		pcs440ep	PIP405		PLU405		\
-	PMC405		PPChameleonEVB	sbc405		sc3		\
-	sequoia		sequoia_nand	taishan		VOH405		\
-	VOM405		W7OLMC		W7OLMG		walnut		\
-	WUH405		XPEDITE1K	yellowstone	yosemite	\
-	yucca								\
+	KAREF		katmai		luan		lwmon5		\
+	METROBOX	MIP405		MIP405T		ML2		\
+	ml300		ocotea		OCRTC		ORSG		\
+	p3p440		PCI405		pcs440ep	PIP405		\
+	PLU405		PMC405		PPChameleonEVB	sbc405		\
+	sc3		sequoia		sequoia_nand	taishan		\
+	VOH405		VOM405		W7OLMC		W7OLMG		\
+	walnut		WUH405		XPEDITE1K	yellowstone	\
+	yosemite	yucca						\
 "
 
 #########################################################################
@@ -151,6 +151,14 @@ LIST_85xx="	\
 "
 
 #########################################################################
+## MPC86xx Systems
+#########################################################################
+
+LIST_86xx="	\
+    MPC8641HPCN	\
+"
+
+#########################################################################
 ## 74xx/7xx Systems
 #########################################################################
 
@@ -170,6 +178,7 @@ LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
 	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
 	  ${LIST_83xx}				\
 	  ${LIST_85xx}				\
+	  ${LIST_86xx}				\
 	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"
 
@@ -356,7 +365,7 @@ do
 	microblaze| \
 	mips|mips_el| \
 	nios|nios2| \
-	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
+	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
 	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
diff --git a/Makefile b/Makefile
index d5e220a..626283f 100644
--- a/Makefile
+++ b/Makefile
@@ -214,6 +214,8 @@ LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/drivers/libpostdrivers.a
 LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
 	"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
+LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
+	"post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
 LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
 	"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
 LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
@@ -1139,6 +1141,9 @@ katmai_config:	unconfig
 luan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
 
+lwmon5_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
+
 METROBOX_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
 
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
index ddbcb80..c56b273 100644
--- a/board/amcc/acadia/Makefile
+++ b/board/amcc/acadia/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_acadia.o cpr.o memory.o
+COBJS	= $(BOARD).o cmd_acadia.o memory.o pll.o
 SOBJS	=
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 46d63e6..8b82ea4 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-       	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-       	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
-       	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-       	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
-       	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-       	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
-       	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
+	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
+	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
+	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
+	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
 
 	/*
 	 * Ultra (405EZ) was nice enough to add another GPIO controller
@@ -55,10 +55,12 @@ int board_early_init_f(void)
 {
 	unsigned int reg;
 
+#if !defined(CONFIG_NAND_U_BOOT)
 	/* don't reinit PLL when booting via I2C bootstrap option */
 	mfsdr(SDR_PINSTP, reg);
 	if (reg != 0xf0000000)
 		board_pll_init_f();
+#endif
 
 	acadia_gpio_init();
 
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 25904d3..9346d2c 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -31,6 +31,8 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
+extern void board_pll_init_f(void);
+
 /*
  * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
  */
@@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val)
 
 long int initdram(int board_type)
 {
+#if defined(CONFIG_NAND_SPL)
+	u32 reg;
+
+	/* don't reinit PLL when booting via I2C bootstrap option */
+	mfsdr(SDR_PINSTP, reg);
+	if (reg != 0xf0000000)
+		board_pll_init_f();
+#endif
+
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	int i;
 	u32 val;
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/pll.c
index 9dcce35..9dcce35 100644
--- a/board/amcc/acadia/cpr.c
+++ b/board/amcc/acadia/pll.c
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2e651df..caf6690 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -416,7 +416,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
@@ -457,7 +457,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index dcafac9..ededb3e 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -207,14 +207,14 @@ long int fixed_sdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long strap;
 
 	/*--------------------------------------------------------------------------+
-     *	The ebony board is always configured as the host & requires the
-     *	PCI arbiter to be enabled.
+	 * The ebony board is always configured as the host & requires the
+	 * PCI arbiter to be enabled.
 	 *--------------------------------------------------------------------------*/
 	strap = mfdcr(cpc0_strp1);
 	if ((strap & 0x00100000) == 0) {
@@ -224,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 286bdc1..b804d55 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -292,7 +292,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -309,7 +309,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 778aafc..2eff3b3 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -161,7 +161,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init( struct pci_controller *hose )
 {
 	unsigned long strap;
@@ -179,7 +179,7 @@ int pci_pre_init( struct pci_controller *hose )
 
 	return  1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 
 /*************************************************************************
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 3f6d204..3bd1b81 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -306,7 +306,7 @@ long int fixed_sdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -323,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
index 06ef7f9..e1c9ad4 100644
--- a/board/amcc/sequoia/Makefile
+++ b/board/amcc/sequoia/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o sdram.o
+COBJS	= $(BOARD).o cmd_sequoia.o sdram.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
new file mode 100644
index 0000000..6fc60ea
--- /dev/null
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+static u8 boot_533_nor[] = {
+	0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
+	0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+};
+
+static u8 boot_533_nand[] = {
+	0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
+	0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+};
+
+static u8 boot_667_nor[] = {
+	0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
+	0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+};
+
+static u8 boot_667_nand[] = {
+	0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
+	0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+};
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u8 chip;
+	u8 *buf;
+	int cpu_freq;
+
+	if (argc < 3) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	cpu_freq = simple_strtol(argv[1], NULL, 10);
+	if (!((cpu_freq == 533) || (cpu_freq == 667))) {
+		printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
+		return 1;
+	}
+
+	/* use 0x52 as I2C EEPROM address for now */
+	chip = 0x52;
+
+	if ((strcmp(argv[2], "nor") != 0) &&
+	    (strcmp(argv[2], "nand") != 0)) {
+		printf("Unsupported boot-device - only nor|nand support\n");
+		return 1;
+	}
+
+	if (strcmp(argv[2], "nand") == 0) {
+		switch (cpu_freq) {
+		default:
+		case 533:
+			buf = boot_533_nand;
+			break;
+		case 667:
+			buf = boot_667_nand;
+			break;
+		}
+	} else {
+		switch (cpu_freq) {
+		default:
+		case 533:
+			buf = boot_533_nor;
+			break;
+		case 667:
+			buf = boot_667_nor;
+			break;
+		}
+	}
+
+	if (i2c_write(chip, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", chip);
+	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+
+	printf("Done\n");
+	printf("Please power-cycle the board for the changes to take effect\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootstrap,	3,	0,	do_bootstrap,
+	"bootstrap - program the I2C bootstrap EEPROM\n",
+	"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
+	);
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index ba365ae..f823117 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -25,7 +25,6 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <ppc440.h>
-#include "sequoia.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -226,7 +225,7 @@ int misc_init_r(void)
 	if (act == NULL || strcmp(act, "hostdev") == 0)	{
 		/* SDR Setting */
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
-		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
@@ -254,7 +253,7 @@ int misc_init_r(void)
 		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
 
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
-		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
@@ -298,7 +297,7 @@ int misc_init_r(void)
 		/* SDR Setting */
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
-		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@@ -323,7 +322,7 @@ int misc_init_r(void)
 
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
 
 		/*clear resets*/
@@ -426,23 +425,10 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
-#if 0
-	/*--------------------------------------------------------------------------+
-	 *	Cactus is always configured as the host & requires the
-	 *	PCI arbiter to be enabled ???
-	 *--------------------------------------------------------------------------*/
-	unsigned long strap;
-	mfsdr(sdr_sdstp1, strap);
-	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
-		printf("PCI: SDR0_STRP1[PAE] not set.\n");
-		printf("PCI: Configuration aborted.\n");
-		return 0;
-	}
-#endif
 
 	/*-------------------------------------------------------------------------+
 	  | Set priority for all PLB3 devices to 0.
@@ -480,7 +466,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -586,3 +572,13 @@ int is_pci_host(struct pci_controller *hose)
 	return (1);
 }
 #endif				/* defined(CONFIG_PCI) */
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h
deleted file mode 100644
index 1d44b16..0000000
--- a/board/amcc/sequoia/sequoia.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-/*----------------------------------------------------------------------------+
-  | EBC Configuration Register - EBC0_CFG
-  +----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED	    0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK	    0x38000000
-#define EBC0_CFG_RTC_16PERCLK	    0x00000000
-#define EBC0_CFG_RTC_32PERCLK	    0x08000000
-#define EBC0_CFG_RTC_64PERCLK	    0x10000000
-#define EBC0_CFG_RTC_128PERCLK	    0x18000000
-#define EBC0_CFG_RTC_256PERCLK	    0x20000000
-#define EBC0_CFG_RTC_512PERCLK	    0x28000000
-#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
-#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW	    0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
-#define EBC0_CFG_EMPL_HIGH	    0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW	    0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
-#define EBC0_CFG_EMPH_HIGH	    0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW	    0x00000000
-#define EBC0_CFG_BPF_TWODW	    0x00100000
-#define EBC0_CFG_BPF_FOURDW	    0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT	    0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED	    0x00000000
-#define EBC0_CFG_PME_ENABLED	    0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
-
-#define SDR0_USB0                    0x0320     /* USB Control Register */
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 1a2e53b..bc976c7 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -236,7 +236,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -253,7 +253,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index c2e12ba..912f09e 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -385,7 +385,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
@@ -426,7 +426,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 90eaab1..7316c34 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -604,7 +604,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -621,7 +621,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c
index f00837a..807b9e8 100644
--- a/board/bf537-stamp/ether_bf537.c
+++ b/board/bf537-stamp/ether_bf537.c
@@ -48,7 +48,7 @@
 #define TXBUF_BASE_ADDR		0xFF800000
 #define TX_BUF_CNT		1
 
-#define TOUT_LOOP 		1000000
+#define TOUT_LOOP		1000000
 
 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
 ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h
index acc1e86..1fa7a10 100644
--- a/board/bf537-stamp/flash-defines.h
+++ b/board/bf537-stamp/flash-defines.h
@@ -44,9 +44,9 @@
 #define ERASE_SECT		6
 #define READ			7
 #define GET_SECTNUM		8
-#define FLASH_START_L 		0x0000
-#define FLASH_START_H 		0x2000
-#define FLASH_MAN_ST 		2
+#define FLASH_START_L		0x0000
+#define FLASH_START_H		0x2000
+#define FLASH_MAN_ST		2
 #define RESET_VAL		0xF0
 
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c
index 7077e85..d9c08ee 100644
--- a/board/bf537-stamp/stm_m25p64.c
+++ b/board/bf537-stamp/stm_m25p64.c
@@ -9,7 +9,7 @@
 
 /* Application definitions */
 
-#define	NUM_SECTORS 	128	/* number of sectors */
+#define	NUM_SECTORS	128	/* number of sectors */
 #define SECTOR_SIZE	0x10000
 #define NOP_NUM		1000
 
diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S
index 3fb2d0c..8632097 100644
--- a/board/bf537-stamp/u-boot.lds.S
+++ b/board/bf537-stamp/u-boot.lds.S
@@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
    __DYNAMIC = 0;    */
 MEMORY
  {
- ram : 	   ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
+ ram :	   ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
  l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
  l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
  }
@@ -47,11 +47,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
@@ -68,7 +68,7 @@ SECTIONS
   .text      :
   {
     /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector before the environment sector. If it throws 	*/
+    /* the sector before the environment sector. If it throws	*/
     /* an error during compilation remove an object here to get	*/
     /* it linked after the configuration sector.		*/
 
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index 929ff2e..b723641 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -345,23 +345,23 @@ int last_stage_init(void)
 	/* This is needed to get the RGMII working for the 1.3+
 	 * CDS cards */
 	if (get_board_version() ==  0x13) {
-		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+		miiphy_write(CONFIG_TSEC1_NAME,
 				TSEC1_PHY_ADDR, 29, 18);
 
-		miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
+		miiphy_read(CONFIG_TSEC1_NAME,
 				TSEC1_PHY_ADDR, 30, &temp);
 
 		temp = (temp & 0xf03f);
 		temp |= 2 << 9;		/* 36 ohm */
 		temp |= 2 << 6;		/* 39 ohm */
 
-		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+		miiphy_write(CONFIG_TSEC1_NAME,
 				TSEC1_PHY_ADDR, 30, temp);
 
-		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+		miiphy_write(CONFIG_TSEC1_NAME,
 				TSEC1_PHY_ADDR, 29, 3);
 
-		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+		miiphy_write(CONFIG_TSEC1_NAME,
 				TSEC1_PHY_ADDR, 30, 0x8000);
 	}
 
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index f803610..2ed0fc2 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -23,9 +23,11 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 #include <net.h>
+#include <pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -179,11 +181,15 @@ int board_early_init_f (void)
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
 	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+#ifdef CONFIG_CPCI405_6U
 	if (cpci405_version() == 3) {
 		mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
 	} else {
 		mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
 	}
+#else
+	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+#endif
 	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
@@ -227,10 +233,10 @@ int cpci405_version(void)
 	 */
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
-	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
 	udelay(1000);                   /* wait some time before reading input */
-	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+	value = in_be32((void*)GPIO0_IR) & 0x00180000;       /* get config bits */
 
 	/*
 	 * Restore GPIO settings
@@ -245,7 +251,7 @@ int cpci405_version(void)
 		/* CS2==0 && CS3==1 -> version 2 */
 		return 2;
 	case 0x00100000:
-		/* CS2==1 && CS3==0 -> version 3 */
+		/* CS2==1 && CS3==0 -> version 3 or 6U board */
 		return 3;
 	case 0x00000000:
 		/* CS2==0 && CS3==0 -> version 4 */
@@ -283,7 +289,6 @@ int misc_init_r (void)
 	 * On CPCI-405 version 2 the environment is saved in eeprom!
 	 * FPGA can be gzip compressed (malloc) and booted this late.
 	 */
-
 	if (cpci405_version() >= 2) {
 		/*
 		 * Setup GPIO pins (CS6+CS7 as GPIO)
@@ -354,6 +359,7 @@ int misc_init_r (void)
 		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 		udelay(1000); /* wait 1ms */
 
+#ifdef CONFIG_CPCI405_6U
 		if (cpci405_version() == 3) {
 			volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
 			volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
@@ -375,6 +381,7 @@ int misc_init_r (void)
 			udelay(100);
 			*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
 		}
+#endif
 	}
 	else {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
@@ -493,12 +500,6 @@ int checkboard (void)
 #endif
 
 	putc ('\n');
-
-	/*
-	 * Disable sleep mode in LXT971
-	 */
-	lxt971_no_sleep();
-
 	return 0;
 }
 
@@ -511,24 +512,22 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
-/* ------------------------------------------------------------------------- */
 
-int testdram (void)
+void reset_phy(void)
 {
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
 
-	return (0);
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
 }
 
+
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_CPCI405_VER2
@@ -552,6 +551,41 @@ void ide_set_reset(int on)
 #endif /* CONFIG_CPCI405_VER2 */
 
 
+#if defined(CONFIG_PCI)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = 0xff;
+
+	/*
+	 * Write pci interrupt line register (cpci405 specific)
+	 */
+	switch (PCI_DEV(dev) & 0x03) {
+	case 0:
+		int_line = 27 + 2;
+		break;
+	case 1:
+		int_line = 27 + 3;
+		break;
+	case 2:
+		int_line = 27 + 0;
+		break;
+	case 3:
+		int_line = 27 + 1;
+		break;
+	}
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+	hose->fixup_irq = cpci405_pci_fixup_irq;
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+
 #ifdef CONFIG_CPCI405AB
 
 #define ONE_WIRE_CLEAR   (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile
new file mode 100644
index 0000000..06ef7f9
--- /dev/null
+++ b/board/lwmon5/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o sdram.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk
new file mode 100644
index 0000000..bf2b879
--- /dev/null
+++ b/board/lwmon5/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# lwmon5 (440EPx)
+#
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
new file mode 100644
index 0000000..6798e80
--- /dev/null
+++ b/board/lwmon5/init.S
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CFG_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for the FPGA Chip select 2 */
+	tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+
+	/* TLB-entry for the FPGA Chip select 3 */
+	tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
+
+	/* TLB-entry for the LIME Controller */
+	tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I)
+
+	/*TLB-entry PCI registers*/
+	tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/* TLB-entry for peripherals */
+	tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	tlbtab_end
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
new file mode 100644
index 0000000..d916284
--- /dev/null
+++ b/board/lwmon5/lwmon5.c
@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc440.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+ulong flash_get_size (ulong base, int banknum);
+
+int board_early_init_f(void)
+{
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	/* PLB Write pipelining disabled. Denali Core workaround */
+	mtdcr(plb0_acr, 0xDE000000);
+	mtdcr(plb1_acr, 0xDE000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
+	mtdcr(uic0er, 0x00000000);  /* disable all */
+	mtdcr(uic0cr, 0x00000000);  /* we have not critical interrupts at the moment */
+	mtdcr(uic0pr, 0xfffff7ff);  /* Adjustment of the polarity */
+	mtdcr(uic0tr, 0x00000810);  /* per ref-board manual */
+	mtdcr(uic0vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(uic0sr, 0xffffffff);  /* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);  /* clear all */
+	mtdcr(uic1er, 0x00000000);  /* disable all */
+	mtdcr(uic1cr, 0x00000000);  /* all non-critical */
+	mtdcr(uic1pr, 0xFFFFC7AD);  /* Adjustment of the polarity */
+	mtdcr(uic1tr, 0x0600384A);  /* per ref-board manual */
+	mtdcr(uic1vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(uic1sr, 0xffffffff);  /* clear all */
+
+	mtdcr(uic2sr, 0xffffffff);  /* clear all */
+	mtdcr(uic2er, 0x00000000);  /* disable all */
+	mtdcr(uic2cr, 0x00000000);  /* all non-critical */
+	mtdcr(uic2pr, 0x27C00000);  /* Adjustment of the polarity */
+	mtdcr(uic2tr, 0xDFC00000);  /* per ref-board manual */
+	mtdcr(uic2vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(uic2sr, 0xffffffff);  /* clear all. Why this??? */
+
+	/* Trace Pins are disabled. SDR0_PFC0 Register */
+	mtsdr(SDR0_PFC0, 0x0);
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	/* SMII via ZMII */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_6;
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_6;
+
+	/* enable SPI (SCP) */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	mtsdr(SDR0_PFC4, 0x80000000);
+
+	/* PCI arbiter disabled */
+	/* PCI Host Configuration disbaled */
+	mfsdr(sdr_pci0, reg);
+	reg = 0;
+	mtsdr(sdr_pci0, 0x00000000 | reg);
+
+	gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
+
+	return 0;
+}
+
+/*---------------------------------------------------------------------------+
+  | misc_init_r.
+  +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+	u32 pbcr;
+	int size_val = 0;
+	u32 reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	mfebc(pb0cr, pbcr);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtebc(pb0cr, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_ENV_ADDR_REDUND,
+			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+
+	/*
+	 * USB suff...
+	 */
+	/* SDR Setting */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_USB0, usb2d0cr);
+	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+
+	/* An 8-bit/60MHz interface is the only possible alternative
+	   when connecting the Device to the PHY */
+	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+	mtsdr(SDR0_USB0, usb2d0cr);
+	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	/*
+	 * Clear resets
+	 */
+	udelay (1000);
+	mtsdr(SDR0_SRST1, 0x00000000);
+	udelay (1000);
+	mtsdr(SDR0_SRST0, 0x00000000);
+
+	printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+	mtdcr(plb4_acr, reg);
+
+	/*
+	 * Reset Lime controller
+	 */
+	gpio_write_bit(CFG_GPIO_LIME_S, 1);
+	udelay(500);
+	gpio_write_bit(CFG_GPIO_LIME_RST, 1);
+
+	/* Lime memory clock adjusted to 133MHz */
+	out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+	/* Wait untill time expired. Because of requirements in lime manual */
+	udelay(300);
+	/* Write lime controller memory parameters */
+	out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+
+	/*
+	 * Reset PHY's
+	 */
+	gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
+	gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
+	udelay(100);
+	gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: lwmon5");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_MBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif	/* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440EPX PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Cactus is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
+
+void hw_watchdog_reset(void)
+{
+	int val;
+
+	/*
+	 * Toggle watchdog output
+	 */
+	val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
+	gpio_write_bit(CFG_GPIO_WATCHDOG, val);
+}
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
new file mode 100644
index 0000000..9a4a8ee
--- /dev/null
+++ b/board/lwmon5/sdram.c
@@ -0,0 +1,662 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <ppc440.h>
+
+#include "sdram.h"
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CFG_ENABLE_SDRAM_CACHE
+#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
+#endif
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void dcbz_area(u32 start_address, u32 num_bytes);
+void dflush(void);
+
+#ifdef CONFIG_ADD_RAM_INFO
+static u32 is_ecc_enabled(void)
+{
+	u32 val;
+
+	mfsdram(DDR0_22, val);
+	val &= DDR0_22_CTRL_RAW_MASK;
+	if (val)
+		return 1;
+	else
+		return 0;
+}
+
+void board_add_ram_info(int use_default)
+{
+	PPC440_SYS_INFO board_cfg;
+	u32 val;
+
+	if (is_ecc_enabled())
+		puts(" (ECC");
+	else
+		puts(" (ECC not");
+
+	get_sys_info(&board_cfg);
+	printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+	mfsdram(DDR0_03, val);
+	val = DDR0_03_CASLAT_DECODE(val);
+	printf(", CL%d)", val);
+}
+#endif
+
+static int wait_for_dlllock(void)
+{
+	u32 val;
+	int wait = 0;
+
+	/*
+	 * Wait for the DCC master delay line to finish calibration
+	 */
+	mtdcr(ddrcfga, DDR0_17);
+	val = DDR0_17_DLLLOCKREG_UNLOCKED;
+
+	while (wait != 0xffff) {
+		val = mfdcr(ddrcfgd);
+		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
+			/* dlllockreg bit on */
+			return 0;
+		else
+			wait++;
+	}
+	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+	debug("Waiting for dlllockreg bit to raise\n");
+
+	return -1;
+}
+
+#if defined(CONFIG_DDR_DATA_EYE)
+int wait_for_dram_init_complete(void)
+{
+	u32 val;
+	int wait = 0;
+
+	/*
+	 * Wait for 'DRAM initialization complete' bit in status register
+	 */
+	mtdcr(ddrcfga, DDR0_00);
+
+	while (wait != 0xffff) {
+		val = mfdcr(ddrcfgd);
+		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
+			/* 'DRAM initialization complete' bit */
+			return 0;
+		else
+			wait++;
+	}
+
+	debug("DRAM initialization complete bit in status register did not rise\n");
+
+	return -1;
+}
+
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
+{
+	int k, j;
+	u32 val;
+	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
+	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
+	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
+	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
+	volatile u32 *ram_pointer;
+	u32 test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	ram_pointer = (volatile u32 *)start_addr;
+
+	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
+		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
+
+		/*
+		 * De-assert 'start' parameter.
+		 */
+		mtdcr(ddrcfga, DDR0_02);
+		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+		mtdcr(ddrcfgd, val);
+
+		/*
+		 * Set 'wr_dqs_shift'
+		 */
+		mtdcr(ddrcfga, DDR0_09);
+		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+		mtdcr(ddrcfgd, val);
+
+		/*
+		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
+		 */
+		dqs_out_shift = wr_dqs_shift + 32;
+		mtdcr(ddrcfga, DDR0_22);
+		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+		mtdcr(ddrcfgd, val);
+
+		passing_cases = 0;
+
+		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
+			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
+			/*
+			 * Set 'dll_dqs_delay_X'.
+			 */
+			/* dll_dqs_delay_0 */
+			mtdcr(ddrcfga, DDR0_17);
+			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+			mtdcr(ddrcfgd, val);
+			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
+			mtdcr(ddrcfga, DDR0_18);
+			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+			mtdcr(ddrcfgd, val);
+			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
+			mtdcr(ddrcfga, DDR0_19);
+			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+			mtdcr(ddrcfgd, val);
+
+			ppcMsync();
+			ppcMbar();
+
+			/*
+			 * Assert 'start' parameter.
+			 */
+			mtdcr(ddrcfga, DDR0_02);
+			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+			mtdcr(ddrcfgd, val);
+
+			ppcMsync();
+			ppcMbar();
+
+			/*
+			 * Wait for the DCC master delay line to finish calibration
+			 */
+			if (wait_for_dlllock() != 0) {
+				printf("dlllock did not occur !!!\n");
+				printf("denali_core_search_data_eye!!!\n");
+				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
+				       wr_dqs_shift, dll_dqs_delay_X);
+				hang();
+			}
+			ppcMsync();
+			ppcMbar();
+
+			if (wait_for_dram_init_complete() != 0) {
+				printf("dram init complete did not occur !!!\n");
+				printf("denali_core_search_data_eye!!!\n");
+				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
+				       wr_dqs_shift, dll_dqs_delay_X);
+				hang();
+			}
+			udelay(100);  /* wait 100us to ensure init is really completed !!! */
+
+			/* write values */
+			for (j=0; j<NUM_TRIES; j++) {
+				ram_pointer[j] = test[j];
+
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+			}
+
+			/* read values back */
+			for (j=0; j<NUM_TRIES; j++) {
+				for (k=0; k<NUM_READS; k++) {
+					/* clear any cache at ram location */
+					__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+					if (ram_pointer[j] != test[j])
+						break;
+				}
+
+				/* read error */
+				if (k != NUM_READS)
+					break;
+			}
+
+			/* See if the dll_dqs_delay_X value passed.*/
+			if (j < NUM_TRIES) {
+				/* Failed */
+				passing_cases = 0;
+				/* break; */
+			} else {
+				/* Passed */
+				if (passing_cases == 0)
+					dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
+				passing_cases++;
+				if (passing_cases >= max_passing_cases) {
+					max_passing_cases = passing_cases;
+					wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
+					dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
+					dll_dqs_delay_X_end_window = dll_dqs_delay_X;
+				}
+			}
+
+			/*
+			 * De-assert 'start' parameter.
+			 */
+			mtdcr(ddrcfga, DDR0_02);
+			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+			mtdcr(ddrcfgd, val);
+
+		} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
+
+	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
+
+	/*
+	 * Largest passing window is now detected.
+	 */
+
+	/* Compute dll_dqs_delay_X value */
+	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
+	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
+
+	debug("DQS calibration - Window detected:\n");
+	debug("max_passing_cases = %d\n", max_passing_cases);
+	debug("wr_dqs_shift	 = %d\n", wr_dqs_shift);
+	debug("dll_dqs_delay_X	 = %d\n", dll_dqs_delay_X);
+	debug("dll_dqs_delay_X window = %d - %d\n",
+	      dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
+
+	/*
+	 * De-assert 'start' parameter.
+	 */
+	mtdcr(ddrcfga, DDR0_02);
+	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+	mtdcr(ddrcfgd, val);
+
+	/*
+	 * Set 'wr_dqs_shift'
+	 */
+	mtdcr(ddrcfga, DDR0_09);
+	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+		| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_09=0x%08lx\n", val);
+
+	/*
+	 * Set 'dqs_out_shift' = wr_dqs_shift + 32
+	 */
+	dqs_out_shift = wr_dqs_shift + 32;
+	mtdcr(ddrcfga, DDR0_22);
+	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+		| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_22=0x%08lx\n", val);
+
+	/*
+	 * Set 'dll_dqs_delay_X'.
+	 */
+	/* dll_dqs_delay_0 */
+	mtdcr(ddrcfga, DDR0_17);
+	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+		| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_17=0x%08lx\n", val);
+
+	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
+	mtdcr(ddrcfga, DDR0_18);
+	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+		| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+		| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+		| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+		| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_18=0x%08lx\n", val);
+
+	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
+	mtdcr(ddrcfga, DDR0_19);
+	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+		| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+		| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+		| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+		| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_19=0x%08lx\n", val);
+
+	/*
+	 * Assert 'start' parameter.
+	 */
+	mtdcr(ddrcfga, DDR0_02);
+	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+	mtdcr(ddrcfgd, val);
+
+	ppcMsync();
+	ppcMbar();
+
+	/*
+	 * Wait for the DCC master delay line to finish calibration
+	 */
+	if (wait_for_dlllock() != 0) {
+		printf("dlllock did not occur !!!\n");
+		hang();
+	}
+	ppcMsync();
+	ppcMbar();
+
+	if (wait_for_dram_init_complete() != 0) {
+		printf("dram init complete did not occur !!!\n");
+		hang();
+	}
+	udelay(100);  /* wait 100us to ensure init is really completed !!! */
+}
+#endif /* CONFIG_DDR_DATA_EYE */
+
+#ifdef CONFIG_DDR_ECC
+static void wait_ddr_idle(void)
+{
+	/*
+	 * Controller idle status cannot be determined for Denali
+	 * DDR2 code. Just return here.
+	 */
+}
+
+static void blank_string(int size)
+{
+	int i;
+
+	for (i=0; i<size; i++)
+		putc('\b');
+	for (i=0; i<size; i++)
+		putc(' ');
+	for (i=0; i<size; i++)
+		putc('\b');
+}
+
+static void program_ecc(u32 start_address,
+			u32 num_bytes,
+			u32 tlb_word2_i_value)
+{
+	u32 current_address;
+	u32 end_address;
+	u32 address_increment;
+	u32 val;
+	char str[] = "ECC generation -";
+	char slash[] = "\\|/-\\|/-";
+	int loop = 0;
+	int loopi = 0;
+
+	current_address = start_address;
+
+	sync();
+	eieio();
+	wait_ddr_idle();
+
+	if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
+		/* ECC bit set method for non-cached memory */
+		address_increment = 4;
+		end_address = current_address + num_bytes;
+
+		puts(str);
+
+		while (current_address < end_address) {
+			*((u32 *)current_address) = 0x00000000;
+			current_address += address_increment;
+
+			if ((loop++ % (2 << 20)) == 0) {
+				putc('\b');
+				putc(slash[loopi++ % 8]);
+			}
+		}
+
+		blank_string(strlen(str));
+	} else {
+		/* ECC bit set method for cached memory */
+#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+		/*
+		 * Some boards (like lwmon5) need to preserve the memory
+		 * content upon ECC generation (for the log-buffer).
+		 * Therefore we don't fill the memory with a pattern or
+		 * just zero it, but write the same values back that are
+		 * already in the memory cells.
+		 */
+		address_increment = CFG_CACHELINE_SIZE;
+		end_address = current_address + num_bytes;
+
+		current_address = start_address;
+		while (current_address < end_address) {
+			ppcDcbi(current_address);
+			ppcDcbf(current_address);
+			current_address += CFG_CACHELINE_SIZE;
+		}
+#else
+		dcbz_area(start_address, num_bytes);
+		dflush();
+#endif
+	}
+
+	sync();
+	eieio();
+	wait_ddr_idle();
+
+	/* Clear error status */
+	mfsdram(DDR0_00, val);
+	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+	/* Set 'int_mask' parameter to functionnal value */
+	mfsdram(DDR0_01, val);
+	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
+
+	sync();
+	eieio();
+	wait_ddr_idle();
+}
+#endif
+
+static __inline__ u32 get_mcsr(void)
+{
+	u32 val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static __inline__ void set_mcsr(u32 val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+	u32 val;
+
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
+	/* CL=3 */
+	mtsdram(DDR0_02, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
+
+	mtsdram(DDR0_04, 0x0A030300);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0103C812);
+	mtsdram(DDR0_07, 0x00090100);
+	mtsdram(DDR0_08, 0x02c80001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_11, 0x000CC800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x1e000000);
+	mtsdram(DDR0_18, 0x1e1e1e1e);
+	mtsdram(DDR0_19, 0x1e1e1e1e);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC	*/
+#else
+	mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+	mtsdram(DDR0_23, 0x01000000);
+	mtsdram(DDR0_24, 0x01010001);
+
+	mtsdram(DDR0_26, 0x2D93028A);
+	mtsdram(DDR0_27, 0x0784682B);
+
+	mtsdram(DDR0_28, 0x00000080);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000006);
+
+	mtsdram(DDR0_43, 0x030A0200);
+	mtsdram(DDR0_44, 0x00000003);
+	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#else
+	/* CL=4 */
+	mtsdram(DDR0_02, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+	mtsdram(DDR0_04, 0x0B030300);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0003C812);
+	mtsdram(DDR0_07, 0x00090100);
+	mtsdram(DDR0_08, 0x03c80001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_11, 0x000CC800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x1e000000);
+	mtsdram(DDR0_18, 0x1e1e1e1e);
+	mtsdram(DDR0_19, 0x1e1e1e1e);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
+#else
+	mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+	mtsdram(DDR0_23, 0x01000000);
+	mtsdram(DDR0_24, 0x01010001);
+
+	mtsdram(DDR0_26, 0x2D93028A);
+	mtsdram(DDR0_27, 0x0784682B);
+
+	mtsdram(DDR0_28, 0x00000080);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000008);
+
+	mtsdram(DDR0_43, 0x050A0200);
+	mtsdram(DDR0_44, 0x00000005);
+	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#endif
+
+	wait_for_dlllock();
+
+	/*
+	 * Program tlb entries for this size (dynamic)
+	 */
+	program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Setup 2nd TLB with same physical address but different virtual address
+	 * with cache enabled. This is done for fast ECC generation.
+	 */
+	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+
+#ifdef CONFIG_DDR_DATA_EYE
+	/*
+	 * Perform data eye search if requested.
+	 */
+	denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
+
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	val = get_mcsr();
+	set_mcsr(val);
+#endif
+
+#ifdef CONFIG_DDR_ECC
+	/*
+	 * If ECC is enabled, initialize the parity bits.
+	 */
+	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+#endif
+
+	return (CFG_MBYTES_SDRAM << 20);
+}
diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h
new file mode 100644
index 0000000..7f847aa
--- /dev/null
+++ b/board/lwmon5/sdram.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPD_SDRAM_DENALI_H_
+#define _SPD_SDRAM_DENALI_H_
+
+#define ppcMsync	sync
+#define ppcMbar		eieio
+
+/* General definitions */
+#define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
+#define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
+#define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
+#define SDRAM_NONE          0           /* No DIMM detected in Slot */
+#define MAXRANKS            2           /* 2 ranks maximum */
+
+/* Supported PLB Frequencies */
+#define PLB_FREQ_133MHZ     133333333
+#define PLB_FREQ_152MHZ     152000000
+#define PLB_FREQ_160MHZ     160000000
+#define PLB_FREQ_166MHZ     166666666
+
+/* Denali Core Registers */
+#define SDRAM_DCR_BASE 0x10
+
+#define DDR_DCR_BASE 0x10
+#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
+#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
+
+/*-----------------------------------------------------------------------------+
+  | Values for ddrcfga register - indirect addressing of these regs
+  +-----------------------------------------------------------------------------*/
+
+#define DDR0_00                         0x00
+#define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
+#define DDR0_00_INT_ACK_ALL               0x7F000000
+#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
+/* Status */
+#define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
+/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT0           0x00010000
+/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT1           0x00020000
+/* Bit2. Single correctable ECC event detected */
+#define DDR0_00_INT_STATUS_BIT2           0x00040000
+/* Bit3. Multiple correctable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT3           0x00080000
+/* Bit4. Single uncorrectable ECC event detected. */
+#define DDR0_00_INT_STATUS_BIT4           0x00100000
+/* Bit5. Multiple uncorrectable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT5           0x00200000
+/* Bit6. DRAM initialization complete. */
+#define DDR0_00_INT_STATUS_BIT6           0x00400000
+/* Bit7. Logical OR of all lower bits. */
+#define DDR0_00_INT_STATUS_BIT7           0x00800000
+
+#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
+#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
+#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+
+#define DDR0_01                         0x01
+#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
+#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
+#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
+#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_01_INT_MASK_MASK             0x000000FF
+#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
+#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
+
+#define DDR0_02                         0x02
+#define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
+#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
+#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
+#define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
+#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
+#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_02_START_MASK                0x00000001
+#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
+#define DDR0_02_START_OFF                 0x00000000
+#define DDR0_02_START_ON                  0x00000001
+
+#define DDR0_03                         0x03
+#define DDR0_03_BSTLEN_MASK               0x07000000
+#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_03_CASLAT_MASK               0x00070000
+#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
+#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_03_INITAREF_MASK             0x0000000F
+#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_04                         0x04
+#define DDR0_04_TRC_MASK                  0x1F000000
+#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_04_TRRD_MASK                 0x00070000
+#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_04_TRTP_MASK                 0x00000700
+#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
+
+#define DDR0_05                         0x05
+#define DDR0_05_TMRD_MASK                 0x1F000000
+#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_05_TEMRS_MASK                0x00070000
+#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_05_TRP_MASK                  0x00000F00
+#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_05_TRAS_MIN_MASK             0x000000FF
+#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
+
+#define DDR0_06                         0x06
+#define DDR0_06_WRITEINTERP_MASK          0x01000000
+#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_06_TWTR_MASK                 0x00070000
+#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_06_TDLL_MASK                 0x0000FF00
+#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_06_TRFC_MASK                 0x0000007F
+#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_07                         0x07
+#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
+#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_07_TFAW_MASK                 0x001F0000
+#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
+#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_07_AREFRESH_MASK             0x00000001
+#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_08                         0x08
+#define DDR0_08_WRLAT_MASK                0x07000000
+#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_08_TCPD_MASK                 0x00FF0000
+#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_08_DQS_N_EN_MASK             0x00000100
+#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
+#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_09                         0x09
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_09_RTT_0_MASK                0x00030000
+#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
+#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_10                         0x0A
+#define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
+#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_10_CS_MAP_MASK               0x00000300
+#define DDR0_10_CS_MAP_NO_MEM             0x00000000
+#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
+#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
+#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
+
+#define DDR0_11                         0x0B
+#define DDR0_11_SREFRESH_MASK             0x01000000
+#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_11_TXSNR_MASK                0x00FF0000
+#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_11_TXSR_MASK                 0x0000FF00
+#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
+
+#define DDR0_12                         0x0C
+#define DDR0_12_TCKE_MASK                 0x0000007
+#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
+#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
+
+#define DDR0_13                         0x0D
+
+#define DDR0_14                         0x0E
+#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
+#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_14_REDUC_MASK                0x00010000
+#define DDR0_14_REDUC_64BITS              0x00000000
+#define DDR0_14_REDUC_32BITS              0x00010000
+#define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
+#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
+
+#define DDR0_15                         0x0F
+
+#define DDR0_16                         0x10
+
+#define DDR0_17                         0x11
+#define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
+#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
+#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
+#define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_17_DLL_LOCK_MASK             0x00007F00 /* Read only */
+#define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
+
+#define DDR0_18                         0x12
+#define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
+#define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
+#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
+#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
+#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
+#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_19                         0x13
+#define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
+#define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
+#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
+#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
+#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
+#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_20                         0x14
+#define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
+#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
+#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
+#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
+#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_21                         0x15
+#define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
+#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
+#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
+#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
+#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_22                         0x16
+/* ECC */
+#define DDR0_22_CTRL_RAW_MASK             0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not being used */
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC checking is on, but no attempts to correct*/
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* No ECC RAM storage available */
+#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC checking and correcting on */
+#define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
+
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
+#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
+#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
+
+
+#define DDR0_23                         0x17
+#define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
+#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_23_ECC_C_SYND_MASK           0x00FF0000 /* Read only */
+#define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_23_ECC_U_SYND_MASK           0x0000FF00 /* Read only */
+#define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_23_FWC_MASK                  0x00000001 /* Write only */
+#define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_24                         0x18
+#define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
+#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
+#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
+#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
+#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
+#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
+
+#define DDR0_25                         0x19
+#define DDR0_25_VERSION_MASK              0xFFFF0000 /* Read only */
+#define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF /* Read only */
+#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_26                         0x1A
+#define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
+#define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_26_TREF_MASK                 0x00003FFF
+#define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_27                         0x1B
+#define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
+#define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_27_TINIT_MASK                0x0000FFFF
+#define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_28                         0x1C
+#define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
+#define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
+#define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
+
+#define DDR0_29                         0x1D
+
+#define DDR0_30                         0x1E
+
+#define DDR0_31                         0x1F
+#define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
+#define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_32                         0x20
+#define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF /* Read only */
+#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_33                         0x21
+#define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001 /* Read only */
+#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_34                         0x22
+#define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_35                         0x23
+#define DDR0_35_ECC_U_ADDR_MASK           0x00000001 /* Read only */
+#define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_36                         0x24
+#define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_37                         0x25
+#define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_38                         0x26
+#define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_39                         0x27
+#define DDR0_39_ECC_C_ADDR_MASK           0x00000001 /* Read only */
+#define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_40                         0x28
+#define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_41                         0x29
+#define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_42                         0x2A
+#define DDR0_42_ADDR_PINS_MASK            0x07000000
+#define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
+#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_43                         0x2B
+#define DDR0_43_TWR_MASK                  0x07000000
+#define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_43_APREBIT_MASK              0x000F0000
+#define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_43_COLUMN_SIZE_MASK          0x00000700
+#define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
+#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_44                         0x2C
+#define DDR0_44_TRCD_MASK                 0x000000FF
+#define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
+
+#endif /* _SPD_SDRAM_DENALI_H_ */
diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds
new file mode 100644
index 0000000..a423f98
--- /dev/null
+++ b/board/lwmon5/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 8858f0a..b73ab2a 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -217,7 +217,7 @@ int testdram(void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
@@ -258,7 +258,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index 5abc87d..b764499 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -172,7 +172,7 @@ int testdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -192,7 +192,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 2f28e9d..1a8aacb 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -176,7 +176,7 @@ int misc_init_r (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long strap;
@@ -193,7 +193,7 @@ int pci_pre_init(struct pci_controller *hose)
 
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index 7816472..8a831fa 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -313,7 +313,7 @@ long int fixed_sdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -330,7 +330,7 @@ int pci_pre_init(struct pci_controller * hose )
 
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S
index a5de806..a7959f3 100644
--- a/board/smdk2400/lowlevel_init.S
+++ b/board/smdk2400/lowlevel_init.S
@@ -117,7 +117,7 @@
 #define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
 #define Trp	0x0	/* 2 clk */
 #define Trc	0x3	/* 7 clk */
-#define Tchr	0x2 	/* 3 clk */
+#define Tchr	0x2	/* 3 clk */
 
 #define REFCNT	1113	/* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */
 
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 0fb233d..5882124 100644
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -52,147 +52,147 @@ long int fixed_sdram (void);
 const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 TxClav	*/
+	/* PA29 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[0] */
+	/* PA9	*/ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 L1TXD */
+	/* PA8	*/ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 L1RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   1,	 1,   1,   0,	0   }, /* TDM A1 L1RSYNC */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   1,   0,	 0,   0,   0,	0   }, /* FREERUN */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
     },
 
     /* Port B configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB9	*/ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB8	*/ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB7	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB6	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB5	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB4	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
     },
 
     /* Port C */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
-	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,	 0,   0,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   1,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FETHMDC */
+	/* PC9	*/ {   0,   0,	 0,   0,   0,	0   }, /* FETHMDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
     },
 
     /* Port D */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
-	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TxD */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   0,   0   }, /* I2C CLK */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC2 TxD */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
+	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
+	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
+	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
+	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
+	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
+	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD18 */
+	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,	 1,   0,   0,	0   }, /* I2C CLK */
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
+	/* PD8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
     }
 };
 
@@ -227,12 +227,12 @@ reset_phy(void)
 #if (CONFIG_ETHER_INDEX == 2)
 	bcsr->bcsr2 &= ~FETH2_RST;
 	udelay(2);
-	bcsr->bcsr2 |=  FETH2_RST;
+	bcsr->bcsr2 |=	FETH2_RST;
 	udelay(1000);
 #elif (CONFIG_ETHER_INDEX == 3)
 	bcsr->bcsr3 &= ~FETH3_RST;
 	udelay(2);
-	bcsr->bcsr3 |=  FETH3_RST;
+	bcsr->bcsr3 |=	FETH3_RST;
 	udelay(1000);
 #endif
 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
@@ -252,10 +252,10 @@ int
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_pcix_t *pci = &immr->im_pcix;
 
-    pci->peer &= 0xfffffffdf; /* disable master abort */
+	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
 
 	/* Why is the phy reset done _after_ the ethernet
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index a569b53..8411cf0 100644
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -209,7 +209,7 @@ long int fixed_sdram (void)
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller * hose )
 {
 	unsigned long strap;
@@ -227,7 +227,7 @@ int pci_pre_init(struct pci_controller * hose )
 #endif
 	return 1;
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
diff --git a/common/Makefile b/common/Makefile
index bc1f714..ef7d097 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -38,8 +38,8 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
-	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
-	  cmd_usb.o cmd_vfd.o \
+	  cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
+	  cmd_universe.o cmd_usb.o cmd_vfd.o \
 	  command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
diff --git a/common/cmd_log.c b/common/cmd_log.c
index 042a403..fba8bd8 100644
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2007
  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
  *
  * Code used from linux/kernel/printk.c
@@ -60,45 +60,40 @@ static char buf[1024];
 /* This combination will not print messages with the default loglevel */
 static unsigned console_loglevel = 3;
 static unsigned default_message_loglevel = 4;
-static unsigned char *log_buf = NULL;
-static unsigned long *ext_log_size;
-static unsigned long *ext_log_start;
-static unsigned long *ext_logged_chars;
-#define log_size (*ext_log_size)
-#define log_start (*ext_log_start)
-#define logged_chars (*ext_logged_chars)
+static unsigned log_version = 1;
+static logbuff_t *log;
 
-/* Forced by code, eh! */
-#define LOGBUFF_MAGIC 0xc0de4ced
-
-/* The mapping used here has to be the same as in setup_ext_logbuff ()
-   in linux/kernel/printk */
 void logbuff_init_ptrs (void)
 {
-	unsigned long *ext_tag;
-	unsigned long post_word;
+	unsigned long tag, post_word;
 	char *s;
 
-	log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
-	ext_tag = (unsigned long *)(log_buf)-4;
- 	ext_log_start = (unsigned long *)(log_buf)-3;
-	ext_log_size = (unsigned long *)(log_buf)-2;
-	ext_logged_chars = (unsigned long *)(log_buf)-1;
+	log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1;
+
+	/* Set up log version */
+	if ((s = getenv ("logversion")) != NULL)
+		log_version = (int)simple_strtoul (s, NULL, 10);
+
+	if (log_version == 2)
+		tag = log->v2.tag;
+	else
+		tag = log->v1.tag;
 	post_word = post_word_load();
 #ifdef CONFIG_POST
 	/* The post routines have setup the word so we can simply test it */
- 	if (post_word_load () & POST_COLDBOOT) {
- 		logged_chars = log_size = log_start = 0;
-		*ext_tag = LOGBUFF_MAGIC;
- 	}
+	if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
+		logbuff_reset ();
+	}
 #else
 	/* No post routines, so we do our own checking                    */
- 	if (post_word != LOGBUFF_MAGIC) {
- 		logged_chars = log_size = log_start = 0;
+	if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
+		logbuff_reset ();
 		post_word_store (LOGBUFF_MAGIC);
-		*ext_tag = LOGBUFF_MAGIC;
- 	}
+	}
 #endif
+	if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
+		log->v2.start = log->v2.con;
+
 	/* Initialize default loglevel if present */
 	if ((s = getenv ("loglevel")) != NULL)
 		console_loglevel = (int)simple_strtoul (s, NULL, 10);
@@ -106,6 +101,15 @@ void logbuff_init_ptrs (void)
 	gd->post_log_word |= LOGBUFF_INITIALIZED;
 }
 
+void logbuff_reset (void)
+{
+	memset (log, 0, sizeof (logbuff_t));
+	if (log_version == 2)
+		log->v2.tag = LOGBUFF_MAGIC;
+	else
+		log->v1.tag = LOGBUFF_MAGIC;
+}
+
 int drv_logbuff_init (void)
 {
 	device_t logdev;
@@ -162,7 +166,7 @@ void logbuff_log(char *msg)
 int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char *s;
-	unsigned long i;
+	unsigned long i, start, size;
 
 	if (strcmp(argv[1],"append") == 0) {
 		/* Log concatenation of all arguments separated by spaces */
@@ -177,21 +181,34 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	case 2:
 		if (strcmp(argv[1],"show") == 0) {
-			for (i=0; i < (log_size&LOGBUFF_MASK); i++) {
-				s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK);
+			if (log_version == 2) {
+				start = log->v2.start;
+				size = log->v2.end - log->v2.start;
+			}
+			else {
+				start = log->v1.start;
+				size = log->v1.size;
+			}
+			for (i=0; i < (size&LOGBUFF_MASK); i++) {
+				s = (char *)log->buf+((start+i)&LOGBUFF_MASK);
 				putc (*s);
 			}
 			return 0;
 		} else if (strcmp(argv[1],"reset") == 0) {
-			log_start    = 0;
-			log_size     = 0;
-			logged_chars = 0;
+			logbuff_reset ();
 			return 0;
 		} else if (strcmp(argv[1],"info") == 0) {
-			printf ("Logbuffer   at  %08lx\n", (unsigned long)log_buf);
-			printf ("log_start    =  %08lx\n", log_start);
-			printf ("log_size     =  %08lx\n", log_size);
-			printf ("logged_chars =  %08lx\n", logged_chars);
+			printf ("Logbuffer   at  %08lx\n", (unsigned long)log->buf);
+			if (log_version == 2) {
+				printf ("log_start    =  %08lx\n", log->v2.start);
+				printf ("log_end      =  %08lx\n", log->v2.end);
+				printf ("logged_chars =  %08lx\n", log->v2.chars);
+			}
+			else {
+				printf ("log_start    =  %08lx\n", log->v1.start);
+				printf ("log_size     =  %08lx\n", log->v1.size);
+				printf ("logged_chars =  %08lx\n", log->v1.chars);
+			}
 			return 0;
 		}
 		printf ("Usage:\n%s\n", cmdtp->usage);
@@ -202,7 +219,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 }
-#if defined(CONFIG_LOGBUFFER)
+
 U_BOOT_CMD(
 	log,     255,	1,	do_log,
 	"log     - manipulate logbuffer\n",
@@ -211,7 +228,7 @@ U_BOOT_CMD(
 	"log show   - show contents\n"
 	"log append <msg> - append <msg> to the logbuffer\n"
 );
-#endif	/* CONFIG_LOGBUFFER */
+
 static int logbuff_printk(const char *line)
 {
 	int i;
@@ -241,13 +258,22 @@ static int logbuff_printk(const char *line)
 		}
 		line_feed = 0;
 		for (; p < buf_end; p++) {
-			log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p;
-			if (log_size < LOGBUFF_LEN)
-				log_size++;
-			else
-				log_start++;
-
-			logged_chars++;
+			if (log_version == 2) {
+				log->buf[log->v2.end & LOGBUFF_MASK] = *p;
+				log->v2.end++;
+				if (log->v2.end - log->v2.start > LOGBUFF_LEN)
+					log->v2.start++;
+				log->v2.chars++;
+			}
+			else {
+				log->buf[(log->v1.start + log->v1.size) &
+					 LOGBUFF_MASK] = *p;
+				if (log->v1.size < LOGBUFF_LEN)
+					log->v1.size++;
+				else
+					log->v1.start++;
+				log->v1.chars++;
+			}
 			if (*p == '\n') {
 				line_feed = 1;
 				break;
diff --git a/common/cmd_sata.c b/common/cmd_sata.c
new file mode 100644
index 0000000..bd4c11f
--- /dev/null
+++ b/common/cmd_sata.c
@@ -0,0 +1,712 @@
+/*
+ * Copyright (C) Procsys. All rights reserved.
+ * Author: Mushtaq Khan <mushtaq_k@procsys.com>
+ *			<mushtaqk_921@yahoo.co.in>
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * with the reference to libata in kernel 2.4.32
+ *
+ */
+
+/*
+ * File contains SATA read-write and other utility functions.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <command.h>
+#include <config.h>
+#include <ide.h>
+#include <ata.h>
+
+#ifdef CFG_SATA_SUPPORTED
+/*For debug prints set macro DEBUG_SATA to 1 */
+#define DEBUG_SATA 0
+/*Macro for SATA library specific declarations */
+#define SATA_DECL
+#include <sata.h>
+#undef SATA_DECL
+
+static u8 __inline__
+sata_inb (unsigned long ioaddr)
+{
+	return inb (ioaddr);
+}
+
+static void __inline__
+sata_outb (unsigned char val, unsigned long ioaddr)
+{
+	outb (val, ioaddr);
+}
+
+static void
+output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
+{
+	outsw (ioaddr->data_addr, sect_buf, words << 1);
+}
+
+static int
+input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
+{
+	insw (ioaddr->data_addr, sect_buf, words << 1);
+	return 0;
+}
+
+static void
+sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
+{
+	unsigned char *end, *last;
+
+	last = dst;
+	end = src + len - 1;
+
+	/* reserve space for '\0' */
+	if (len < 2)
+		goto OUT;
+
+	/* skip leading white space */
+	while ((*src) && (src < end) && (*src == ' '))
+		++src;
+
+	/* copy string, omitting trailing white space */
+	while ((*src) && (src < end)) {
+		*dst++ = *src;
+		if (*src++ != ' ')
+			last = dst;
+	}
+      OUT:
+	*last = '\0';
+}
+
+int
+sata_bus_softreset (int num)
+{
+	u8 dev = 0, status = 0, i;
+
+	port[num].dev_mask = 0;
+
+	for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) {
+		if (!(sata_devchk (&port[num].ioaddr, i))) {
+			PRINTF ("dev_chk failed for dev#%d\n", i);
+		} else {
+			port[num].dev_mask |= (1 << i);
+			PRINTF ("dev_chk passed for dev#%d\n", i);
+		}
+	}
+
+	if (!(port[num].dev_mask)) {
+		printf ("no devices on port%d\n", num);
+		return 1;
+	}
+
+	dev_select (&port[num].ioaddr, dev);
+
+	port[num].ctl_reg = 0x08;	/*Default value of control reg */
+	sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
+	udelay (10);
+	sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
+	udelay (10);
+	sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
+
+	/* spec mandates ">= 2ms" before checking status.
+	 * We wait 150ms, because that was the magic delay used for
+	 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
+	 * between when the ATA command register is written, and then
+	 * status is checked.  Because waiting for "a while" before
+	 * checking status is fine, post SRST, we perform this magic
+	 * delay here as well.
+	 */
+	msleep (150);
+	status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
+	while ((status & ATA_BUSY)) {
+		msleep (100);
+		status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
+	}
+
+	if (status & ATA_BUSY)
+		printf ("ata%u is slow to respond,plz be patient\n", port);
+
+	while ((status & ATA_BUSY)) {
+		msleep (100);
+		status = sata_chk_status (&port[num].ioaddr);
+	}
+
+	if (status & ATA_BUSY) {
+		printf ("ata%u failed to respond : ", port);
+		printf ("bus reset failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+void
+sata_identify (int num, int dev)
+{
+	u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev;
+	u16 iobuf[ATA_SECT_SIZE];
+	u64 n_sectors = 0;
+	u8 mask = 0;
+
+	memset (iobuf, 0, sizeof (iobuf));
+	hd_driveid_t *iop = (hd_driveid_t *) iobuf;
+
+	if (dev == 0)
+		mask = 0x01;
+	else
+		mask = 0x02;
+
+	if (!(port[num].dev_mask & mask)) {
+		printf ("dev%d is not present on port#%d\n", dev, num);
+		return;
+	}
+
+	printf ("port=%d dev=%d\n", num, dev);
+
+	dev_select (&port[num].ioaddr, dev);
+
+	status = 0;
+	cmd = ATA_CMD_IDENT;	/*Device Identify Command */
+	sata_outb (cmd, port[num].ioaddr.command_addr);
+	sata_inb (port[num].ioaddr.altstatus_addr);
+	udelay (10);
+
+	status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
+	if (status & ATA_ERR) {
+		printf ("\ndevice not responding\n");
+		port[num].dev_mask &= ~mask;
+		return;
+	}
+
+	input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
+
+	PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
+		"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
+		iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
+		iobuf[87], iobuf[88]);
+
+	/* we require LBA and DMA support (bits 8 & 9 of word 49) */
+	if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
+		PRINTF ("ata%u: no dma/lba\n", num);
+	}
+	ata_dump_id (iobuf);
+
+	if (ata_id_has_lba48 (iobuf)) {
+		n_sectors = ata_id_u64 (iobuf, 100);
+	} else {
+		n_sectors = ata_id_u32 (iobuf, 60);
+	}
+	PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
+	PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
+
+	if (n_sectors == 0) {
+		port[num].dev_mask &= ~mask;
+		return;
+	}
+
+	sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
+		  sizeof (sata_dev_desc[devno].revision));
+	sata_cpy (sata_dev_desc[devno].vendor, iop->model,
+		  sizeof (sata_dev_desc[devno].vendor));
+	sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
+		  sizeof (sata_dev_desc[devno].product));
+	strswab (sata_dev_desc[devno].revision);
+	strswab (sata_dev_desc[devno].vendor);
+
+	if ((iop->config & 0x0080) == 0x0080) {
+		sata_dev_desc[devno].removable = 1;
+	} else {
+		sata_dev_desc[devno].removable = 0;
+	}
+
+	sata_dev_desc[devno].lba = iop->lba_capacity;
+	PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
+
+#ifdef CONFIG_LBA48
+	if (iop->command_set_2 & 0x0400) {
+		sata_dev_desc[devno].lba48 = 1;
+		lba = (unsigned long long) iop->lba48_capacity[0] |
+		    ((unsigned long long) iop->lba48_capacity[1] << 16) |
+		    ((unsigned long long) iop->lba48_capacity[2] << 32) |
+		    ((unsigned long long) iop->lba48_capacity[3] << 48);
+	} else {
+		sata_dev_desc[devno].lba48 = 0;
+	}
+#endif
+
+	/* assuming HD */
+	sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
+	sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
+	sata_dev_desc[devno].lun = 0;	/* just to fill something in... */
+}
+
+void
+set_Feature_cmd (int num, int dev)
+{
+	u8 mask = 0x00, status = 0;
+
+	if (dev == 0)
+		mask = 0x01;
+	else
+		mask = 0x02;
+
+	if (!(port[num].dev_mask & mask)) {
+		PRINTF ("dev%d is not present on port#%d\n", dev, num);
+		return;
+	}
+
+	dev_select (&port[num].ioaddr, dev);
+
+	sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
+	sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
+	sata_outb (0, port[num].ioaddr.lbal_addr);
+	sata_outb (0, port[num].ioaddr.lbam_addr);
+	sata_outb (0, port[num].ioaddr.lbah_addr);
+
+	sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
+	sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
+
+	udelay (50);
+	msleep (150);
+
+	status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
+	if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
+		printf ("Error  : status 0x%02x\n", status);
+		port[num].dev_mask &= ~mask;
+	}
+}
+
+void
+sata_port (struct sata_ioports *ioport)
+{
+	ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
+	ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
+	ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
+	ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
+	ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
+	ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
+	ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
+	ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
+	ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
+	ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
+}
+
+int
+sata_devchk (struct sata_ioports *ioaddr, int dev)
+{
+	u8 nsect, lbal;
+
+	dev_select (ioaddr, dev);
+
+	sata_outb (0x55, ioaddr->nsect_addr);
+	sata_outb (0xaa, ioaddr->lbal_addr);
+
+	sata_outb (0xaa, ioaddr->nsect_addr);
+	sata_outb (0x55, ioaddr->lbal_addr);
+
+	sata_outb (0x55, ioaddr->nsect_addr);
+	sata_outb (0xaa, ioaddr->lbal_addr);
+
+	nsect = sata_inb (ioaddr->nsect_addr);
+	lbal = sata_inb (ioaddr->lbal_addr);
+
+	if ((nsect == 0x55) && (lbal == 0xaa))
+		return 1;	/* we found a device */
+	else
+		return 0;	/* nothing found */
+}
+
+void
+dev_select (struct sata_ioports *ioaddr, int dev)
+{
+	u8 tmp = 0;
+
+	if (dev == 0)
+		tmp = ATA_DEVICE_OBS;
+	else
+		tmp = ATA_DEVICE_OBS | ATA_DEV1;
+
+	sata_outb (tmp, ioaddr->device_addr);
+	sata_inb (ioaddr->altstatus_addr);
+	udelay (5);
+}
+
+u8
+sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
+{
+	u8 status;
+
+	do {
+		udelay (1000);
+		status = sata_chk_status (ioaddr);
+		max--;
+	} while ((status & bits) && (max > 0));
+
+	return status;
+}
+
+u8
+sata_chk_status (struct sata_ioports * ioaddr)
+{
+	return sata_inb (ioaddr->status_addr);
+}
+
+void
+msleep (int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++)
+		udelay (1000);
+}
+
+ulong
+sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
+{
+	ulong n = 0, *buffer = (ulong *)buff;
+	u8 dev = 0, num = 0, mask = 0, status = 0;
+
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
+
+	if (blknr & 0x0000fffff0000000) {
+		if (!sata_dev_desc[devno].lba48) {
+			printf ("Drive doesn't support 48-bit addressing\n");
+			return 0;
+		}
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
+	/*Port Number */
+	num = device / CFG_SATA_DEVS_PER_BUS;
+	/*dev on the port */
+	if (device >= CFG_SATA_DEVS_PER_BUS)
+		dev = device - CFG_SATA_DEVS_PER_BUS;
+	else
+		dev = device;
+
+	if (dev == 0)
+		mask = 0x01;
+	else
+		mask = 0x02;
+
+	if (!(port[num].dev_mask & mask)) {
+		printf ("dev%d is not present on port#%d\n", dev, num);
+		return 0;
+	}
+
+	/* Select device */
+	dev_select (&port[num].ioaddr, dev);
+
+	status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+	if (status & ATA_BUSY) {
+		printf ("ata%u failed to respond\n", port[num].port_no);
+		return n;
+	}
+	while (blkcnt-- > 0) {
+		status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+		if (status & ATA_BUSY) {
+			printf ("ata%u failed to respond\n", 0);
+			return n;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			sata_outb (0, port[num].ioaddr.nsect_addr);
+			sata_outb ((blknr >> 24) & 0xFF,
+				   port[num].ioaddr.lbal_addr);
+			sata_outb ((blknr >> 32) & 0xFF,
+				   port[num].ioaddr.lbam_addr);
+			sata_outb ((blknr >> 40) & 0xFF,
+				   port[num].ioaddr.lbah_addr);
+		}
+#endif
+		sata_outb (1, port[num].ioaddr.nsect_addr);
+		sata_outb (((blknr) >> 0) & 0xFF,
+			   port[num].ioaddr.lbal_addr);
+		sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
+		sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
+
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
+			sata_outb (ATA_CMD_READ_EXT,
+				   port[num].ioaddr.command_addr);
+		} else
+#endif
+		{
+			sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
+				   port[num].ioaddr.device_addr);
+			sata_outb (ATA_CMD_READ,
+				   port[num].ioaddr.command_addr);
+		}
+
+		msleep (50);
+		/*may take up to 4 sec */
+		status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
+
+		if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
+		    != ATA_STAT_DRQ) {
+			u8 err = 0;
+
+			printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
+				device, (ulong) blknr, status);
+			err = sata_inb (port[num].ioaddr.error_addr);
+			printf ("Error reg = 0x%x\n", err);
+			return (n);
+		}
+		input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
+		sata_inb (port[num].ioaddr.altstatus_addr);
+		udelay (50);
+
+		++n;
+		++blknr;
+		buffer += ATA_SECTORWORDS;
+	}
+	return n;
+}
+
+ulong
+sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
+{
+	ulong n = 0, *buffer = (ulong *)buff;
+	unsigned char status = 0, num = 0, dev = 0, mask = 0;
+
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
+
+	if (blknr & 0x0000fffff0000000) {
+		if (!sata_dev_desc[devno].lba48) {
+			printf ("Drive doesn't support 48-bit addressing\n");
+			return 0;
+		}
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
+	/*Port Number */
+	num = device / CFG_SATA_DEVS_PER_BUS;
+	/*dev on the Port */
+	if (device >= CFG_SATA_DEVS_PER_BUS)
+		dev = device - CFG_SATA_DEVS_PER_BUS;
+	else
+		dev = device;
+
+	if (dev == 0)
+		mask = 0x01;
+	else
+		mask = 0x02;
+
+	/* Select device */
+	dev_select (&port[num].ioaddr, dev);
+
+	status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+	if (status & ATA_BUSY) {
+		printf ("ata%u failed to respond\n", port[num].port_no);
+		return n;
+	}
+
+	while (blkcnt-- > 0) {
+		status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+		if (status & ATA_BUSY) {
+			printf ("ata%u failed to respond\n",
+				port[num].port_no);
+			return n;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			sata_outb (0, port[num].ioaddr.nsect_addr);
+			sata_outb ((blknr >> 24) & 0xFF,
+				   port[num].ioaddr.lbal_addr);
+			sata_outb ((blknr >> 32) & 0xFF,
+				   port[num].ioaddr.lbam_addr);
+			sata_outb ((blknr >> 40) & 0xFF,
+				   port[num].ioaddr.lbah_addr);
+		}
+#endif
+		sata_outb (1, port[num].ioaddr.nsect_addr);
+		sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
+		sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
+		sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
+			sata_outb (ATA_CMD_WRITE_EXT,
+				   port[num].ioaddr.command_addr);
+		} else
+#endif
+		{
+			sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
+				   port[num].ioaddr.device_addr);
+			sata_outb (ATA_CMD_WRITE,
+				   port[num].ioaddr.command_addr);
+		}
+
+		msleep (50);
+		/*may take up to 4 sec */
+		status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
+		if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
+		    != ATA_STAT_DRQ) {
+			printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
+				device, (ulong) blknr, status);
+			return (n);
+		}
+
+		output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
+		sata_inb (port[num].ioaddr.altstatus_addr);
+		udelay (50);
+
+		++n;
+		++blknr;
+		buffer += ATA_SECTORWORDS;
+	}
+	return n;
+}
+
+block_dev_desc_t *sata_get_dev (int dev);
+
+block_dev_desc_t *
+sata_get_dev (int dev)
+{
+	return ((block_dev_desc_t *) & sata_dev_desc[dev]);
+}
+
+int
+do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+
+	switch (argc) {
+	case 0:
+	case 1:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 2:
+		if (strncmp (argv[1], "init", 4) == 0) {
+			int rcode = 0;
+
+			rcode = init_sata ();
+			if (rcode)
+				printf ("Sata initialization Failed\n");
+			return rcode;
+		} else if (strncmp (argv[1], "inf", 3) == 0) {
+			int i;
+
+			putc ('\n');
+			for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) {
+				/*List only known devices */
+				if (sata_dev_desc[i].type ==
+				    DEV_TYPE_UNKNOWN)
+					continue;
+				printf ("sata dev %d: ", i);
+				dev_print (&sata_dev_desc[i]);
+			}
+			return 0;
+		}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 3:
+		if (strcmp (argv[1], "dev") == 0) {
+			int dev = (int) simple_strtoul (argv[2], NULL, 10);
+
+			if (dev >= CFG_SATA_MAXDEVICES) {
+				printf ("\nSata dev %d not available\n",
+					dev);
+				return 1;
+			}
+			printf ("\nSATA dev %d: ", dev);
+			dev_print (&sata_dev_desc[dev]);
+			if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
+				return 1;
+			curr_dev = dev;
+			return 0;
+		} else if (strcmp (argv[1], "part") == 0) {
+			int dev = (int) simple_strtoul (argv[2], NULL, 10);
+
+			if (dev >= CFG_SATA_MAXDEVICES) {
+				printf ("\nSata dev %d not available\n",
+					dev);
+				return 1;
+			}
+			PRINTF ("\nSATA dev %d: ", dev);
+			if (sata_dev_desc[dev].part_type !=
+			    PART_TYPE_UNKNOWN) {
+				print_part (&sata_dev_desc[dev]);
+			} else {
+				printf ("\nSata dev %d partition type "
+					"unknown\n", dev);
+				return 1;
+			}
+			return 0;
+		}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	default:
+		if (argc < 5) {
+			printf ("Usage:\n%s\n", cmdtp->usage);
+			return 1;
+		}
+		if (strcmp (argv[1], "read") == 0) {
+			ulong addr = simple_strtoul (argv[2], NULL, 16);
+			ulong cnt = simple_strtoul (argv[4], NULL, 16);
+			ulong n;
+			lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
+
+			memset ((int *) addr, 0, cnt * 512);
+			printf ("\nSATA read: dev %d blk # %ld,"
+				"count %ld ... ", curr_dev, blk, cnt);
+			n = sata_read (curr_dev, blk, cnt, (ulong *) addr);
+			/* flush cache after read */
+			flush_cache (addr, cnt * 512);
+			printf ("%ld blocks read: %s\n", n,
+				(n == cnt) ? "OK" : "ERR");
+			if (n == cnt)
+				return 1;
+			else
+				return 0;
+		} else if (strcmp (argv[1], "write") == 0) {
+			ulong addr = simple_strtoul (argv[2], NULL, 16);
+			ulong cnt = simple_strtoul (argv[4], NULL, 16);
+			ulong n;
+			lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
+
+			printf ("\nSata write: dev %d blk # %ld,"
+				"count %ld ... ", curr_dev, blk, cnt);
+			n = sata_write (curr_dev, blk, cnt, (ulong *) addr);
+			printf ("%ld blocks written: %s\n", n,
+				(n == cnt) ? "OK" : "ERR");
+			if (n == cnt)
+				return 1;
+			else
+				return 0;
+		} else {
+			printf ("Usage:\n%s\n", cmdtp->usage);
+			return 1;
+		}
+	}			/*End OF SWITCH */
+}
+
+U_BOOT_CMD (sata, 5, 1, do_sata,
+	    "sata init\n"
+	    "sata info\n"
+	    "sata part device\n"
+	    "sata dev device\n"
+	    "sata read  addr blk# cnt\n"
+	    "sata write  addr blk# cnt\n", "cmd for init,rw and dev-info\n");
+
+#endif
diff --git a/common/main.c b/common/main.c
index 553ac35..a00ebc1 100644
--- a/common/main.c
+++ b/common/main.c
@@ -113,7 +113,7 @@ static __inline__ int abortboot(int bootdelay)
 	u_int i;
 
 #  ifdef CONFIG_AUTOBOOT_PROMPT
-	printf (CONFIG_AUTOBOOT_PROMPT, bootdelay);
+	printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
 #  endif
 
 #  ifdef CONFIG_AUTOBOOT_DELAY_STR
@@ -187,7 +187,7 @@ static __inline__ int abortboot(int bootdelay)
 	}
 #  if DEBUG_BOOTKEYS
 	if (!abort)
-		puts ("key timeout\n");
+		puts("key timeout\n");
 #  endif
 
 #ifdef CONFIG_SILENT_CONSOLE
@@ -244,13 +244,13 @@ static __inline__ int abortboot(int bootdelay)
 # endif
 				break;
 			}
-			udelay (10000);
+			udelay(10000);
 		}
 
-		printf ("\b\b\b%2d ", bootdelay);
+		printf("\b\b\b%2d ", bootdelay);
 	}
 
-	putc ('\n');
+	putc('\n');
 
 #ifdef CONFIG_SILENT_CONSOLE
 	if (abort)
@@ -962,7 +962,7 @@ int readline (const char *const prompt)
 			n = 0;
 			continue;
 
-		case 0x17:				/* ^W - erase word 	*/
+		case 0x17:				/* ^W - erase word	*/
 			p=delete_char(console_buffer, p, &col, &n, plen);
 			while ((n > 0) && (*p != ' ')) {
 				p=delete_char(console_buffer, p, &col, &n, plen);
diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 1143038..b5834b9 100644
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -125,7 +125,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -143,7 +143,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index afcbb24..1a54dd1 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -149,7 +149,7 @@ data_ok:
 .progress3:
 
 	/* clear bss section in ram, size must be 4-byte aligned  */
-	movl	$_i386boot_bss_start, %eax        /* BSS start */
+	movl	$_i386boot_bss_start, %edi        /* MK_CHG BSS start */
 	movl	$_i386boot_bss_size, %ecx         /* BSS size */
 	movl	%ecx, %eax
 	andl	$3, %eax
diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S
index 087435e..0637003 100644
--- a/cpu/mpc5xx/start.S
+++ b/cpu/mpc5xx/start.S
@@ -155,7 +155,7 @@ in_flash:
 	/* Initialize some SPRs that are hard to access from C			*/
 	/*----------------------------------------------------------------------*/
 
-	lis     r3, CFG_IMMR@h          	/* Pass IMMR as arg1 to C routine */
+	lis     r3, CFG_IMMR@h			/* Pass IMMR as arg1 to C routine */
 	lis	r2, CFG_INIT_SP_ADDR@h
 	ori	r1, r2, CFG_INIT_SP_ADDR@l	/* Set up the stack in internal SRAM */
 	/* Note: R0 is still 0 here */
@@ -210,7 +210,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -228,7 +228,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 3936b55..9b1bd48 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -208,7 +208,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -227,7 +227,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S
index 5233202..b5145ca 100644
--- a/cpu/mpc8220/start.S
+++ b/cpu/mpc8220/start.S
@@ -169,7 +169,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -188,7 +188,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16	    /* copy EE bit from saved MSR */
diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S
index 9ff052c..784edc3 100644
--- a/cpu/mpc824x/start.S
+++ b/cpu/mpc824x/start.S
@@ -220,7 +220,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = EXC_OFF_ALIGN
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -238,7 +238,7 @@ Alignment:
 /* Program check exception */
 	. = EXC_OFF_PROGRAM
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S
index 2e93bbb..7f5dc81 100644
--- a/cpu/mpc8260/start.S
+++ b/cpu/mpc8260/start.S
@@ -279,7 +279,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -298,7 +298,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
@@ -676,13 +676,13 @@ init_debug:
 	bdnz	1b
 
 	/* Load the Instruction Address Breakpoint Register (IABR).	*/
-	/* 								*/
+	/*								*/
 	/* The address to load is stored in the first word of dual port	*/
 	/* ram and should be preserved while the power is on, so you	*/
 	/* can plug addresses into that location then reset the cpu and	*/
 	/* this code will load that address into the IABR after the	*/
 	/* reset.							*/
-	/* 								*/
+	/*								*/
 	/* When the program counter matches the contents of the IABR,	*/
 	/* an exception is generated (before the instruction at that	*/
 	/* location completes). The vector for this exception is 0x1300 */
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index e078f27..841fe82 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -415,7 +415,7 @@ static const struct {
 		"clock-frequency",
 		fdt_set_busfreq
 	},
-#ifdef CONFIG_MPC83XX_TSEC1
+#ifdef CONFIG_TSEC1
 	{	"/" OF_SOC "/ethernet@24000,
 		"mac-address",
 		fdt_set_eth0
@@ -425,7 +425,7 @@ static const struct {
 		fdt_set_eth0
 	},
 #endif
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
 	{	"/" OF_SOC "/ethernet@25000,
 		"mac-address",
 		fdt_set_eth1
@@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	if (p != NULL)
 		*p = cpu_to_be32(clock);
 
-#ifdef CONFIG_MPC83XX_TSEC1
+#ifdef CONFIG_TSEC1
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enetaddr, 6);
@@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		memcpy(p, bd->bi_enetaddr, 6);
 #endif
 
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enet1addr, 6);
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 6ee9ec9..496c8a5 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -263,7 +263,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -282,7 +282,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 7735a52..1d791c9 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	if (p != NULL)
 		*p = cpu_to_be32(clock);
 
-#if defined(CONFIG_MPC85XX_TSEC1)
+#if defined(CONFIG_TSEC1)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 	if (p)
 		memcpy(p, bd->bi_enetaddr, 6);
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 20c7ebc..77c155c 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -457,7 +457,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x0600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -475,7 +475,7 @@ Alignment:
 /* Program check exception */
 	. = 0x0700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index a33acfe..9456471 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	if (p != NULL)
 		*p = cpu_to_be32(clock);
 
-#if defined(CONFIG_MPC86XX_TSEC1)
+#if defined(CONFIG_TSEC1)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enetaddr, 6);
@@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		memcpy(p, bd->bi_enetaddr, 6);
 #endif
 
-#if defined(CONFIG_MPC86XX_TSEC2)
+#if defined(CONFIG_TSEC2)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enet1addr, 6);
@@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		memcpy(p, bd->bi_enet1addr, 6);
 #endif
 
-#if defined(CONFIG_MPC86XX_TSEC3)
+#if defined(CONFIG_TSEC3)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enet2addr, 6);
@@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		memcpy(p, bd->bi_enet2addr, 6);
 #endif
 
-#if defined(CONFIG_MPC86XX_TSEC4)
+#if defined(CONFIG_TSEC4)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enet3addr, 6);
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 67c56db..412745b 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -116,7 +116,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -134,7 +134,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S
index 33a3f6c..eca4b50 100644
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -224,7 +224,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -242,7 +242,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 8bf03e1..2837929 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -77,11 +77,21 @@
 #include <asm/processor.h>
 #include <pci.h>
 
+#ifdef CONFIG_PCI
+
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
+/*
+ * Board-specific pci initialization
+ * Platform code can reimplement pci_pre_init() if needed
+ */
+int __pci_pre_init(struct pci_controller *hose)
+{
+	return 1;
+}
+int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
 
 #if defined(CONFIG_PMC405)
 ushort pmc405_pci_subsys_deviceid(void);
@@ -191,6 +201,13 @@ void pci_405gp_init(struct pci_controller *hose)
 	if (hose->pci_fb)
 		pciauto_region_init(hose->pci_fb);
 
+	/* Let board change/modify hose & do initial checks */
+	if (pci_pre_init (hose) == 0) {
+		printf("PCI: Board-specific initialization failed.\n");
+		printf("PCI: Configuration aborted.\n");
+		return;
+	}
+
 	pci_register_hose(hose);
 
 	/*--------------------------------------------------------------------------+
@@ -416,14 +433,12 @@ void pci_init_board(void)
 
 #endif
 
-#endif /* CONFIG_PCI */
-
 #endif /* CONFIG_405GP */
 
 /*-----------------------------------------------------------------------------+
  * CONFIG_440
  *-----------------------------------------------------------------------------*/
-#if defined(CONFIG_440) && defined(CONFIG_PCI)
+#if defined(CONFIG_440)
 
 static struct pci_controller ppc440_hose = {0};
 
@@ -496,14 +511,12 @@ void pci_440_init (struct pci_controller *hose)
 
 	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
 
-#if defined(CFG_PCI_PRE_INIT)
 	/* Let board change/modify hose & do initial checks */
 	if (pci_pre_init (hose) == 0) {
 		printf("PCI: Board-specific initialization failed.\n");
 		printf("PCI: Configuration aborted.\n");
 		return;
 	}
-#endif
 
 	pci_register_hose( hose );
 
@@ -575,4 +588,5 @@ void pci_init_board(void)
 #endif
 }
 
-#endif /* CONFIG_440 & CONFIG_PCI */
+#endif /* CONFIG_440 */
+#endif /* CONFIG_PCI */
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index c500d3f..e24cd81 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -262,7 +262,7 @@ typedef struct bank_param BANKPARMS;
 #ifdef CFG_SIMULATE_SPD_EEPROM
 extern unsigned char cfg_simulate_spd_eeprom[128];
 #endif
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 
 static unsigned char spd_read(uchar chip, uint addr);
 static void get_spd_info(unsigned long *dimm_populated,
@@ -373,7 +373,7 @@ long int spd_sdram(void) {
 
 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
 	/* and program tlb entries for this size (dynamic) */
-	program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
 #endif
 
 	/*
@@ -1340,14 +1340,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 			 */
 			cr |= SDRAM_BXCR_SDBE;
 
- 			for (i = 0; i < num_banks; i++) {
+			for (i = 0; i < num_banks; i++) {
 				bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
 					(4 << 20) * bank_size_id;
 				bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
 				debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
 				      dimm_num, i, ctrl_bank_num[dimm_num]+i,
 				      bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
- 			}
+			}
 		}
 	}
 
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 48b9ee2..b5c0f53 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -58,8 +58,8 @@
 #define SDRAM_DDR2	2
 #define SDRAM_NONE	0
 
-#define MAXDIMMS 	2
-#define MAXRANKS 	4
+#define MAXDIMMS	2
+#define MAXRANKS	4
 #define MAXBXCF		4
 #define MAX_SPD_BYTES	256   /* Max number of bytes on the DIMM's SPD EEPROM */
 
@@ -144,7 +144,7 @@ typedef enum ddr_cas_id {
  * Prototypes
  *-----------------------------------------------------------------------------*/
 static unsigned long sdram_memsize(void);
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 static void get_spd_info(unsigned long *dimm_populated,
 			 unsigned char *iic0_dimm_addr,
 			 unsigned long num_dimm_banks);
@@ -528,7 +528,7 @@ long int initdram(int board_type)
 	dram_size = sdram_memsize();
 
 	/* and program tlb entries for this size (dynamic) */
-	program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 
 	/*------------------------------------------------------------------
 	 * DQS calibration.
diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk
index 119e061..4fd5108 100644
--- a/cpu/ppc4xx/config.mk
+++ b/cpu/ppc4xx/config.mk
@@ -22,5 +22,13 @@
 #
 
 PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
+PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float
 
-PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
+
+ifneq (,$(findstring CONFIG_440,$(is440)))
+PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
+else
+PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
+endif
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 66e8637..351da36 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -153,7 +153,7 @@ cpu_init_f (void)
 	 */
 	asm volatile("	bl	0f"		::: "lr");
 	asm volatile("0:	mflr	3"		::: "r3");
-	asm volatile("	addi 	4, 0, 14"	::: "r4");
+	asm volatile("	addi	4, 0, 14"	::: "r4");
 	asm volatile("	mtctr	4"		::: "ctr");
 	asm volatile("1:	icbt	0, 3");
 	asm volatile("	addi	3, 3, 32"	::: "r3");
@@ -211,6 +211,8 @@ cpu_init_f (void)
 	val = mfspr(tcr);
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
+#elif defined(CONFIG_440EPX)
+	val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
 #else
 	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 #endif
diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index dd84e58..5235203 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -103,6 +103,18 @@ void gpio_write_bit(int pin, int val)
 		out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
 }
 
+int gpio_read_out_bit(int pin)
+{
+	u32 offs = 0;
+
+	if (pin >= GPIO_MAX) {
+		offs = 0x100;
+		pin -= GPIO_MAX;
+	}
+
+	return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
+}
+
 #if defined(CFG_440_GPIO_TABLE)
 void gpio_set_chip_configuration(void)
 {
@@ -157,12 +169,38 @@ void gpio_set_chip_configuration(void)
 				switch (gpio_tab[gpio_core][i].alt_nb) {
 				case GPIO_SEL:
 					if (gpio_core == GPIO0) {
-						reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
+						/*
+						 * Setup output value
+						 * 1 -> high level
+						 * 0 -> low level
+						 * else -> don't touch
+						 */
+						reg = in32(GPIO0_OR);
+						if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
+							reg |= (0x80000000 >> (i));
+						else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
+							reg &= ~(0x80000000 >> (i));
+						out32(GPIO0_OR, reg);
+
+						reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
 						out32(GPIO0_TCR, reg);
 					}
 
 					if (gpio_core == GPIO1) {
-						reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
+						/*
+						 * Setup output value
+						 * 1 -> high level
+						 * 0 -> low level
+						 * else -> don't touch
+						 */
+						reg = in32(GPIO0_OR);
+						if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
+							reg |= (0x80000000 >> (i));
+						else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
+							reg &= ~(0x80000000 >> (i));
+						out32(GPIO0_OR, reg);
+
+						reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
 						out32(GPIO1_TCR, reg);
 					}
 
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 78d0042..6086b6c 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -22,26 +22,27 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-/*------------------------------------------------------------------------------+ */
-/* */
-/*	 This source code has been made available to you by IBM on an AS-IS */
-/*	 basis.	 Anyone receiving this source is licensed under IBM */
-/*	 copyrights to use it in any way he or she deems fit, including */
-/*	 copying it, modifying it, compiling it, and redistributing it either */
-/*	 with or without modifications.	 No license under IBM patents or */
-/*	 patent applications is to be implied by the copyright license. */
-/* */
-/*	 Any user of this software should understand that IBM cannot provide */
-/*	 technical support for this software and will not be responsible for */
-/*	 any consequences resulting from the use of this software. */
-/* */
-/*	 Any person who transfers this source code or any derivative work */
-/*	 must include the IBM copyright notice, this paragraph, and the */
-/*	 preceding two paragraphs in the transferred software. */
-/* */
-/*	 COPYRIGHT   I B M   CORPORATION 1995 */
-/*	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
+/*------------------------------------------------------------------------------+
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-------------------------------------------------------------------------------
+ */
 
 /*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
  *
@@ -59,7 +60,6 @@
  *  address and (s)dram will be positioned at address 0
  */
 #include <config.h>
-#include <mpc8xx.h>
 #include <ppc4xx.h>
 #include <version.h>
 
@@ -110,11 +110,11 @@
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
-#define function_prolog(func_name)      .text; \
+#define function_prolog(func_name)	.text; \
 					.align 2; \
 					.globl func_name; \
 					func_name:
-#define function_epilog(func_name)      .type func_name,@function; \
+#define function_epilog(func_name)	.type func_name,@function; \
 					.size func_name,.-func_name
 
 /* We don't want the  MMU yet.
@@ -294,11 +294,13 @@ skip_debug_init:
 	mtspr	ivor7,r1	/* Floating point unavailable */
 	li	r1,0x0c00
 	mtspr	ivor8,r1	/* System call */
-	li	r1,0x1000
-	mtspr	ivor10,r1	/* Decrementer (PIT for 440) */
-	li	r1,0x1400
-	mtspr	ivor13,r1	/* Data TLB error */
+	li	r1,0x0a00
+	mtspr	ivor9,r1	/* Auxiliary Processor unavailable */
+	li	r1,0x0900
+	mtspr	ivor10,r1	/* Decrementer */
 	li	r1,0x1300
+	mtspr	ivor13,r1	/* Data TLB error */
+	li	r1,0x1400
 	mtspr	ivor14,r1	/* Instr TLB error */
 	li	r1,0x2000
 	mtspr	ivor15,r1	/* Debug */
@@ -503,11 +505,81 @@ version_string:
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 
-/*
- * Maybe this should be moved somewhere else because the current
- * location (0x100) is where the CriticalInput Execption should be.
- */
 	. = EXC_OFF_SYS_RESET
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Critical input. */
+	CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
+
+#ifdef CONFIG_440
+/* Machine check */
+	MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+#else
+	CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+#endif /* CONFIG_440 */
+
+/* Data Storage exception. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_Alignment:
+	.long	AlignmentException - _start + _START_OFFSET
+	.long	int_return - _start + _START_OFFSET
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_ProgramCheck:
+	.long	ProgramCheckException - _start + _START_OFFSET
+	.long	int_return - _start + _START_OFFSET
+
+#ifdef CONFIG_440
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+	STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
+	STD_EXCEPTION(0xa00, APU, UnknownException)
+#endif
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+
+#ifdef CONFIG_440
+	STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
+	STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
+#else
+	STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
+	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+#endif
+	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+	. = _START_OFFSET
 #endif
 	.globl	_start
 _start:
@@ -817,21 +889,21 @@ _start:
 	 */
 	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CFG_OCM_DATA_ADDR@l
-	ori	r3,r3,0x8270	/* 32K Offset, 16K for Bank 1, R/W/Enable */
+	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
 	mtdcr	ocmplb3cr1,r3		/* Set PLB Access */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
 	mtdcr	ocmplb3cr2,r3		/* Set PLB Access */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CFG_OCM_DATA_ADDR@l
-	ori	r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
-	mtdcr	ocmdscr1, r3            /* Set Data Side */
-	mtdcr	ocmiscr1, r3            /* Set Instruction Side */
+	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
+	mtdcr	ocmdscr1, r3		/* Set Data Side */
+	mtdcr	ocmiscr1, r3		/* Set Instruction Side */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
-	mtdcr	ocmdscr2, r3            /* Set Data Side */
-	mtdcr	ocmiscr2, r3            /* Set Instruction Side */
-	addis	r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
+	mtdcr	ocmdscr2, r3		/* Set Data Side */
+	mtdcr	ocmiscr2, r3		/* Set Instruction Side */
+	addis	r3,0,0x0800		/* OCM Data Parity Disable - 1 Wait State */
 	mtdcr	ocmdsisdpc,r3
 
 	isync
@@ -850,7 +922,7 @@ _start:
 	mtdcr	ocmdscntl, r4		/* set data-side IRAM config */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CFG_OCM_DATA_ADDR@l
 	mtdcr	ocmdsarc, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
@@ -1017,107 +1089,6 @@ start_ram:
 
 
 #ifndef CONFIG_NAND_SPL
-/*****************************************************************************/
-	.globl	_start_of_vectors
-_start_of_vectors:
-
-#if 0
-/*TODO Fixup _start above so we can do this*/
-/* Critical input. */
-	CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
-#endif
-
-/* Machine check */
-	CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. */
-	STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. */
-	STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
-	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
-	. = 0x600
-Alignment:
-	EXCEPTION_PROLOG
-	mfspr	r4,DAR
-	stw	r4,_DAR(r21)
-	mfspr	r5,DSISR
-	stw	r5,_DSISR(r21)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
-
-/* Program check exception */
-	. = 0x700
-ProgramCheck:
-	EXCEPTION_PROLOG
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
-
-	/* No FPU on MPC8xx.  This exception is not supposed to happen.
-	*/
-	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
-
-	/* I guess we could implement decrementer, and may have
-	 * to someday for timekeeping.
-	 */
-	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
-	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
-	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
-	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
-	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
-
-	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
-	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
-
-	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
-	 * for all unimplemented and illegal instructions.
-	 */
-	STD_EXCEPTION(0x1000, PIT, PITException)
-
-	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
-	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
-
-	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
-	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
-	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
-	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
-	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
-	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
-	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
-
-	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
-	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
-	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
-	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
-
-	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
-
-	.globl	_end_of_vectors
-_end_of_vectors:
-
-
-	. = 0x2100
-
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
@@ -1133,28 +1104,12 @@ transfer_to_handler:
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
-#if 0
-	andi.	r23,r23,MSR_PR
-	mfspr	r23,SPRG3		/* if from user, fix up tss.regs */
-	beq	2f
-	addi	r24,r1,STACK_FRAME_OVERHEAD
-	stw	r24,PT_REGS(r23)
-2:	addi	r2,r23,-TSS		/* set r2 to current */
-	tovirt(r2,r2,r23)
-#endif
 	mflr	r23
 	andi.	r24,r23,0x3f00		/* get vector offset */
 	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
-#if 0
-	addi	r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
-	cmplw	0,r1,r2
-	cmplw	1,r1,r24
-	crand	1,1,4
-	bgt	stack_ovf		/* if r2 < r1 < r2+TASK_STRUCT_SIZE */
-#endif
 	lwz	r24,0(r23)		/* virtual address of handler */
 	lwz	r23,4(r23)		/* where to go when done */
 	mtspr	SRR0,r24
@@ -1215,16 +1170,72 @@ crit_return:
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
-	mtspr	990,r2		/* SRR2 */
-	mtspr	991,r0		/* SRR3 */
+	mtspr	csrr0,r2
+	mtspr	csrr1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfci
 
-/* Cache functions.
-*/
+#ifdef CONFIG_440
+mck_return:
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	mcsrr0,r2
+	mtspr	mcsrr1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfmci
+#endif /* CONFIG_440 */
+
+
+/*
+ * Cache functions.
+ *
+ * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
+ * although for some cache-ralated calls stubs have to be provided to satisfy
+ * symbols resolution.
+ * Icache-related functions are used in POST framework.
+ *
+ */
+#ifdef CONFIG_440
+       .globl  dcache_disable
+       .globl  icache_disable	
+       .globl  icache_enable
+dcache_disable:
+icache_disable:
+icache_enable:
+	blr
+
+	.globl	dcache_status
+	.globl	icache_status
+dcache_status:
+icache_status:
+	mr	r3,  0
+	blr
+#else
 flush_dcache:
 	addis	r9,r0,0x0002		/* set mask for EE and CE msr bits */
 	ori	r9,r9,0x8000
@@ -1303,24 +1314,13 @@ dcache_status:
 	mfdccr	r3
 	srwi	r3, r3, 31	/* >>31 => select bit 0 */
 	blr
+#endif
 
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
 	blr
 
-#if !defined(CONFIG_440)
-	.globl wr_pit
-wr_pit:
-	mtspr	pit, r3
-	blr
-#endif
-
-	.globl wr_tcr
-wr_tcr:
-	mtspr	tcr, r3
-	blr
-
 /*------------------------------------------------------------------------------- */
 /* Function:	 out16 */
 /* Description:	 Output 16 bits */
@@ -1518,7 +1518,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 
-	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	addi	r0, r10, in_ram - _start + _START_OFFSET
 	mtlr	r0
 	blr				/* NEVER RETURNS! */
 
@@ -1588,7 +1588,7 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
-	lwz	r7, GOT(_start)
+	lwz	r7, GOT(_start_of_vectors)
 	lwz	r8, GOT(_end_of_vectors)
 
 	li	r9, 0x100		/* reset vector always at 0x100 */
@@ -1608,35 +1608,48 @@ trap_init:
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
-	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
-	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+	li	r7, .L_MachineCheck - _start + _START_OFFSET
+	li	r8, Alignment - _start + _START_OFFSET
 2:
 	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector	*/
+	addi	r7, r7, 0x100		/* next exception vector */
 	cmplw	0, r7, r8
 	blt	2b
 
-	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	li	r7, .L_Alignment - _start + _START_OFFSET
 	bl	trap_reloc
 
-	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	li	r7, .L_ProgramCheck - _start + _START_OFFSET
 	bl	trap_reloc
 
-	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
-	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
+#ifdef CONFIG_440
+	li	r7, .L_FPUnavailable - _start + _START_OFFSET
 	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector	*/
-	cmplw	0, r7, r8
-	blt	3b
 
-	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
-	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
+	li	r7, .L_Decrementer - _start + _START_OFFSET
+	bl	trap_reloc
+
+	li	r7, .L_APU - _start + _START_OFFSET
+	bl	trap_reloc
+
+	li	r7, .L_InstructionTLBError - _start + _START_OFFSET
+	bl	trap_reloc
+
+	li	r7, .L_DataTLBError - _start + _START_OFFSET
+	bl	trap_reloc
+#else /* CONFIG_440 */
+	li	r7, .L_PIT - _start + _START_OFFSET
+	bl	trap_reloc
+
+	li	r7, .L_InstructionTLBMiss - _start + _START_OFFSET
+	bl	trap_reloc
+
+	li	r7, .L_DataTLBMiss - _start + _START_OFFSET
+	bl	trap_reloc
+#endif /* CONFIG_440 */
+
+	li	r7, .L_DebugBreakpoint - _start + _START_OFFSET
 	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector	*/
-	cmplw	0, r7, r8
-	blt	4b
 
 #if !defined(CONFIG_440)
 	addi	r7,r0,0x1000		/* set ME bit (Machine Exceptions) */
@@ -1679,13 +1692,13 @@ trap_reloc:
 +----------------------------------------------------------------------------*/
 	function_prolog(dcbz_area)
 	rlwinm. r5,r4,0,27,31
-	rlwinm  r5,r4,27,5,31
-	beq     ..d_ra2
-	addi    r5,r5,0x0001
-..d_ra2:mtctr   r5
-..d_ag2:dcbz    r0,r3
-	addi    r3,r3,32
-	bdnz    ..d_ag2
+	rlwinm	r5,r4,27,5,31
+	beq	..d_ra2
+	addi	r5,r5,0x0001
+..d_ra2:mtctr	r5
+..d_ag2:dcbz	r0,r3
+	addi	r3,r3,32
+	bdnz	..d_ag2
 	sync
 	blr
 	function_epilog(dcbz_area)
@@ -1694,26 +1707,26 @@ trap_reloc:
 | dflush.  Assume 32K at vector address is cachable.
 +----------------------------------------------------------------------------*/
 	function_prolog(dflush)
-	mfmsr   r9
-	rlwinm  r8,r9,0,15,13
-	rlwinm  r8,r8,0,17,15
-	mtmsr   r8
-	addi    r3,r0,0x0000
-	mtspr   dvlim,r3
-	mfspr   r3,ivpr
-	addi    r4,r0,1024
-	mtctr   r4
+	mfmsr	r9
+	rlwinm	r8,r9,0,15,13
+	rlwinm	r8,r8,0,17,15
+	mtmsr	r8
+	addi	r3,r0,0x0000
+	mtspr	dvlim,r3
+	mfspr	r3,ivpr
+	addi	r4,r0,1024
+	mtctr	r4
 ..dflush_loop:
-	lwz     r6,0x0(r3)
-	addi    r3,r3,32
-	bdnz    ..dflush_loop
-	addi    r3,r3,-32
-	mtctr   r4
-..ag:   dcbf    r0,r3
-	addi    r3,r3,-32
-	bdnz    ..ag
+	lwz	r6,0x0(r3)
+	addi	r3,r3,32
+	bdnz	..dflush_loop
+	addi	r3,r3,-32
+	mtctr	r4
+..ag:	dcbf	r0,r3
+	addi	r3,r3,-32
+	bdnz	..ag
 	sync
-	mtmsr   r9
+	mtmsr	r9
 	blr
 	function_epilog(dflush)
 #endif /* CONFIG_440 */
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index 50344a4..049a785 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -36,7 +36,8 @@ typedef struct region {
 	unsigned long tlb_word2_i_value;
 } region_t;
 
-static int add_tlb_entry(unsigned long base_addr,
+static int add_tlb_entry(unsigned long phys_addr,
+			 unsigned long virt_addr,
 			 unsigned long tlb_word0_size_value,
 			 unsigned long tlb_word2_i_value)
 {
@@ -55,9 +56,9 @@ static int add_tlb_entry(unsigned long base_addr,
 		return -1;
 
 	/* Second, create the TLB entry */
-	tlb_word0_value = TLB_WORD0_EPN_ENCODE(base_addr) | TLB_WORD0_V_ENABLE |
+	tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
 		TLB_WORD0_TS_0 | tlb_word0_size_value;
-	tlb_word1_value = TLB_WORD1_RPN_ENCODE(base_addr) | TLB_WORD1_ERPN_ENCODE(0);
+	tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
 	tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
 		TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
 		TLB_WORD2_W_DISABLE | tlb_word2_i_value |
@@ -81,7 +82,9 @@ static int add_tlb_entry(unsigned long base_addr,
 	return 0;
 }
 
-static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
+static void program_tlb_addr(unsigned long phys_addr,
+			     unsigned long virt_addr,
+			     unsigned long mem_size,
 			     unsigned long tlb_word2_i_value)
 {
 	int rc;
@@ -91,70 +94,86 @@ static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
 	while (mem_size != 0) {
 		rc = 0;
 		/* Add the TLB entries in to map the region. */
-		if (((base_addr & TLB_256MB_ALIGN_MASK) == base_addr) &&
+		if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
 		    (mem_size >= TLB_256MB_SIZE)) {
 			/* Add a 256MB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
 				mem_size -= TLB_256MB_SIZE;
-				base_addr += TLB_256MB_SIZE;
+				phys_addr += TLB_256MB_SIZE;
+				virt_addr += TLB_256MB_SIZE;
 			}
-		} else if (((base_addr & TLB_16MB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_16MB_SIZE)) {
 			/* Add a 16MB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
 				mem_size -= TLB_16MB_SIZE;
-				base_addr += TLB_16MB_SIZE;
+				phys_addr += TLB_16MB_SIZE;
+				virt_addr += TLB_16MB_SIZE;
 			}
-		} else if (((base_addr & TLB_1MB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_1MB_SIZE)) {
 			/* Add a 1MB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
 				mem_size -= TLB_1MB_SIZE;
-				base_addr += TLB_1MB_SIZE;
+				phys_addr += TLB_1MB_SIZE;
+				virt_addr += TLB_1MB_SIZE;
 			}
-		} else if (((base_addr & TLB_256KB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_256KB_SIZE)) {
 			/* Add a 256KB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
 				mem_size -= TLB_256KB_SIZE;
-				base_addr += TLB_256KB_SIZE;
+				phys_addr += TLB_256KB_SIZE;
+				virt_addr += TLB_256KB_SIZE;
 			}
-		} else if (((base_addr & TLB_64KB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_64KB_SIZE)) {
 			/* Add a 64KB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
 				mem_size -= TLB_64KB_SIZE;
-				base_addr += TLB_64KB_SIZE;
+				phys_addr += TLB_64KB_SIZE;
+				virt_addr += TLB_64KB_SIZE;
 			}
-		} else if (((base_addr & TLB_16KB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_16KB_SIZE)) {
 			/* Add a 16KB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
 				mem_size -= TLB_16KB_SIZE;
-				base_addr += TLB_16KB_SIZE;
+				phys_addr += TLB_16KB_SIZE;
+				virt_addr += TLB_16KB_SIZE;
 			}
-		} else if (((base_addr & TLB_4KB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_4KB_SIZE)) {
 			/* Add a 4KB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
 				mem_size -= TLB_4KB_SIZE;
-				base_addr += TLB_4KB_SIZE;
+				phys_addr += TLB_4KB_SIZE;
+				virt_addr += TLB_4KB_SIZE;
 			}
-		} else if (((base_addr & TLB_1KB_ALIGN_MASK) == base_addr) &&
+		} else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
 			   (mem_size >= TLB_1KB_SIZE)) {
 			/* Add a 1KB TLB entry */
-			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
+			if ((rc = add_tlb_entry(phys_addr, virt_addr,
+						TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
 				mem_size -= TLB_1KB_SIZE;
-				base_addr += TLB_1KB_SIZE;
+				phys_addr += TLB_1KB_SIZE;
+				virt_addr += TLB_1KB_SIZE;
 			}
 		} else {
 			printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
-				base_addr);
+				phys_addr);
 		}
 
 		if (rc != 0)
 			printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
-				base_addr);
+				phys_addr);
 	}
 
 	return;
@@ -166,16 +185,16 @@ static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
  * Common usage for boards with SDRAM DIMM modules to dynamically
  * configure the TLB's for the SDRAM
  */
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value)
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
 {
 	region_t region_array;
 
-	region_array.base = start;
+	region_array.base = phys_addr;
 	region_array.size = size;
 	region_array.tlb_word2_i_value = tlb_word2_i_value;	/* en-/disable cache */
 
 	/* Call the routine to add in the tlb entries for the memory regions */
-	program_tlb_addr(region_array.base, region_array.size,
+	program_tlb_addr(region_array.base, virt_addr, region_array.size,
 			 region_array.tlb_word2_i_value);
 
 	return;
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 6aecca2..eb9420e 100644..100755
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -36,6 +36,8 @@
 #include <command.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
 #endif
@@ -45,8 +47,7 @@ extern unsigned long search_exception_table(unsigned long);
 
 /* THIS NEEDS CHANGING to use the board info structure.
  */
-#define END_OF_MEM	0x00400000
-
+#define END_OF_MEM	(gd->bd->bi_memstart + gd->bd->bi_memsize)
 
 static __inline__ void set_tsr(unsigned long val)
 {
@@ -110,7 +111,7 @@ void show_regs(struct pt_regs * regs)
 {
 	int i;
 
-	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
 	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
 	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
 	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
@@ -120,14 +121,12 @@ void show_regs(struct pt_regs * regs)
 
 	printf("\n");
 	for (i = 0;  i < 32;  i++) {
-		if ((i % 8) == 0)
-		{
+		if ((i % 8) == 0) {
 			printf("GPR%02d: ", i);
 		}
 
 		printf("%08lX ", regs->gpr[i]);
-		if ((i % 8) == 7)
-		{
+		if ((i % 8) == 7) {
 			printf("\n");
 		}
 	}
@@ -139,13 +138,16 @@ _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+	panic("Exception");
 }
 
 void
 MachineCheckException(struct pt_regs *regs)
 {
-	unsigned long fixup;
+	unsigned long fixup, val;
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	u32 value2;
+#endif
 
 	/* Probing PCI using config cycles cause this exception
 	 * when a device is not present.  Catch it and return to
@@ -161,26 +163,132 @@ MachineCheckException(struct pt_regs *regs)
 		return;
 #endif
 
-	printf("Machine check in kernel mode.\n");
+	printf("Machine Check Exception.\n");
 	printf("Caused by (from msr): ");
-	printf("regs %p ",regs);
-	switch( regs->msr & 0x000F0000) {
-	case (0x80000000>>12):
-		printf("Machine check signal - probably due to mm fault\n"
-		       "with mmu off\n");
+	printf("regs %p ", regs);
+
+	val = get_esr();
+
+#if !defined(CONFIG_440)
+	if (val& ESR_IMCP) {
+		printf("Instruction");
+		mtspr(ESR, val & ~ESR_IMCP);
+	} else {
+		printf("Data");
+	}
+	printf(" machine check.\n");
+
+#elif defined(CONFIG_440)
+	if (val& ESR_IMCP){
+		printf("Instruction Synchronous Machine Check exception\n");
+		mtspr(SPRN_ESR, val & ~ESR_IMCP);
+	} else {
+		val = mfspr(MCSR);
+		if (val & MCSR_IB)
+			printf("Instruction Read PLB Error\n");
+		if (val & MCSR_DRB)
+			printf("Data Read PLB Error\n");
+		if (val & MCSR_DWB)
+			printf("Data Write PLB Error\n");
+		if (val & MCSR_TLBP)
+			printf("TLB Parity Error\n");
+		if (val & MCSR_ICP){
+			/*flush_instruction_cache(); */
+			printf("I-Cache Parity Error\n");
+		}
+		if (val & MCSR_DCSP)
+			printf("D-Cache Search Parity Error\n");
+		if (val & MCSR_DCFP)
+			printf("D-Cache Flush Parity Error\n");
+		if (val & MCSR_IMPE)
+			printf("Machine Check exception is imprecise\n");
+
+		/* Clear MCSR */
+		mtspr(SPRN_MCSR, val);
+	}
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	mfsdram(DDR0_00, val) ;
+	printf("DDR0: DDR0_00 %p\n", val);
+	val = (val >> 16) & 0xff;
+	if (val & 0x80)
+		printf("DDR0: At least one interrupt active\n");
+	if (val & 0x40)
+		printf("DDR0: DRAM initialization complete.\n");
+	if (val & 0x20)
+		printf("DDR0: Multiple uncorrectable ECC events.\n");
+	if (val & 0x10)
+		printf("DDR0: Single uncorrectable ECC event.\n");
+	if (val & 0x08)
+		printf("DDR0: Multiple correctable ECC events.\n");
+	if (val & 0x04)
+		printf("DDR0: Single correctable ECC event.\n");
+	if (val & 0x02)
+		printf("Multiple accesses outside the defined"
+		       " physical memory space detected\n");
+	if (val & 0x01)
+		printf("DDR0: Single access outside the defined"
+		       " physical memory space detected.\n");
+
+	mfsdram(DDR0_01, val);
+	val = (val >> 8) & 0x7;
+	switch (val ) {
+	case 0:
+		printf("DDR0: Write Out-of-Range command\n");
+		break;
+	case 1:
+		printf("DDR0: Read Out-of-Range command\n");
 		break;
-	case (0x80000000>>13):
-		printf("Transfer error ack signal\n");
+	case 2:
+		printf("DDR0: Masked write Out-of-Range command\n");
 		break;
-	case (0x80000000>>14):
-		printf("Data parity signal\n");
+	case 4:
+		printf("DDR0: Wrap write Out-of-Range command\n");
 		break;
-	case (0x80000000>>15):
-		printf("Address parity signal\n");
+	case 5:
+		printf("DDR0: Wrap read Out-of-Range command\n");
 		break;
 	default:
-		printf("Unknown values in msr\n");
+		mfsdram(DDR0_01, value2);
+		printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
 	}
+	mfsdram(DDR0_23, val);
+	if ( (val >> 16) & 0xff)
+		printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
+		       (val >> 16) & 0xff);
+	mfsdram(DDR0_23, val);
+	if ( (val >> 8) & 0xff)
+		printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
+		       (val >> 8) & 0xff);
+	mfsdram(DDR0_33, val);
+	if (val)
+		printf("DDR0: Address of command that caused an "
+		       "Out-of-Range interrupt %p\n", val);
+	mfsdram(DDR0_34, val);
+	if (val)
+		printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+	mfsdram(DDR0_35, val);
+	if (val)
+		printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+	mfsdram(DDR0_36, val);
+	if (val)
+		printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+	mfsdram(DDR0_37, val);
+	if (val)
+		printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+	mfsdram(DDR0_38, val);
+	if (val)
+		printf("DDR0: Address of correctable ECC event %p\n", val);
+	mfsdram(DDR0_39, val);
+	if (val)
+		printf("DDR0: Address of correctable ECC event %p\n", val);
+	mfsdram(DDR0_40, val);
+	if (val)
+		printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+	mfsdram(DDR0_41, val);
+	if (val)
+		printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+#endif /* CONFIG_440EPX */
+#endif /* CONFIG_440 */
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("machine check");
@@ -224,7 +332,7 @@ ProgramCheckException(struct pt_regs *regs)
 }
 
 void
-PITException(struct pt_regs *regs)
+DecrementerPITException(struct pt_regs *regs)
 {
 	/*
 	 * Reset PIT interrupt
@@ -272,17 +380,17 @@ addr_probe(uint *addr)
 
 	__asm__ __volatile__(			\
 		"1:	lwz %0,0(%1)\n"		\
-						"	eieio\n"		\
-						"	li %0,0\n"		\
-						"2:\n"				\
-						".section .fixup,\"ax\"\n"	\
-						"3:	li %0,-1\n"		\
-						"	b 2b\n"			\
-						".section __ex_table,\"a\"\n"	\
-						"	.align 2\n"		\
-						"	.long 1b,3b\n"		\
-						".text"				\
-						: "=r" (retval) : "r"(addr));
+		"	eieio\n"		\
+		"	li %0,0\n"		\
+		"2:\n"				\
+		".section .fixup,\"ax\"\n"	\
+		"3:	li %0,-1\n"		\
+		"	b 2b\n"			\
+		".section __ex_table,\"a\"\n"	\
+		"	.align 2\n"		\
+		"	.long 1b,3b\n"		\
+		".text"				\
+		: "=r" (retval) : "r"(addr));
 
 	return (retval);
 #endif
diff --git a/doc/README.ppc440 b/doc/README.ppc440
index 08f34f5..2e04aba 100644
--- a/doc/README.ppc440
+++ b/doc/README.ppc440
@@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O
 space begins at PCI I/O address 0 and the PCI memory space is
 256 MB starting at PCI address CFG_PCI_TARGBASE. After the
 pci_controller structure is initialized, the cpu-specific code will
-call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is
-defined. This routine is implemented by board-specific code & is where
-the board can over-ride/extend the default pci_controller structure
-settings and do other pre-initialization tasks. If pci_pre_init()
-returns a value of zero, PCI initialization is aborted; otherwise the
-controller structure is registered and initialization continues.
+call the routine pci_pre_init(). This routine is implemented by
+board-specific code & is where the board can over-ride/extend the
+default pci_controller structure settings and exspecially provide
+a routine to map the PCI interrupts and do other pre-initialization
+tasks. If pci_pre_init() returns a value of zero, PCI initialization
+is aborted; otherwise the controller structure is registered and
+initialization continues.
 
 The default 440GP PCI target configuration is minimal -- it assumes that
 the strapping registers are set as necessary. Since the strapping bits
diff --git a/drivers/Makefile b/drivers/Makefile
index c7fcc3f..48fd4ea 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libdrivers.a
 
-COBJS	= 3c589.o 5701rls.o ali512x.o atmel_usart.o \
+COBJS	= 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
 	  bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
 	  cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
 	  e1000.o eepro100.o enc28j60.o \
diff --git a/drivers/ata_piix.c b/drivers/ata_piix.c
new file mode 100644
index 0000000..42456d7
--- /dev/null
+++ b/drivers/ata_piix.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) Procsys. All rights reserved.
+ * Author: Mushtaq Khan <mushtaq_k@procsys.com>
+ *			<mushtaqk_921@yahoo.co.in>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * with the reference to ata_piix driver in kernel 2.4.32
+ */
+
+/*
+ * This file contains SATA controller and SATA drive initialization functions
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <command.h>
+#include <config.h>
+#include <asm/byteorder.h>
+#include <ide.h>
+#include <ata.h>
+
+#ifdef CFG_ATA_PIIX		/*ata_piix driver */
+
+#define DEBUG_SATA 0		/*For debug prints set DEBUG_SATA to 1 */
+
+#define DRV_DECL		/*For file specific declarations */
+#include <sata.h>
+#undef DRV_DECL
+
+/*Macros realted to PCI*/
+#define PCI_SATA_BUS	0x00
+#define PCI_SATA_DEV	0x1f
+#define PCI_SATA_FUNC	0x02
+
+#define PCI_SATA_BASE1 0x10
+#define PCI_SATA_BASE2 0x14
+#define PCI_SATA_BASE3 0x18
+#define PCI_SATA_BASE4 0x1c
+#define PCI_SATA_BASE5 0x20
+#define PCI_PMR         0x90
+#define PCI_PI          0x09
+#define PCI_PCS         0x92
+#define PCI_DMA_CTL     0x48
+
+#define PORT_PRESENT (1<<0)
+#define PORT_ENABLED (1<<4)
+
+u32 bdf;
+u32 iobase1 = 0;		/*Primary cmd block */
+u32 iobase2 = 0;		/*Primary ctl block */
+u32 iobase3 = 0;		/*Sec cmd block */
+u32 iobase4 = 0;		/*sec ctl block */
+u32 iobase5 = 0;		/*BMDMA*/
+int
+pci_sata_init (void)
+{
+	u32 bus = PCI_SATA_BUS;
+	u32 dev = PCI_SATA_DEV;
+	u32 fun = PCI_SATA_FUNC;
+	u16 cmd = 0;
+	u8 lat = 0, pcibios_max_latency = 0xff;
+	u8 pmr;			/*Port mapping reg */
+	u8 pi;			/*Prgming Interface reg */
+
+	bdf = PCI_BDF (bus, dev, fun);
+	pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
+	pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
+	pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
+	pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
+	pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
+
+	if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
+	    (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
+	    (iobase5 == 0xFFFFFFFF)) {
+		printf ("error no base addr for SATA controller\n");
+		return 1;
+	 /*ERROR*/}
+
+	iobase1 &= 0xFFFFFFFE;
+	iobase2 &= 0xFFFFFFFE;
+	iobase3 &= 0xFFFFFFFE;
+	iobase4 &= 0xFFFFFFFE;
+	iobase5 &= 0xFFFFFFFE;
+
+	/*check for mode */
+	pci_read_config_byte (bdf, PCI_PMR, &pmr);
+	if (pmr > 1) {
+		printf ("combined mode not supported\n");
+		return 1;
+	}
+
+	pci_read_config_byte (bdf, PCI_PI, &pi);
+	if ((pi & 0x05) != 0x05) {
+		printf ("Sata is in Legacy mode\n");
+		return 1;
+	} else {
+		printf ("sata is in Native mode\n");
+	}
+
+	/*MASTER CFG AND IO CFG */
+	pci_read_config_word (bdf, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+	pci_write_config_word (bdf, PCI_COMMAND, cmd);
+	pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
+
+	if (lat < 16)
+		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
+	else if (lat > pcibios_max_latency)
+		lat = pcibios_max_latency;
+	pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
+
+	return 0;
+}
+
+int
+sata_bus_probe (int port_no)
+{
+	int orig_mask, mask;
+	u16 pcs;
+
+	mask = (PORT_PRESENT << port_no);
+	pci_read_config_word (bdf, PCI_PCS, &pcs);
+	orig_mask = (int) pcs & 0xff;
+	if ((orig_mask & mask) != mask)
+		return 0;
+	else
+		return 1;
+}
+
+int
+init_sata (void)
+{
+	u8 i, rv = 0;
+
+	for (i = 0; i < CFG_SATA_MAXDEVICES; i++) {
+		sata_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		sata_dev_desc[i].if_type = IF_TYPE_IDE;
+		sata_dev_desc[i].dev = i;
+		sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		sata_dev_desc[i].blksz = 0;
+		sata_dev_desc[i].lba = 0;
+		sata_dev_desc[i].block_read = sata_read;
+	}
+
+	rv = pci_sata_init ();
+	if (rv == 1) {
+		printf ("pci initialization failed\n");
+		return 1;
+	}
+
+	port[0].port_no = 0;
+	port[0].ioaddr.cmd_addr = iobase1;
+	port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
+	    iobase2 | ATA_PCI_CTL_OFS;
+	port[0].ioaddr.bmdma_addr = iobase5;
+
+	port[1].port_no = 1;
+	port[1].ioaddr.cmd_addr = iobase3;
+	port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
+	    iobase4 | ATA_PCI_CTL_OFS;
+	port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
+
+	for (i = 0; i < CFG_SATA_MAXBUS; i++)
+		sata_port (&port[i].ioaddr);
+
+	for (i = 0; i < CFG_SATA_MAXBUS; i++) {
+		if (!(sata_bus_probe (i))) {
+			port[i].port_state = 0;
+			printf ("SATA#%d port is not present \n", i);
+		} else {
+			printf ("SATA#%d port is present\n", i);
+			if (sata_bus_softreset (i)) {
+				port[i].port_state = 0;
+			} else {
+				port[i].port_state = 1;
+			}
+		}
+	}
+
+	for (i = 0; i < CFG_SATA_MAXBUS; i++) {
+		u8 j, devno;
+
+		if (port[i].port_state == 0)
+			continue;
+		for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
+			sata_identify (i, j);
+			set_Feature_cmd (i, j);
+			devno = i * CFG_SATA_DEVS_PER_BUS + j;
+			if ((sata_dev_desc[devno].lba > 0) &&
+			    (sata_dev_desc[devno].blksz > 0)) {
+				dev_print (&sata_dev_desc[devno]);
+				/* initialize partition type */
+				init_part (&sata_dev_desc[devno]);
+				if (curr_dev < 0)
+					curr_dev =
+					    i * CFG_SATA_DEVS_PER_BUS + j;
+			}
+		}
+	}
+	return 0;
+}
+#endif
diff --git a/drivers/tsec.c b/drivers/tsec.c
index b418773..1298478 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -65,33 +65,31 @@ struct tsec_info_struct {
  *   FEC_PHYIDX
  */
 static struct tsec_info_struct tsec_info[] = {
-#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
-#if defined(CONFIG_MPC8544DS)
+#if defined(CONFIG_TSEC1)
+#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
 	{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
 #else
 	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
 #endif
-#elif defined(CONFIG_MPC86XX_TSEC1)
-	{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
-#else
 	{0, 0, 0},
 #endif
-#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
-	{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
-#elif defined(CONFIG_MPC86XX_TSEC2)
+#if defined(CONFIG_TSEC2)
+#if defined(CONFIG_MPC8641HPCN)
 	{TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
 #else
+	{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
+#endif
 	{0, 0, 0},
 #endif
 #ifdef CONFIG_MPC85XX_FEC
 	{FEC_PHY_ADDR, 0, FEC_PHYIDX},
 #else
-#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
+#if defined(CONFIG_TSEC3)
 	{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
 #else
 	{0, 0, 0},
 #endif
-#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
+#if defined(CONFIG_TSEC4)
 	{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
 #else
 	{0, 0, 0},
@@ -928,6 +926,33 @@ struct phy_info phy_info_BCM5461S = {
 	},
 };
 
+struct phy_info phy_info_BCM5464S = {
+	0x02060b1,	/* 5464 ID */
+	"Broadcom BCM5464S",
+	0, /* not clear to me what minor revisions we can shift away */
+	(struct phy_cmd[]) { /* config */
+		/* Reset and configure the PHY */
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+		{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* startup */
+		/* Status is read once to clear old link state */
+		{MIIM_STATUS, miim_read, NULL},
+		/* Auto-negotiate */
+		{MIIM_STATUS, miim_read, &mii_parse_sr},
+		/* Read the status */
+		{MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* shutdown */
+		{miim_end,}
+	},
+};
+
 struct phy_info phy_info_M88E1011S = {
 	0x01410c6,
 	"Marvell 88E1011S",
@@ -1292,6 +1317,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_cis8204,
 	&phy_info_cis8201,
 	&phy_info_BCM5461S,
+	&phy_info_BCM5464S,
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
 	&phy_info_M88E1145,
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
index ba73bae..4a03cec 100644
--- a/include/74xx_7xx.h
+++ b/include/74xx_7xx.h
@@ -34,6 +34,7 @@
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET        0x0100      /* default system reset offset */
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /*----------------------------------------------------------------
  * l2cr values
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index 114dc92..c9b6a36 100644
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
 typedef enum gpio_out	 { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
 
 typedef struct {
-	unsigned long add;	/* gpio core base address	*/
-	gpio_driver_t in_out;	/* Driver Setting		*/
-	gpio_select_t alt_nb;	/* Selected Alternate		*/
+	unsigned long	add;	/* gpio core base address	*/
+	gpio_driver_t	in_out;	/* Driver Setting		*/
+	gpio_select_t	alt_nb;	/* Selected Alternate		*/
+	gpio_out_t	out_val;/* Default Output Value		*/
 } gpio_param_s;
 #endif
 
 void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
 void gpio_write_bit(int pin, int val);
+int gpio_read_out_bit(int pin);
 void gpio_set_chip_configuration(void);
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 5efc3ee..9780fe1 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -35,18 +35,18 @@
 #define MSR_DWE         (1<<10)         /* Debug Wait Enable (4xx) */
 #define MSR_UBLE        (1<<10)         /* BTB lock enable (e500) */
 #define MSR_BE		(1<<9)		/* Branch Trace */
-#define MSR_DE		(1<<9) 		/* Debug Exception Enable */
+#define MSR_DE		(1<<9)		/* Debug Exception Enable */
 #define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
 #define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
-#define MSR_IR		(1<<5) 		/* Instruction Relocate */
+#define MSR_IR		(1<<5)		/* Instruction Relocate */
 #define MSR_IS          (1<<5)          /* Book E Instruction space */
-#define MSR_DR		(1<<4) 		/* Data Relocate */
+#define MSR_DR		(1<<4)		/* Data Relocate */
 #define MSR_DS          (1<<4)          /* Book E Data space */
 #define MSR_PE		(1<<3)		/* Protection Enable */
 #define MSR_PX		(1<<2)		/* Protection Exclusive Mode */
 #define MSR_PMM         (1<<2)          /* Performance monitor mark bit (e500) */
 #define MSR_RI		(1<<1)		/* Recoverable Exception */
-#define MSR_LE		(1<<0) 		/* Little Endian */
+#define MSR_LE		(1<<0)		/* Little Endian */
 
 #ifdef CONFIG_APUS_FAST_EXCEPT
 #define MSR_		MSR_ME|MSR_IP|MSR_RI
@@ -123,9 +123,9 @@
 #define   DBCR_EDM	0x80000000
 #define   DBCR_IDM	0x40000000
 #define   DBCR_RST(x)	(((x) & 0x3) << 28)
-#define     DBCR_RST_NONE       	0
-#define     DBCR_RST_CORE       	1
-#define     DBCR_RST_CHIP       	2
+#define     DBCR_RST_NONE		0
+#define     DBCR_RST_CORE		1
+#define     DBCR_RST_CHIP		2
 #define     DBCR_RST_SYSTEM		3
 #define   DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */
 #define   DBCR_BT	0x04000000	/* Branch Taken Debug Event */
@@ -266,7 +266,7 @@
 #define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
-#define SPRN_IMMR	0x27E  	/* Internal Memory Map Register */
+#define SPRN_IMMR	0x27E	/* Internal Memory Map Register */
 #define SPRN_LDSTCR	0x3F8   /* Load/Store Control Register */
 #define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
 #define SPRN_LR		0x008	/* Link Register */
@@ -308,7 +308,7 @@
 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
 #define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
-#define SPRN_SRR3 	0x3DF	/* Save/Restore Register 3 */
+#define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
 #ifdef CONFIG_BOOKE
 #define SPRN_SVR	0x3FF	/* System Version Register */
 #else
@@ -451,6 +451,17 @@
 #define SPRN_PID1       0x279   /* Process ID Register 1 */
 #define SPRN_PID2       0x27a   /* Process ID Register 2 */
 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
+#ifdef CONFIG_440
+#define MCSR_MCS	0x80000000	/* Machine Check Summary */
+#define MCSR_IB		0x40000000	/* Instruction PLB Error */
+#define MCSR_DRB	0x20000000	/* Data Read PLB Error */
+#define MCSR_DWB	0x10000000	/* Data Write PLB Error */
+#define MCSR_TLBP	0x08000000	/* TLB Parity Error */
+#define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
+#define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
+#define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
+#define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
+#endif
 #define ESR_ST          0x00800000      /* Store Operation */
 
 #if defined(CONFIG_MPC86xx)
@@ -484,17 +495,17 @@
 #define DBCR0	SPRN_DBCR0	/* Debug Control Register 0 */
 #define DBCR1	SPRN_DBCR1	/* Debug Control Register 1 */
 #define DBSR	SPRN_DBSR	/* Debug Status Register */
-#define DCMP	SPRN_DCMP      	/* Data TLB Compare Register */
-#define DEC	SPRN_DEC       	/* Decrement Register */
-#define DMISS	SPRN_DMISS     	/* Data TLB Miss Register */
+#define DCMP	SPRN_DCMP	/* Data TLB Compare Register */
+#define DEC	SPRN_DEC	/* Decrement Register */
+#define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
 #define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
-#define EAR	SPRN_EAR       	/* External Address Register */
+#define EAR	SPRN_EAR	/* External Address Register */
 #define ESR	SPRN_ESR	/* Exception Syndrome Register */
 #define HASH1	SPRN_HASH1	/* Primary Hash Address Register */
 #define HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
 #define HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
 #define HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
-#define IABR	SPRN_IABR      	/* Instruction Address Breakpoint Register */
+#define IABR	SPRN_IABR	/* Instruction Address Breakpoint Register */
 #define IAC1	SPRN_IAC1	/* Instruction Address Register 1 */
 #define IAC2	SPRN_IAC2	/* Instruction Address Register 2 */
 #define IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
@@ -511,13 +522,13 @@
 #define IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
 #define IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
 #define IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
-#define IBAT7L 	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
+#define IBAT7L	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
 #define IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Lower Register */
 #define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
 #define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
-#define IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
+#define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
 #define LDSTCR	SPRN_LDSTCR     /* Load/Store Control Register */
-#define L2CR	SPRN_L2CR    	/* PPC 750 L2 control register */
+#define L2CR	SPRN_L2CR	/* PPC 750 L2 control register */
 #define LR	SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
 #if defined(CONFIG_MPC86xx)
@@ -529,7 +540,7 @@
 #define SVR	SPRN_SVR	/* System-On-Chip Version Register */
 #define PVR	SPRN_PVR	/* Processor Version */
 #define RPA	SPRN_RPA	/* Required Physical Address Register */
-#define SDR1	SPRN_SDR1      	/* MMU hash base register */
+#define SDR1	SPRN_SDR1	/* MMU hash base register */
 #define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
 #define SPR1	SPRN_SPRG1
 #define SPR2	SPRN_SPRG2
@@ -544,6 +555,8 @@
 #define SPRG7   SPRN_SPRG7
 #define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
 #define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
+#define SRR2	SPRN_SRR2	/* Save and Restore Register 2 */
+#define SRR3	SPRN_SRR3	/* Save and Restore Register 3 */
 #define SVR	SPRN_SVR	/* System Version Register */
 #define TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
 #define TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
@@ -598,7 +611,7 @@
 #define IVOR35	SPRN_IVOR35
 #define MCSRR0	SPRN_MCSRR0
 #define MCSRR1	SPRN_MCSRR1
-#define L1CSR0 	SPRN_L1CSR0
+#define L1CSR0	SPRN_L1CSR0
 #define L1CSR1	SPRN_L1CSR1
 #define MCSR	SPRN_MCSR
 #define MMUCSR0	SPRN_MMUCSR0
@@ -607,7 +620,7 @@
 #define PID1	SPRN_PID1
 #define PID2	SPRN_PID2
 #define MAS0	SPRN_MAS0
-#define MAS1 	SPRN_MAS1
+#define MAS1	SPRN_MAS1
 #define MAS2	SPRN_MAS2
 #define MAS3	SPRN_MAS3
 #define MAS4	SPRN_MAS4
@@ -619,7 +632,7 @@
 
 #define DCRN_BEAR	0x090	/* Bus Error Address Register */
 #define DCRN_BESR	0x091	/* Bus Error Syndrome Register */
-#define   BESR_DSES    	0x80000000	/* Data-Side Error Status */
+#define   BESR_DSES	0x80000000	/* Data-Side Error Status */
 #define   BESR_DMES	0x40000000	/* DMA Error Status */
 #define   BESR_RWS	0x20000000	/* Read/Write Status */
 #define   BESR_ETMASK	0x1C000000	/* Error Type */
@@ -676,8 +689,8 @@
 #define   IOCR_E3LP	0x01000000
 #define   IOCR_E4TE	0x00800000
 #define   IOCR_E4LP	0x00400000
-#define   IOCR_EDT     	0x00080000
-#define   IOCR_SOR     	0x00040000
+#define   IOCR_EDT	0x00080000
+#define   IOCR_SOR	0x00040000
 #define   IOCR_EDO	0x00008000
 #define   IOCR_2XC	0x00004000
 #define   IOCR_ATC	0x00002000
@@ -802,7 +815,7 @@
 #define PVR_823		PVR_821
 #define PVR_850		PVR_821
 #define PVR_860		PVR_821
-#define PVR_7400       	0x000C0000
+#define PVR_7400	0x000C0000
 #define PVR_8240	0x00810100
 
 /*
diff --git a/include/ata.h b/include/ata.h
index 8584226..aa6e90d 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -83,6 +83,66 @@
 #define ATA_DEVICE(x)	((x & 1)<<4)
 #define ATA_LBA		0xE0
 
+enum {
+	ATA_MAX_DEVICES = 1,	/* per bus/port */
+	ATA_MAX_PRD = 256,	/* we could make these 256/256 */
+	ATA_SECT_SIZE = 256,	/*256 words per sector */
+
+	/* bits in ATA command block registers */
+	ATA_HOB = (1 << 7),	/* LBA48 selector */
+	ATA_NIEN = (1 << 1),	/* disable-irq flag */
+	/*ATA_LBA                 = (1 << 6), */ /* LBA28 selector */
+	ATA_DEV1 = (1 << 4),	/* Select Device 1 (slave) */
+	ATA_DEVICE_OBS = (1 << 7) | (1 << 5),	/* obs bits in dev reg */
+	ATA_DEVCTL_OBS = (1 << 3),	/* obsolete bit in devctl reg */
+	ATA_BUSY = (1 << 7),	/* BSY status bit */
+	ATA_DRDY = (1 << 6),	/* device ready */
+	ATA_DF = (1 << 5),	/* device fault */
+	ATA_DRQ = (1 << 3),	/* data request i/o */
+	ATA_ERR = (1 << 0),	/* have an error */
+	ATA_SRST = (1 << 2),	/* software reset */
+	ATA_ABORTED = (1 << 2),	/* command aborted */
+	/* ATA command block registers */
+	ATA_REG_DATA = 0x00,
+	ATA_REG_ERR = 0x01,
+	ATA_REG_NSECT = 0x02,
+	ATA_REG_LBAL = 0x03,
+	ATA_REG_LBAM = 0x04,
+	ATA_REG_LBAH = 0x05,
+	ATA_REG_DEVICE = 0x06,
+	ATA_REG_STATUS = 0x07,
+	ATA_PCI_CTL_OFS = 0x02,
+	/* and their aliases */
+	ATA_REG_FEATURE = ATA_REG_ERR,
+	ATA_REG_CMD = ATA_REG_STATUS,
+	ATA_REG_BYTEL = ATA_REG_LBAM,
+	ATA_REG_BYTEH = ATA_REG_LBAH,
+	ATA_REG_DEVSEL = ATA_REG_DEVICE,
+	ATA_REG_IRQ = ATA_REG_NSECT,
+
+	/* SETFEATURES stuff */
+	SETFEATURES_XFER = 0x03,
+	XFER_UDMA_7 = 0x47,
+	XFER_UDMA_6 = 0x46,
+	XFER_UDMA_5 = 0x45,
+	XFER_UDMA_4 = 0x44,
+	XFER_UDMA_3 = 0x43,
+	XFER_UDMA_2 = 0x42,
+	XFER_UDMA_1 = 0x41,
+	XFER_UDMA_0 = 0x40,
+	XFER_MW_DMA_2 = 0x22,
+	XFER_MW_DMA_1 = 0x21,
+	XFER_MW_DMA_0 = 0x20,
+	XFER_PIO_4 = 0x0C,
+	XFER_PIO_3 = 0x0B,
+	XFER_PIO_2 = 0x0A,
+	XFER_PIO_1 = 0x09,
+	XFER_PIO_0 = 0x08,
+	XFER_SW_DMA_2 = 0x12,
+	XFER_SW_DMA_1 = 0x11,
+	XFER_SW_DMA_0 = 0x10,
+	XFER_PIO_SLOW = 0x00
+};
 /*
  * ATA Commands (only mandatory commands listed here)
  */
diff --git a/include/common.h b/include/common.h
index 3c4b37b..d8b6b46 100644
--- a/include/common.h
+++ b/include/common.h
@@ -38,7 +38,7 @@ typedef volatile unsigned char	vu_char;
 #include <linux/string.h>
 #include <asm/ptrace.h>
 #include <stdarg.h>
-#if defined(CONFIG_PCI) && defined(CONFIG_440)
+#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
 #include <pci.h>
 #endif
 #if defined(CONFIG_8xx)
@@ -248,10 +248,11 @@ void	pci_init      (void);
 void	pci_init_board(void);
 void	pciinfo	      (int, int);
 
-#if defined(CONFIG_PCI) && defined(CONFIG_440)
-#   if defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
     int	   pci_pre_init	       (struct pci_controller * );
-#   endif
+#endif
+
+#if defined(CONFIG_PCI) && defined(CONFIG_440)
 #   if defined(CFG_PCI_TARGET_INIT)
 	void	pci_target_init	     (struct pci_controller *);
 #   endif
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 047e2f1..9acde1e 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -55,6 +55,10 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_DNS | \
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index d756f44..3fc99c5 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -37,6 +37,7 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
 #define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
@@ -56,6 +57,10 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 852d94a..4e2e1a8 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -57,6 +57,10 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 2260327..ab302df 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -56,6 +56,10 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index 90d3a8d..7b5f728 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -33,6 +33,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_CPCI440		1	    /* Board is ebony		*/
 #define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index ccd1f19..7fa9ed2 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -49,6 +49,7 @@
   /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
 #define CONFIG_SYSTEMACE 1
 #define CFG_SYSTEMACE_BASE 0xf0000000
+#define CFG_SYSTEMACE_WIDTH 8
 #define CONFIG_DOS_PARTITION 1
 
   /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 2ad6f06..48b94ee 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -38,6 +38,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
 #define CONFIG_440GX		  1	     /* Specifc GX support	*/
+#define CONFIG_440		  1	     /* ... PPC440 family	*/
 #define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
@@ -262,7 +263,6 @@
 #define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		     /* enable board pci_pre_init*/
 #define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index 465a4ec..7aae2bd 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -104,6 +104,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
 #define CONFIG_440GX		  1	     /* Specifc GX support	*/
+#define CONFIG_440		  1	     /* ... PPC440 family	*/
 #define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
@@ -331,7 +332,6 @@
 #define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		     /* enable board pci_pre_init*/
 #define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6976313..7e1005c 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -303,11 +303,11 @@
 #endif
 
 #define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1		1
+#define CONFIG_TSEC1		1
 
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2		1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR			0x1c
 #define TSEC2_PHY_ADDR			4
 #define TSEC1_PHYIDX			0
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0460be9..20c6d5a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -432,10 +432,10 @@
 #endif
 
 #define CONFIG_GMII		1	/* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1	1
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2	1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 0ff6580..72abd8e 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -375,18 +375,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE		/* In case CFG_CMD_MII is specified */
 
-#define CONFIG_MPC83XX_TSEC1
+#define CONFIG_TSEC1
 
-#ifdef CONFIG_MPC83XX_TSEC1
-#define CONFIG_MPC83XX_TSEC1_NAME  "TSEC0"
+#ifdef CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME  "TSEC0"
 #define CFG_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX		0
 #endif
 
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
-#define CONFIG_MPC83XX_TSEC2_NAME  "TSEC1"
+#define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET	0x25000
 #define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
 #define TSEC2_PHY_ADDR		4
@@ -637,11 +637,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_MPC83XX_TSEC1
+#ifdef CONFIG_TSEC1
 #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5aeea58..9176be3 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -366,10 +366,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 418a3a3..b568cb4 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -212,10 +212,10 @@
 #elif defined(CONFIG_TSEC_ENET)
 #define CONFIG_NET_MULTI 	1
 #define CONFIG_MII		1	/* MII PHY management	*/
-#define CONFIG_MPC85XX_TSEC1    1
-#define CONFIG_MPC85XX_TSEC1_NAME      "TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME      "TSEC1"
+#define CONFIG_TSEC1    1
+#define CONFIG_TSEC1_NAME      "TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME      "TSEC1"
 #define CONFIG_MPC85XX_FEC      1
 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 #define TSEC1_PHY_ADDR          7
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index fb360d2..e047e25 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 4c34308..7cd62e9 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC1"
-#define CONFIG_MPC85XX_TSEC3	1
-#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		0
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 680009d..a0d291e 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
-#define CONFIG_MPC85XX_TSEC3	1
-#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
-#define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC2"
+#undef CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		0
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 4c8b4e7..b7e703c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 21e6637..043397f 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -356,10 +356,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 3f65644..0ff0416 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
-#undef  CONFIG_MPC85XX_TSEC3
-#undef  CONFIG_MPC85XX_TSEC4
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#undef  CONFIG_TSEC3
+#undef  CONFIG_TSEC4
 #undef  CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 41daa2b..12af24f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -359,14 +359,14 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 
-#define CONFIG_MPC86XX_TSEC1    1
-#define CONFIG_MPC86XX_TSEC1_NAME       "eTSEC1"
-#define CONFIG_MPC86XX_TSEC2    1
-#define CONFIG_MPC86XX_TSEC2_NAME       "eTSEC2"
-#define CONFIG_MPC86XX_TSEC3    1
-#define CONFIG_MPC86XX_TSEC3_NAME       "eTSEC3"
-#define CONFIG_MPC86XX_TSEC4    1
-#define CONFIG_MPC86XX_TSEC4_NAME       "eTSEC4"
+#define CONFIG_TSEC1    1
+#define CONFIG_TSEC1_NAME       "eTSEC1"
+#define CONFIG_TSEC2    1
+#define CONFIG_TSEC2_NAME       "eTSEC2"
+#define CONFIG_TSEC3    1
+#define CONFIG_TSEC3_NAME       "eTSEC3"
+#define CONFIG_TSEC4    1
+#define CONFIG_TSEC4_NAME       "eTSEC4"
 
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 4fb5440..8f130f5 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -262,10 +262,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 87ab934..0286b53 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -258,10 +258,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 9da1d88..aa3627b 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -44,7 +44,7 @@
 
 #define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
 #define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
@@ -238,7 +238,7 @@
 	"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0"			\
 	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
 #else
-#define CUSTOM_ENV_SETTINGS 						\
+#define CUSTOM_ENV_SETTINGS						\
 	"bootfile=cam5200/uImage\0"					\
 	"u-boot=cam5200/u-boot.bin\0"					\
 	"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ed03577..4a5f8b6 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_NET_MULTI
 #endif
 
-#define CONFIG_MPC83XX_TSEC1		1
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2		1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR			2
 #define TSEC2_PHY_ADDR			1
 #define TSEC1_PHYIDX			0
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index f45f3a2..b0b9dd3 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -258,10 +258,10 @@
 #define CONFIG_NET_MULTI	1
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index 9b32514..f2ad097 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -238,7 +238,6 @@ extern void out32(unsigned int, unsigned long);
 #define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT		    /* let board init pci target    */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 0f447b0..517d130 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -75,7 +75,7 @@
 #define CFG_TEMP_STACK_OCM	1		/* OCM as init ram	*/
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_ADDR	0xf8000000
 #define CFG_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
 #define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of SRAM		*/
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of used area in RAM	*/
@@ -159,7 +159,7 @@
  */
 #define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
 #define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
+#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
 #define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
 #define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
 #define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 67f62d3..df057d9 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -29,6 +29,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_ALPR		1	    /* Board is ebony		*/
 #define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
@@ -94,7 +95,7 @@
 
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -256,7 +257,7 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC     	1       /* enable mdc/mwc commands      */
+#define CONFIG_MX_CYCLIC	1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
@@ -274,7 +275,6 @@
 #define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT		/* let board init pci target    */
 #define CFG_PCI_MASTER_INIT
 
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 763d1c7..d58344d 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -32,6 +32,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
 #define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_440		1	/* ... PPC440 family	        */
 #define CONFIG_4xx		1	/* ... PPC4xx family	        */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
@@ -73,9 +74,9 @@
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
 #define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_ADDR	0x70000000	/* DCache       */
 #define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data	*/
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
@@ -114,8 +115,8 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	256		    /* sectors per device   */
+#define CFG_MAX_FLASH_BANKS	3	/* number of banks			*/
+#define CFG_MAX_FLASH_SECT	256	/* sectors per device			*/
 
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
@@ -125,11 +126,11 @@
 #define CFG_FLASH_ADDR1         0x2aa
 #define CFG_FLASH_WORD_SIZE     unsigned char
 
-#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device      */
-#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device    */
+#define CFG_FLASH_2ND_16BIT_DEV 1	/* bamboo has 8 and 16bit device	*/
+#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device	*/
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -388,7 +389,6 @@
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index a42319b..4a1385c 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -32,6 +32,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_EBONY		1	    /* Board is ebony		*/
 #define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
@@ -121,7 +122,7 @@
 #define CFG_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
@@ -269,7 +270,6 @@
 #define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index cc47a16..a7eda07 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -314,7 +314,6 @@
 #undef CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT	1	/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT		/* let board init pci target    */
 #undef	CFG_PCI_MASTER_INIT
 
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 045a144..cbb59c5 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -273,7 +273,6 @@
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #undef  CFG_PCI_MASTER_INIT
 
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
new file mode 100644
index 0000000..1d87c73
--- /dev/null
+++ b/include/configs/lwmon5.h
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * lwmon5.h - configuration for lwmon5 board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LWMON5		1		/* Board is lwmon5	*/
+#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#define CONFIG_440		1		/* ... PPC440 family	*/
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_SYS_CLK_FREQ	33300000	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_BOOT_BASE_ADDR	0xf0000000
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_LIME_BASE_0         0xc0000000
+#define CFG_LIME_BASE_1         0xc1000000
+#define CFG_LIME_BASE_2         0xc2000000
+#define CFG_LIME_BASE_3         0xc3000000
+#define CFG_FPGA_BASE_0         0xc4000000
+#define CFG_FPGA_BASE_1         0xc4200000
+#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
+#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+
+#define CFG_USB2D0_BASE		0xe0000100
+#define CFG_USB_DEVICE		0xe0000000
+#define CFG_USB_HOST		0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+
+#define CFG_INIT_RAM_END	(4 << 10)
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK		/* no external clock provided	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/* define this if you want console on UART1 */
+#define CONFIG_UART1_CONSOLE	1	/* use UART1 as console		*/
+
+#define CFG_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CFG_ENV_SECT_SIZE	0x40000	/* size of one complete sector		*/
+#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM	(256)		/* 256MB			*/
+#define CFG_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
+#define CONFIG_DDR_DATA_EYE	1		/* use DDR2 optimization	*/
+#if 0 /* test-only: disable ECC for now */
+#define CONFIG_DDR_ECC		1		/* enable ECC			*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_RTC_PCF8563	1		/* enable Philips PCF8563 RTC	*/
+#define CFG_I2C_RTC_ADDR	0x51		/* Philips PCF8563 RTC address	*/
+
+#define CONFIG_PREBOOT	"echo;"						\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"hostname=lwmon5\0"						\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
+	"bootfile=/tftpboot/lwmon5/uImage\0"				\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC180000\0"					\
+	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
+	"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"	\
+		"cp.b 200000 FFF80000 80000\0"			        \
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		3	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	1
+
+/* USB */
+#ifdef CONFIG_440EPX
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#define CMD_USB			CFG_CMD_USB
+#else
+#define CMD_USB			0	/* no USB on 440GRx		*/
+#endif /* CONFIG_440EPX */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
+			       CFG_CMD_ASKENV	|	\
+			       CFG_CMD_DATE	|	\
+			       CFG_CMD_DHCP	|	\
+			       CFG_CMD_DIAG	|	\
+			       CFG_CMD_EEPROM	|	\
+			       CFG_CMD_ELF	|	\
+			       CFG_CMD_FAT	|	\
+			       CFG_CMD_I2C	|	\
+			       CFG_CMD_IRQ	|	\
+			       CFG_CMD_MII	|	\
+			       CFG_CMD_NET	|	\
+			       CFG_CMD_NFS	|	\
+			       CFG_CMD_PCI	|	\
+			       CFG_CMD_PING	|	\
+			       CFG_CMD_REGINFO	|	\
+			       CFG_CMD_SDRAM	|	\
+			       CMD_USB)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+
+#define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x03050200
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xdc000)
+
+/* Memory Bank 1 (Lime) initialization						*/
+#define CFG_EBC_PB1AP		0x01004380
+#define CFG_EBC_PB1CR		(CFG_LIME_BASE_0 | 0xdc000)
+
+/* Memory Bank 2 (FPGA) initialization						*/
+#define CFG_EBC_PB2AP		0x01004400
+#define CFG_EBC_PB2CR		(CFG_FPGA_BASE_0 | 0x1c000)
+
+/* Memory Bank 3 (FPGA2) initialization						*/
+#define CFG_EBC_PB3AP		0x01004400
+#define CFG_EBC_PB3CR		(CFG_FPGA_BASE_1 | 0x1c000)
+
+#define CFG_EBC_CFG		0xb8400000
+
+/*-----------------------------------------------------------------------
+ * Graphics (Fujitsu Lime)
+ *----------------------------------------------------------------------*/
+/* SDRAM Clock frequency adjustment register */
+#define CFG_LIME_SDRAM_CLOCK	0xC1FC0000
+/* Lime Clock frequency is to set 133MHz */
+#define CFG_LIME_CLOCK_133MHZ	0x10000
+
+/* SDRAM Parameter register */
+#define CFG_LIME_MMR		0xC1FCFFFC
+/* SDRAM parameter value */
+#define CFG_LIME_MMR_VALUE	0x414FB7F2
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_GPIO_PHY1_RST	12
+#define CFG_GPIO_FLASH_WP	14
+#define CFG_GPIO_PHY0_RST	22
+#define CFG_GPIO_WATCHDOG	58
+#define CFG_GPIO_LIME_S		59
+#define CFG_GPIO_LIME_RST	60
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	      /* ...			            */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index fe4e638..68e8cec 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -41,6 +41,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_OCOTEA		1	    /* Board is ebony		*/
 #define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
@@ -136,7 +137,7 @@
 #define CFG_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
@@ -293,7 +294,6 @@
 #define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT		/* let board init pci target    */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index aa0901f..22f9f84 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -35,6 +35,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_P3P440		1	    /* Board is P3P440		*/
 #define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/
@@ -226,7 +227,6 @@
 #define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
 
 #define CONFIG_DISABLE_PISE_TEST	/* disable PISE test (PCIX only)*/
@@ -285,7 +285,7 @@
 
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 23bdfc8..751b512 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -32,6 +32,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
 #define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_440		1	/* ... PPC440 family	        */
 #define CONFIG_4xx		1	/* ... PPC4xx family	        */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
@@ -103,7 +104,7 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -266,7 +267,6 @@
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
@@ -315,76 +315,76 @@
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
  */
-#define CFG_440_GPIO_TABLE { /*		GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CFG_440_GPIO_TABLE { /*	  Out		       GPIO	Alternate1	Alternate2   Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6	EBC_CS_N(1)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7	EBC_CS_N(2)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8	EBC_CS_N(3)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9	EBC_CS_N(4)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10	EBC_CS_N(5)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11	EBC_BUS_ERR			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12	ZII_p0Rxd(0)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13	ZII_p0Rxd(1)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14	ZII_p0Rxd(2)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15	ZII_p0Rxd(3)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16	ZII_p0Txd(0)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17	ZII_p0Txd(1)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18	ZII_p0Txd(2)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19	ZII_p0Txd(3)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20	ZII_p0Rx_er			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21	ZII_p0Rx_dv			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22	ZII_p0RxCrs			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23	ZII_p0Tx_er			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24	ZII_p0Tx_en			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25	ZII_p0Col			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26			USB2D_RXVALID	*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28			USB2D_TXVALID	*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO10	EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO11	EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12	ZII_p0Rxd(0)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13	ZII_p0Rxd(1)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14	ZII_p0Rxd(2)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15	ZII_p0Rxd(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16	ZII_p0Txd(0)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17	ZII_p0Txd(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18	ZII_p0Txd(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19	ZII_p0Txd(3)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20	ZII_p0Rx_er			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21	ZII_p0Rx_dv			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22	ZII_p0RxCrs			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23	ZII_p0Tx_er			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24	ZII_p0Tx_en			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25	ZII_p0Col			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO26			USB2D_RXVALID	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO28			USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
 },											\
 {											\
 /* GPIO Core 1 */									\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32	USB2D_OPMODE0			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33	USB2D_OPMODE1			*/	\
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37	UART0_RTS_N			*/	\
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40	UIC_IRQ(0)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41	UIC_IRQ(1)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42	UIC_IRQ(2)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43	UIC_IRQ(3)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
-{ GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO32	USB2D_OPMODE0			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO33	USB2D_OPMODE1			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37	UART0_RTS_N			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40	UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41	UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42	UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43	UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_BI,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO63  Unselect via TraceSelect Bit	*/	\
 }											\
 }
 
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 65aac5c..e6e3866 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -401,10 +401,10 @@
 #define CONFIG_NET_MULTI	1
 #endif
 
-#define CONFIG_MPC83XX_TSEC1	1
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2	1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define CONFIG_PHY_BCM5421S	1
 #define TSEC1_PHY_ADDR		0x19
 #define TSEC2_PHY_ADDR		0x1a
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index d7d07a6..8b2ec07 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -182,6 +182,15 @@
 #undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
 
 /************************************************************
+*SATA/Native Stuff
+************************************************************/
+#define CFG_SATA_SUPPORTED      1
+#define CFG_SATA_MAXBUS         2       /*Max Sata buses supported */
+#define CFG_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
+#define CFG_SATA_MAXDEVICES     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_ATA_PIIX            1       /*Supports ata_piix driver */
+
+/************************************************************
  * ATAPI support (experimental)
  ************************************************************/
 #define CONFIG_ATAPI			/* enable ATAPI Support */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 23243a4..3219992 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -37,6 +37,7 @@
 #else
 #define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
 #endif
+#define CONFIG_440		1		/* ... PPC440 family	*/
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 /* Detect Sequoia PLL input clock automatically via CPLD bit		*/
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
@@ -58,6 +59,7 @@
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
 #define CFG_OCM_BASE		0xe0010000      /* ocm			*/
+#define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
 #define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
 #define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
 #define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
@@ -80,7 +82,7 @@
 #define CFG_INIT_RAM_END	(4 << 10)
 #define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -125,7 +127,7 @@
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -327,6 +329,22 @@
 			       CFG_CMD_SDRAM	|	\
 			       CMD_USB)
 
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_UART	   | \
+				 CFG_POST_I2C	   | \
+				 CFG_POST_CACHE	   | \
+				 CFG_POST_FPU	   | \
+				 CFG_POST_ETHER	   | \
+				 CFG_POST_SPR)
+
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR	0x10000000 /* free virtual address	*/
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
 #define CONFIG_SUPPORT_VFAT
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -370,7 +388,6 @@
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 625cf20..21065b9 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -230,10 +230,10 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 1978a32..2e527b2 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -42,20 +42,20 @@
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_STXSSA		1	/* Silicon Tx GPPP SSA board specific*/
 
-#undef  CONFIG_PCI	         	/* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
-#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_PCI			/* PCI ethernet support	*/
+#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
-#undef CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 
 /* sysclk for MPC85xx
  */
 
-#define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
+#define CONFIG_SYS_CLK_FREQ	33000000 /* most pci cards are 33Mhz */
 
 /* Blinkin' LEDs for Robert :-)
 */
@@ -64,23 +64,23 @@
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
-#define  CONFIG_BTB                          /* toggle branch predition */
-#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	       */
+#define  CONFIG_BTB				/* toggle branch predition */
+#define  CONFIG_ADDR_STREAMING			/* toggle addr streaming	*/
 
-#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
+#define CONFIG_BOARD_EARLY_INIT_F   1	     	/* Call board_pre_init	 */
 
-#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
-#define CFG_MEMTEST_START       0x00200000  /* memtest region */
-#define CFG_MEMTEST_END         0x00400000
+#undef	CFG_DRAM_TEST			    	/* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00200000  	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
 
 
-/* Localbus connector.  There are many options that can be
+/* Localbus connector.	There are many options that can be
  * connected here, including sdram or lots of flash.
  * This address, however, is used to configure a 256M local bus
  * window that includes the Config latch below.
  */
-#define CFG_LBC_OPTION_BASE	0xF0000000      /* Localbus Extension */
+#define CFG_LBC_OPTION_BASE	0xF0000000	/* Localbus Extension */
 #define CFG_LBC_OPTION_SIZE	256		/* 256MB */
 
 /* There are various flash options used, we configure for the largest,
@@ -88,16 +88,16 @@
  * sizes.
  */
 #ifdef CONFIG_STXSSA_4M
-#define CFG_FLASH_BASE		0xFFC00000      /* start of  4 MiB flash */
+#define CFG_FLASH_BASE		0xFFC00000	/* start of  4 MiB flash */
 #else
-#define CFG_FLASH_BASE		0xFC000000      /* start of 64 MiB flash */
+#define CFG_FLASH_BASE		0xFC000000	/* start of 64 MiB flash */
 #endif
 #define CFG_BR0_PRELIM	(CFG_FLASH_BASE | 0x1801) /* port size 32bit	 */
 #define CFG_OR0_PRELIM	(CFG_FLASH_BASE | 0x0FF7)
 
 #define CFG_FLASH_CFI		1
 #define CFG_FLASH_CFI_DRIVER	1
-#undef CFG_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster) */
+#undef CFG_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
 #define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
 
@@ -110,22 +110,22 @@
  */
 #define CFG_LBC_CFGLATCH_BASE	0xFB000000	/* Base of config latch */
 #define CFG_BR1_PRELIM		0xFB001801	/* 32-bit port */
-#define CFG_OR1_PRELIM		0xFFFF0FF7      /* 64K is enough */
+#define CFG_OR1_PRELIM		0xFFFF0FF7	/* 64K is enough */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef	CFG_RAMBOOT
 #endif
 
 #ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT 	0x40000000	/* CCSRBAR by BDI cfg	*/
+#define CFG_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
 #else
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
-#define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
@@ -140,14 +140,14 @@
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
+#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
 #define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq	*/
 #define CFG_LBC_LBCR		0x00000000
 #define CFG_LBC_LSRT		0x20000000
 #define CFG_LBC_MRTPR		0x20000000
@@ -158,52 +158,52 @@
 #define CFG_LBC_LSDMR_5		0x4061b723
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(512 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_REG_SIZE	1
 #define CFG_NS16550_CLK		get_bus_freq(0)
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* I2C */
 #define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
-#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #if 0
-#define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x00}	/* Don't probe these addrs */
 #else
 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
 #undef CFG_I2C_NOPROBES
 #endif
 #define CFG_I2C_OFFSET		0x3000
 
-/* I2C EEPROM.  AT24C32, we keep our environment in here.
+/* I2C EEPROM.	AT24C32, we keep our environment in here.
 */
 #define CFG_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
 #define CFG_I2C_EEPROM_ADDR_LEN		2
@@ -232,35 +232,35 @@
 #if defined(CONFIG_PCI) 		/* PCI Ethernet card */
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CONFIG_TULIP
 
 #if !defined(CONFIG_PCI_PNP)
-  #define PCI_ENET0_IOADDR    	0xe0000000
-  #define PCI_ENET0_MEMADDR     0xe0000000
-  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
+  #define PCI_ENET0_IOADDR	0xe0000000
+  #define PCI_ENET0_MEMADDR	0xe0000000
+  #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
-#undef CONFIG_PCI_SCAN_SHOW
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPS85XX_FEC
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		4
@@ -270,9 +270,9 @@
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
-#define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
-#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
-#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
+#define CONFIG_ETHER_ON_FCC2		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
 
 #if (CONFIG_ETHER_INDEX == 2)
   /*
@@ -281,19 +281,19 @@
    * - Select bus for bd/buffers
    * - Full duplex
    */
-  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-  #define CFG_CPMFCR_RAMTYPE    0
+  #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CFG_CPMFCR_RAMTYPE	0
 #if 0
-  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+  #define CFG_FCC_PSMR		(FCC_PSMR_FDE)
 #else
-  #define CFG_FCC_PSMR          0
+  #define CFG_FCC_PSMR		0
 #endif
   #define FETH2_RST		0x01
 #elif (CONFIG_ETHER_INDEX == 3)
   /* need more definitions here for FE3 */
   #define FETH3_RST		0x80
-#endif  				/* CONFIG_ETHER_INDEX */
+#endif					/* CONFIG_ETHER_INDEX */
 
 /* MDIO is done through the TSEC0 control.
 */
@@ -415,13 +415,13 @@
  */
 #ifdef CFG_ENV_IS_IN_EEPROM		/* use restricted "standard" environment */
 
-#define CONFIG_BAUDRATE	 	38400
+#define CONFIG_BAUDRATE		38400
 
 #define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 #define CONFIG_BOOTCOMMAND	"bootm 0xffc00000 0xffd00000"
 #define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 #define CONFIG_SERVERIP 	192.168.85.1
-#define CONFIG_IPADDR  		192.168.85.60
+#define CONFIG_IPADDR		192.168.85.60
 #define CONFIG_GATEWAYIP	192.168.85.1
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_HOSTNAME 	STX_SSA
@@ -431,7 +431,7 @@
 
 #else /* ENV IS IN FLASH		-- use a full-blown envionment */
 
-#define CONFIG_BAUDRATE	 	115200
+#define CONFIG_BAUDRATE		115200
 
 #define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
 
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 2b28f93..d756be7 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -30,6 +30,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_TAISHAN		1	/* Board is taishan		*/
 #define CONFIG_440GX		1	/* Specifc GX support		*/
+#define CONFIG_440		1	/* ... PPC440 family		*/
 #define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #undef	CFG_DRAM_TEST			/* Disable-takes long time!	*/
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
@@ -217,8 +218,8 @@
 #define CONFIG_EMAC_NR_START	2	/* start with EMAC 2 (skip 0&1)	*/
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_NET_MULTI	1
-#define CONFIG_PHY_ADDR	      	0xff	     /* no phy on EMAC0		*/
-#define CONFIG_PHY1_ADDR      	0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY_ADDR		0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR	0xff	     /* no phy on EMAC1		*/
 #define CONFIG_PHY2_ADDR	0x1
 #define CONFIG_PHY3_ADDR	0x3
 #define CONFIG_ET1011C_PHY	1
@@ -297,7 +298,6 @@
 #define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT		/* let board init pci target    */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index b68ae54..3b106ef 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -38,6 +38,7 @@
 #define CONFIG_440GR		1	/* Specific PPC440GR support	*/
 #define CONFIG_HOSTNAME		yellowstone
 #endif
+#define CONFIG_440		1	/* ... PPC440 family		*/
 #define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
 
@@ -122,7 +123,7 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -311,7 +312,6 @@
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 7f8b022..1fdcc4b 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -289,7 +289,6 @@
 #undef CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT	1	/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT		/* let board init pci target    */
 #undef	CFG_PCI_MASTER_INIT
 
diff --git a/include/logbuff.h b/include/logbuff.h
index 3acfc18..d415729 100644
--- a/include/logbuff.h
+++ b/include/logbuff.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2007
  * Detlev Zundel, dzu@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,6 +25,7 @@
 
 #ifdef CONFIG_LOGBUFFER
 
+#define LOGBUFF_MAGIC	0xc0de4ced	/* Forced by code, eh!	*/
 #define LOGBUFF_LEN	(16384)	/* Must be 16k right now */
 #define LOGBUFF_MASK	(LOGBUFF_LEN-1)
 #define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
@@ -32,6 +33,29 @@
 
 #define LOGBUFF_INITIALIZED	(1<<31)
 
+/* The mapping used here has to be the same as in setup_ext_logbuff ()
+   in linux/kernel/printk */
+
+typedef struct {
+	union {
+		struct {
+			unsigned long	tag;
+			unsigned long	start;
+			unsigned long	con;
+			unsigned long	end;
+			unsigned long	chars;
+		} v2;
+		struct {
+			unsigned long	dummy;
+			unsigned long	tag;
+			unsigned long	start;
+			unsigned long	size;
+			unsigned long	chars;
+		} v1;
+	};
+	unsigned char	buf[0];
+} logbuff_t;
+
 int drv_logbuff_init (void);
 void logbuff_init_ptrs (void);
 void logbuff_log(char *msg);
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
index 7508f6d..414651f 100644
--- a/include/mpc5xx.h
+++ b/include/mpc5xx.h
@@ -36,6 +36,7 @@
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /*-----------------------------------------------------------------------
  * ISB bit in IMMR to set internal memory map
@@ -75,10 +76,10 @@
 #define SIUMCR_DBPC01	0x00080000	/* - " -				*/
 #define SIUMCR_DBPC10	0x00100000	/* - " -				*/
 #define SIUMCR_DBPC11	0x00180000	/* - " -				*/
-#define SIUMCR_GPC00	0x00000000	/* General Pins Config 			*/
-#define SIUMCR_GPC01	0x00020000	/* General Pins Config 			*/
-#define SIUMCR_GPC10	0x00040000	/* General Pins Config 			*/
-#define SIUMCR_GPC11	0x00060000	/* General Pins Config 			*/
+#define SIUMCR_GPC00	0x00000000	/* General Pins Config			*/
+#define SIUMCR_GPC01	0x00020000	/* General Pins Config			*/
+#define SIUMCR_GPC10	0x00040000	/* General Pins Config			*/
+#define SIUMCR_GPC11	0x00060000	/* General Pins Config			*/
 #define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
 #define SIUMCR_SC00	0x00000000	/* Multi Chip 32 bit			*/
 #define SIUMCR_SC01	0x00004000	/* Muilt Chip 16 bit			*/
@@ -89,7 +90,7 @@
 #define SIUMCR_MLRC01	0x00000400	/* - " -				*/
 #define SIUMCR_MLRC10	0x00000800	/* - " -				*/
 #define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
-#define SIUMCR_MTSC	0x00000100	/* Memory transfer      		*/
+#define SIUMCR_MTSC	0x00000100	/* Memory transfer			*/
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control Register
@@ -122,13 +123,13 @@
  * SCCR - System Clock and reset Control Register
  */
 #define SCCR_DFNL_MSK	0x00000070	/* DFNL mask				*/
-#define SCCR_DFNH_MSK	0x00000007  	/* DFNH mask				*/
+#define SCCR_DFNH_MSK	0x00000007	/* DFNH mask				*/
 #define SCCR_DFNL_SHIFT 0x0000004	/* DFNL shift value			*/
 #define SCCR_RTSEL	0x00100000	/* RTC circuit input source select	*/
 #define SCCR_EBDF00	0x00000000	/* Division factor 1. CLKOUT is GCLK2   */
 #define SCCR_EBDF11	0x00060000	/* reserved				*/
 #define SCCR_TBS	0x02000000	/* Time Base Source			*/
-#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide 			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
 #define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
 #define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
 #define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
@@ -137,11 +138,11 @@
 /*-----------------------------------------------------------------------
  * MC - Memory Controller
  */
-#define BR_V		0x00000001	/* Bank valid 				*/
-#define BR_BI		0x00000002	/* Burst inhibit 			*/
-#define BR_PS_8		0x00000400	/* 8 bit port size 			*/
-#define BR_PS_16	0x00000800	/* 16 bit port size 			*/
-#define BR_PS_32	0x00000000	/* 32 bit port size 			*/
+#define BR_V		0x00000001	/* Bank valid				*/
+#define BR_BI		0x00000002	/* Burst inhibit			*/
+#define BR_PS_8		0x00000400	/* 8 bit port size			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size			*/
 #define BR_LBDIR	0x00000008	/* Late burst data in progess		*/
 #define BR_SETA		0x00000004	/* External Data Acknowledge		*/
 #define OR_SCY_3	0x00000030	/* 3 clock cycles wait states		*/
@@ -158,8 +159,8 @@
 /*-----------------------------------------------------------------------
  * UMCR - UIMB Module Configuration Register
  */
-#define UMCR_FSPEED 	0x00000000	/* Full speed. Opposit of UMCR_HSPEED	*/
-#define UMCR_HSPEED 	0x10000000	/* Half speed				*/
+#define UMCR_FSPEED	0x00000000	/* Full speed. Opposit of UMCR_HSPEED	*/
+#define UMCR_HSPEED	0x10000000	/* Half speed				*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
@@ -173,16 +174,16 @@
  * SCI - Serial communication interface
  */
 
-#define SCI_TDRE	0x0100		/* Transmit data register empty 	*/
-#define SCI_TE		0x0008		/* Transmitter enabled 			*/
+#define SCI_TDRE	0x0100		/* Transmit data register empty		*/
+#define SCI_TE		0x0008		/* Transmitter enabled			*/
 #define SCI_RE		0x0004		/* Receiver enabled			*/
-#define SCI_RDRF	0x0040		/* Receive data register full 		*/
-#define SCI_PE		0x0400		/* Parity enable 			*/
-#define SCI_SCXBR_MK	0x1fff		/* Baudrate mask 			*/
-#define SCI_SCXDR_MK	0x00ff		/* Data register mask 			*/
+#define SCI_RDRF	0x0040		/* Receive data register full		*/
+#define SCI_PE		0x0400		/* Parity enable			*/
+#define SCI_SCXBR_MK	0x1fff		/* Baudrate mask			*/
+#define SCI_SCXDR_MK	0x00ff		/* Data register mask			*/
 #define SCI_M_11	0x0200		/* Frame size is 11 bit			*/
 #define SCI_M_10	0x0000		/* Frame size is 10 bit			*/
-#define SCI_PORT_1	((int)1)	/* Place this later somewhere better 	*/
+#define SCI_PORT_1	((int)1)	/* Place this later somewhere better	*/
 #define SCI_PORT_2	((int)2)
 
 #endif	/* __MPC5XX_H__ */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 089aa13..a4581a3 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -39,6 +39,7 @@
 
 /* Exception offsets (PowerPC standard) */
 #define EXC_OFF_SYS_RESET	0x0100
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /* useful macros for manipulating CSx_START/STOP */
 #if defined(CONFIG_MGT5100)
diff --git a/include/mpc8220.h b/include/mpc8220.h
index ff7acc6..d3b1457 100644
--- a/include/mpc8220.h
+++ b/include/mpc8220.h
@@ -35,6 +35,7 @@
 
 /* Exception offsets (PowerPC standard) */
 #define EXC_OFF_SYS_RESET   0x0100
+#define _START_OFFSET	EXC_OFF_SYS_RESET
 
 /* Internal memory map */
 /* MPC8220 Internal Register MMAP */
diff --git a/include/mpc824x.h b/include/mpc824x.h
index 30fc795..30f01d5 100644
--- a/include/mpc824x.h
+++ b/include/mpc824x.h
@@ -88,7 +88,7 @@
 #define	PREP_PCI_MEMORY_BUS	0x80000000
 #define	PREP_PCI_MEMORY_SIZE	0x80000000
 #define MPC107_PCI_CMD		0x80000004	/* MPC107 PCI cmd reg */
-#define MPC107_PCI_STAT 	0x80000006	/* MPC107 PCI status reg */
+#define MPC107_PCI_STAT		0x80000006	/* MPC107 PCI status reg */
 #define PROC_INT1_ADR		0x800000a8	/* MPC107 Processor i/f cfg1 */
 #define PROC_INT2_ADR		0x800000ac	/* MPC107 Processor i/f cfg2 */
 #define MEM_CONT1_ADR		0x800000f0	/* MPC107 Memory control config. 1 */
@@ -98,8 +98,8 @@
 #define MEM_ERREN1_ADR		0x800000c0	/* MPC107 Memory error enable 1 */
 #define MEM_START1_ADR		0x80000080	/* MPC107 Memory starting addr */
 #define MEM_START2_ADR		0x80000084	/* MPC107 Memory starting addr-lo */
-#define XMEM_START1_ADR 	0x80000088	/* MPC107 Extended mem. start addr-hi*/
-#define XMEM_START2_ADR 	0x8000008c	/* MPC107 Extended mem. start addr-lo*/
+#define XMEM_START1_ADR		0x80000088	/* MPC107 Extended mem. start addr-hi*/
+#define XMEM_START2_ADR		0x8000008c	/* MPC107 Extended mem. start addr-lo*/
 #define MEM_END1_ADR		0x80000090	/* MPC107 Memory ending address */
 #define MEM_END2_ADR		0x80000094	/* MPC107 Memory ending addr-lo */
 #define XMEM_END1_ADR		0x80000098	/* MPC107 Extended mem. end addrs-hi */
@@ -142,6 +142,8 @@
 #define EXC_OFF_JMDDI		0x1600	/* Java Mode denorm detect Interr -- WTF??*/
 #define EXC_OFF_RMTE		0x2000	/* Run Mode or Trace Exception */
 
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
 #define MAP_A_CONFIG_ADDR_HIGH	0x8000	/* Upper half of CONFIG_ADDR for Map A */
 #define MAP_A_CONFIG_ADDR_LOW	0x0CF8	/* Lower half of CONFIG_ADDR for Map A */
 #define MAP_A_CONFIG_DATA_HIGH	0x8000	/* Upper half of CONFIG_DAT for Map A */
diff --git a/include/mpc8260.h b/include/mpc8260.h
index d9dd92d..0525294 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -53,7 +53,7 @@
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/
-
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration Register					 4-25
@@ -664,7 +664,7 @@
 #define PSDMR_CL_3	     0x00000003	/* CAS Latency = 3		*/
 
 /*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register			 	10-24
+ * LSDMR - Local Bus SDRAM Mode Register				10-24
  */
 
 /*
@@ -707,23 +707,23 @@
 /*-----------------------------------------------------------------------
  * TMR1-TMR4 - Timer Mode Registers					17-6
  */
-#define TMRx_PS_MSK		0xff00	/* Prescaler Value 		*/
+#define TMRx_PS_MSK		0xff00	/* Prescaler Value		*/
 #define TMRx_CE_MSK		0x00c0	/* Capture Edge and Enable Interrupt*/
-#define TMRx_OM			0x0020	/* Output Mode 			*/
+#define TMRx_OM			0x0020	/* Output Mode			*/
 #define TMRx_ORI		0x0010	/* Output Reference Interrupt Enable*/
-#define TMRx_FRR		0x0008	/* Free Run/Restart 		*/
+#define TMRx_FRR		0x0008	/* Free Run/Restart		*/
 #define TMRx_ICLK_MSK		0x0006	/* Timer Input Clock Source mask */
-#define TMRx_GE			0x0001	/* Gate Enable  		*/
+#define TMRx_GE			0x0001	/* Gate Enable			*/
 
 #define TMRx_CE_INTR_DIS	0x0000	/* Disable Interrupt on capture event*/
 #define TMRx_CE_RISING		0x0040	/* Capture on Rising TINx edge only */
 #define TMRx_CE_FALLING		0x0080	/* Capture on Falling TINx edge only */
-#define TMRx_CE_ANY		0x00c0	/* Capture on any TINx edge 	*/
+#define TMRx_CE_ANY		0x00c0	/* Capture on any TINx edge	*/
 
-#define TMRx_ICLK_IN_CAS	0x0000	/* Internally cascaded input 	*/
+#define TMRx_ICLK_IN_CAS	0x0000	/* Internally cascaded input	*/
 #define TMRx_ICLK_IN_GEN	0x0002	/* Internal General system clock*/
 #define TMRx_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16*/
-#define TMRx_ICLK_TIN_PIN	0x0006	/* TINx pin 			*/
+#define TMRx_ICLK_TIN_PIN	0x0006	/* TINx pin			*/
 
 
 /*-----------------------------------------------------------------------
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 60fc214..336c0ac 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -25,6 +25,7 @@
 /* System reset offset (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET		0x0100
+#define	_START_OFFSET			EXC_OFF_SYS_RESET
 
 /* IMMRBAR - Internal Memory Register Base Address
  */
@@ -438,9 +439,9 @@
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
 #if defined(CONFIG_MPC831X)
-#define HRCWH_ROM_LOC_NAND_SP_8BIT 	0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
-#define HRCWH_ROM_LOC_NAND_LP_8BIT 	0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
 #define HRCWH_ROM_LOC_NAND_LP_16BIT	0x00600000
 
 #define HRCWH_RL_EXT_LEGACY		0x00000000
@@ -1217,7 +1218,7 @@
 #define FCR_CMD1		0x00FF0000
 #define FCR_CMD1_SHIFT		16
 #define FCR_CMD2		0x0000FF00
-#define FCR_CMD2_SHIFT   	8
+#define FCR_CMD2_SHIFT		8
 #define FCR_CMD3		0x000000FF
 #define FCR_CMD3_SHIFT		0
 
@@ -1241,8 +1242,8 @@
 /* LTESR - Transfer Error Status Register
  */
 #define LTESR_BM		0x80000000
-#define LTESR_FCT 		0x40000000
-#define LTESR_PAR 		0x20000000
+#define LTESR_FCT		0x40000000
+#define LTESR_PAR		0x20000000
 #define LTESR_WP		0x04000000
 #define LTESR_ATMW		0x00800000
 #define LTESR_ATMR		0x00400000
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index a4d99b2..6fbd504 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -8,6 +8,7 @@
 #define __MPC85xx_H__
 
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset	*/
+#define	_START_OFFSET		EXC_OFF_SYS_RESET
 
 #if defined(CONFIG_E500)
 #include <e500.h>
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 673bfed..9fd349a 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -8,7 +8,7 @@
 #define __MPC86xx_H__
 
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
-
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /*
  * platform register addresses
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 2911758..bef748f 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -35,7 +35,7 @@
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
-
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control Register				11-9
@@ -208,12 +208,12 @@
 #define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
 #define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
 #define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
-#define SCCR_DFNL001	0x00000100	/* Division by 4 	                */
-#define SCCR_DFNL010	0x00000200	/* Division by 8 	                */
-#define SCCR_DFNL011	0x00000300	/* Division by 16 	                */
-#define SCCR_DFNL100	0x00000400	/* Division by 32 	                */
-#define SCCR_DFNL101	0x00000500	/* Division by 64 	                */
-#define SCCR_DFNL110	0x00000600	/* Division by 128 	                */
+#define SCCR_DFNL001	0x00000100	/* Division by 4	                */
+#define SCCR_DFNL010	0x00000200	/* Division by 8	                */
+#define SCCR_DFNL011	0x00000300	/* Division by 16	                */
+#define SCCR_DFNL100	0x00000400	/* Division by 32	                */
+#define SCCR_DFNL101	0x00000500	/* Division by 64	                */
+#define SCCR_DFNL110	0x00000600	/* Division by 128	                */
 #define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
 #define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
 #define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/
diff --git a/include/post.h b/include/post.h
index cdefbdd..8259e5d 100644
--- a/include/post.h
+++ b/include/post.h
@@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void);
 #define CFG_POST_SYSMON		0x00000800
 #define CFG_POST_DSP		0x00001000
 #define CFG_POST_CODEC		0x00002000
+#define CFG_POST_FPU		0x00004000
 
 #endif /* CONFIG_POST */
 
diff --git a/include/ppc405.h b/include/ppc405.h
index 71ad12e..8e64731 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -27,6 +27,15 @@
 /*--------------------------------------------------------------------- */
 	#define  srr2  0x3de      /* save/restore register 2 */
 	#define  srr3  0x3df      /* save/restore register 3 */
+
+	/*
+	 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
+	 * exception for the exact same purposes - let's alias them and have a
+	 * common handling in crit_return() and CRIT_EXCEPTION
+	 */
+	#define  csrr0 srr2
+	#define  csrr1 srr3
+
 	#define  dbsr  0x3f0      /* debug status register */
 	#define  dbcr0 0x3f2      /* debug control register 0 */
 	#define  dbcr1 0x3bd      /* debug control register 1 */
@@ -134,12 +143,12 @@
 #define UIC_USBH1	0x00040000	/* USB Host 1			*/
 #define UIC_USBH2	0x00020000	/* USB Host 2			*/
 #define UIC_USBDEV	0x00010000	/* USB Device			*/
-#define UIC_ENET	0x00008000	/* Ethernet interrupt status 	*/
-#define UIC_ENET1	0x00008000	/* dummy define              	*/
+#define UIC_ENET	0x00008000	/* Ethernet interrupt status	*/
+#define UIC_ENET1	0x00008000	/* dummy define			*/
 #define UIC_EMAC_WAKE	0x00004000	/* EMAC wake up			*/
 
 #define UIC_MADMAL	0x00002000	/* Logical OR of following MadMAL int */
-#define UIC_MAL_SERR 	0x00002000	/*   MAL SERR			*/
+#define UIC_MAL_SERR	0x00002000	/*   MAL SERR			*/
 #define UIC_MAL_TXDE	0x00002000	/*   MAL TXDE			*/
 #define UIC_MAL_RXDE	0x00002000	/*   MAL RXDE			*/
 
@@ -877,7 +886,7 @@
 #define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register                  */
 #define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register		     */
 #define reset   (CNTRL_DCR_BASE+0x3)  /* reset register			     */
-#define strap   (CNTRL_DCR_BASE+0x4)  /* strap register		   	     */
+#define strap   (CNTRL_DCR_BASE+0x4)  /* strap register			     */
 
 #define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
 
@@ -1110,13 +1119,13 @@
 | UART Register Offsets
 '----------------------------------------------------------------------------*/
 #define		DATA_REG	0x00
-#define		DL_LSB    	0x00
-#define		DL_MSB  	0x01
+#define		DL_LSB		0x00
+#define		DL_MSB		0x01
 #define		INT_ENABLE      0x01
 #define		FIFO_CONTROL    0x02
 #define		LINE_CONTROL    0x03
 #define		MODEM_CONTROL   0x04
-#define		LINE_STATUS  	0x05
+#define		LINE_STATUS	0x05
 #define		MODEM_STATUS    0x06
 #define		SCRATCH         0x07
 
diff --git a/include/ppc440.h b/include/ppc440.h
index 07f75de..93c10f1 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -82,10 +82,7 @@
 #define	 ivor13 0x19d	/* interrupt vector offset register 13 */
 #define	 ivor14 0x19e	/* interrupt vector offset register 14 */
 #define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440)
 #define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
 #define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
 #define	 mcsr	0x23c	/* machine check status register */
@@ -115,7 +112,7 @@
 #define	 icdbtrh 0x39f	/* instruction cache debug tag register high */
 #define	 mmucr	0x3b2	/* mmu control register */
 #define	 ccr0	0x3b3	/* core configuration register 0 */
-#define  ccr1  	0x378	/* core configuration for 440x5 only */
+#define  ccr1	0x378	/* core configuration for 440x5 only */
 #define	 icdbdr 0x3d3	/* instruction cache debug data register */
 #define	 dbdr	0x3f3	/* debug data register */
 
@@ -139,7 +136,7 @@
 #define clk_opbd	0x00c0
 #define clk_perd	0x00e0
 #define clk_mald	0x0100
-#define clk_spcid   	0x0120
+#define clk_spcid	0x0120
 #define clk_icfg	0x0140
 
 /* 440gx sdr register definations */
@@ -285,6 +282,30 @@
 #define sdr_sdstp3	0x4003
 #endif	/* CONFIG_440GX */
 
+/*----------------------------------------------------------------------------+
+| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
++----------------------------------------------------------------------------*/
+#define CCR0_PRE		0x40000000
+#define CCR0_CRPE		0x08000000
+#define CCR0_DSTG		0x00200000
+#define CCR0_DAPUIB		0x00100000
+#define CCR0_DTB		0x00008000
+#define CCR0_GICBT		0x00004000
+#define CCR0_GDCBT		0x00002000
+#define CCR0_FLSTA		0x00000100
+#define CCR0_ICSLC_MASK		0x0000000C
+#define CCR0_ICSLT_MASK		0x00000003
+#define CCR1_TCS_MASK		0x00000080
+#define CCR1_TCS_INTCLK		0x00000000
+#define CCR1_TCS_EXTCLK		0x00000080
+#define MMUCR_SWOA		0x01000000
+#define MMUCR_U1TE		0x00400000
+#define MMUCR_U2SWOAE		0x00200000
+#define MMUCR_DULXE		0x00800000
+#define MMUCR_IULXE		0x00400000
+#define MMUCR_STS		0x00100000
+#define MMUCR_STID_MASK		0x000000FF
+
 #ifdef CONFIG_440SPE
 #undef sdr_sdstp2
 #define sdr_sdstp2	0x0022
@@ -310,30 +331,6 @@
 #define sdr_sdstp6	0x4005
 #define sdr_sdstp7	0x4007
 
-/*----------------------------------------------------------------------------+
-| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
-+----------------------------------------------------------------------------*/
-#define CCR0_PRE		0x40000000
-#define CCR0_CRPE		0x08000000
-#define CCR0_DSTG		0x00200000
-#define CCR0_DAPUIB		0x00100000
-#define CCR0_DTB		0x00008000
-#define CCR0_GICBT		0x00004000
-#define CCR0_GDCBT		0x00002000
-#define CCR0_FLSTA		0x00000100
-#define CCR0_ICSLC_MASK		0x0000000C
-#define CCR0_ICSLT_MASK		0x00000003
-#define CCR1_TCS_MASK		0x00000080
-#define CCR1_TCS_INTCLK		0x00000000
-#define CCR1_TCS_EXTCLK		0x00000080
-#define MMUCR_SEOA		0x01000000
-#define MMUCR_U1TE		0x00400000
-#define MMUCR_U2SWOAE		0x00200000
-#define MMUCR_DULXE		0x00800000
-#define MMUCR_IULXE		0x00400000
-#define MMUCR_STS		0x00100000
-#define MMUCR_STID_MASK		0x000000FF
-
 #define SDR0_CFGADDR		0x00E
 #define SDR0_CFGDATA		0x00F
 
@@ -687,8 +684,8 @@
 #define SDRAM_CODT_CKSE_SINGLE_END		0x00000008
 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	0x00000004
 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	0x00000002
-#define SDRAM_CODT_IO_HIZ  			0x00000000
-#define SDRAM_CODT_IO_NMODE  			0x00000001
+#define SDRAM_CODT_IO_HIZ			0x00000000
+#define SDRAM_CODT_IO_NMODE			0x00000001
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Mode Register
@@ -956,7 +953,8 @@
 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -1025,7 +1023,7 @@
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR_USB2D0CR                 0x0320
+#define SDR0_USB2D0CR                 0x0320
 #define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
 #define   SDR0_USB2D0CR_USB2DEV_SELECTION      0x00000004    /* USB 2.0 Device Selection */
 #define   SDR0_USB2D0CR_EBC_SELECTION          0x00000000    /* EBC Selection */
@@ -1103,6 +1101,8 @@
 #define   SDR0_PFC2_SELECT_CONFIG_5            0xC0000000   /* 2xRTBI  using RGMII bridge */
 #define   SDR0_PFC2_SELECT_CONFIG_6            0x40000000   /* 2xSMII  using  ZMII bridge */
 
+#define SDR0_PFC4		0x4104
+
 /* USB2PHY0 Control Register */
 #define SDR0_USB2PHY0CR               0x4103
 #define   SDR0_USB2PHY0CR_UTMICN_MASK          0x00100000 /*  PHY UTMI interface connection */
@@ -1421,7 +1421,7 @@
 #define uicvr  uic0vr
 #define uicvcr uic0vcr
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
 /*----------------------------------------------------------------------------+
 | Clock / Power-on-reset DCR's.
 +----------------------------------------------------------------------------*/
@@ -1490,9 +1490,11 @@
 #define CPR0_OPBD_OPBDV0_DECODE(n)	((((((unsigned long)(n))>>24)-1)&0x03)+1)
 
 #define CPR0_PERD			0xE0
+#if !defined(CONFIG_440EPX)
 #define CPR0_PERD_PERDV0_MASK		0x03000000
 #define CPR0_PERD_PERDV0_ENCODE(n)	((((unsigned long)(n))&0x03)<<24)
 #define CPR0_PERD_PERDV0_DECODE(n)	((((((unsigned long)(n))>>24)-1)&0x03)+1)
+#endif
 
 #define CPR0_MALD			0x100
 #define CPR0_MALD_MALDV0_MASK		0x03000000
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 67759c7..ca241d2 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -22,6 +22,8 @@
 #ifndef	__PPC4XX_H__
 #define __PPC4XX_H__
 
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+#define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
 
 #if defined(CONFIG_440)
 #include <ppc440.h>
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 3e47e82..9f4029f 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -113,11 +113,11 @@
 
 #if  defined(CONFIG_5xx)
 /* Some special purpose registers */
-#define DER	149		/* Debug Enable Register	    	*/
-#define COUNTA	150		/* Breakpoint Counter	    	 	*/
-#define COUNTB	151		/* Breakpoint Counter	    	 	*/
-#define LCTRL1	156		/* Load/Store Support	    	 	*/
-#define LCTRL2	157		/* Load/Store Support	    	 	*/
+#define DER	149		/* Debug Enable Register		*/
+#define COUNTA	150		/* Breakpoint Counter			*/
+#define COUNTB	151		/* Breakpoint Counter			*/
+#define LCTRL1	156		/* Load/Store Support			*/
+#define LCTRL2	157		/* Load/Store Support			*/
 #define ICTRL	158		/* I-Bus Support Control Register	*/
 #define EID	81
 #endif	/* CONFIG_5xx */
@@ -217,7 +217,7 @@
  * We assume sprg3 has the physical address of the current
  * task's thread_struct.
  */
-#define EXCEPTION_PROLOG	\
+#define EXCEPTION_PROLOG(reg1, reg2)	\
 	mtspr	SPRG0,r20;	\
 	mtspr	SPRG1,r21;	\
 	mfcr	r20;		\
@@ -235,8 +235,10 @@
 	stw	r22,_CTR(r21);	\
 	mfspr	r20,XER;	\
 	stw	r20,_XER(r21);	\
-	mfspr	r22,SRR0;	\
-	mfspr	r23,SRR1;	\
+	mfspr	r20,DEAR;	\
+	stw	r20,_DAR(r21);	\
+	mfspr	r22,reg1;	\
+	mfspr	r23,reg2;	\
 	stw	r0,GPR0(r21);	\
 	stw	r1,GPR1(r21);	\
 	stw	r2,GPR2(r21);	\
@@ -249,41 +251,6 @@
  */
 
 /*
- * Critical exception entry code.  This is just like the other exception
- * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
- */
-#define CRITICAL_EXCEPTION_PROLOG       \
-	mtspr   SPRG0,r20;      \
-	mtspr   SPRG1,r21;      \
-	mfcr    r20;            \
-	subi    r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;  /* alloc exc. frame */\
-	stw     r20,_CCR(r21);          /* save registers */ \
-	stw     r22,GPR22(r21); \
-	stw     r23,GPR23(r21); \
-	mfspr   r20,SPRG0;      \
-	stw     r20,GPR20(r21); \
-	mfspr   r22,SPRG1;      \
-	stw     r22,GPR21(r21); \
-	mflr    r20;            \
-	stw     r20,_LINK(r21); \
-	mfctr   r22;            \
-	stw     r22,_CTR(r21);  \
-	mfspr   r20,XER;        \
-	stw     r20,_XER(r21);  \
-	mfspr   r22,990;        /* SRR2 */      \
-	mfspr   r23,991;        /* SRR3 */      \
-	stw     r0,GPR0(r21);   \
-	stw     r1,GPR1(r21);   \
-	stw     r2,GPR2(r21);   \
-	stw     r1,0(r21);      \
-	mr      r1,r21;                 /* set new kernel sp */ \
-	SAVE_4GPRS(3, r21);
-/*
- * Note: code which follows this uses cr0.eq (set if from kernel),
- * r21, r22 (SRR2), and r23 (SRR3).
- */
-
-/*
  * Exception vectors.
  *
  * The data words for `hdlr' and `int_return' are initialized with
@@ -293,30 +260,45 @@
 #define STD_EXCEPTION(n, label, hdlr)			\
 	. = n;						\
 label:							\
-	EXCEPTION_PROLOG;				\
+	EXCEPTION_PROLOG(SRR0, SRR1);			\
 	lwz	r3,GOT(transfer_to_handler);		\
 	mtlr	r3;					\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
 	li	r20,MSR_KERNEL;				\
 	rlwimi	r20,r23,0,25,25;			\
-	blrl	; 					\
+	blrl;						\
 .L_ ## label :						\
-	.long	hdlr - _start + EXC_OFF_SYS_RESET;	\
-	.long	int_return - _start + EXC_OFF_SYS_RESET
-
-
-#define CRIT_EXCEPTION(n, label, hdlr)                  \
-	. = n;                                          \
-label:                                                  \
-	CRITICAL_EXCEPTION_PROLOG;                      \
-	lwz     r3,GOT(transfer_to_handler);            \
-	mtlr    r3;                                     \
-	addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-	li      r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
-	rlwimi  r20,r23,0,25,25;                        \
-	blrl    ;                                       \
-.L_ ## label :                                          \
-	.long   hdlr - _start + EXC_OFF_SYS_RESET;      \
-	.long   crit_return - _start + EXC_OFF_SYS_RESET
+	.long	hdlr - _start + _START_OFFSET;		\
+	.long	int_return - _start + _START_OFFSET
+
+#define CRIT_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
+	lwz	r3,GOT(transfer_to_handler);			\
+	mtlr	r3;						\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	li	r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));	\
+	rlwimi	r20,r23,0,25,25;				\
+	blrl;							\
+.L_ ## label :							\
+	.long	hdlr - _start + _START_OFFSET;			\
+	.long	crit_return - _start + _START_OFFSET
+
+#ifdef CONFIG_440
+#define MCK_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
+	lwz	r3,GOT(transfer_to_handler);			\
+	mtlr	r3;						\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	li	r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));	\
+	rlwimi	r20,r23,0,25,25;				\
+	blrl;							\
+.L_ ## label :							\
+	.long	hdlr - _start + _START_OFFSET;			\
+	.long	mck_return - _start + _START_OFFSET
+#endif /* CONFIG_440  */
 
 #endif	/* __PPC_ASM_TMPL__ */
diff --git a/include/sata.h b/include/sata.h
new file mode 100644
index 0000000..165b471
--- /dev/null
+++ b/include/sata.h
@@ -0,0 +1,108 @@
+
+#if (DEBUG_SATA)
+#define PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+struct sata_ioports {
+	unsigned long cmd_addr;
+	unsigned long data_addr;
+	unsigned long error_addr;
+	unsigned long feature_addr;
+	unsigned long nsect_addr;
+	unsigned long lbal_addr;
+	unsigned long lbam_addr;
+	unsigned long lbah_addr;
+	unsigned long device_addr;
+	unsigned long status_addr;
+	unsigned long command_addr;
+	unsigned long altstatus_addr;
+	unsigned long ctl_addr;
+	unsigned long bmdma_addr;
+	unsigned long scr_addr;
+};
+
+struct sata_port {
+	unsigned char port_no;		/* primary=0, secondary=1	*/
+	struct sata_ioports ioaddr;	/* ATA cmd/ctl/dma reg blks	*/
+	unsigned char ctl_reg;
+	unsigned char last_ctl;
+	unsigned char port_state;	/* 1-port is available and	*/
+					/* 0-port is not available	*/
+	unsigned char dev_mask;
+};
+
+/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
+#ifdef SATA_DECL		/*SATA library specific declarations */
+#define ata_id_has_lba48(id)    ((id)[83] & (1 << 10))
+#define ata_id_has_lba(id)      ((id)[49] & (1 << 9))
+#define ata_id_has_dma(id)      ((id)[49] & (1 << 8))
+#define ata_id_u32(id,n)        \
+	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
+#define ata_id_u64(id,n)        \
+	(((u64) (id)[(n) + 3] << 48) | \
+	((u64) (id)[(n) + 2] << 32) | \
+	((u64) (id)[(n) + 1] << 16) | \
+	((u64) (id)[(n) + 0]) )
+#endif
+
+#ifdef SATA_DECL		/*SATA library specific declarations */
+static inline void
+ata_dump_id (u16 * id)
+{
+	PRINTF ("49==0x%04x  "
+		"53==0x%04x  "
+		"63==0x%04x  "
+		"64==0x%04x  "
+		"75==0x%04x  \n", id[49], id[53], id[63], id[64], id[75]);
+	PRINTF ("80==0x%04x  "
+		"81==0x%04x  "
+		"82==0x%04x  "
+		"83==0x%04x  "
+		"84==0x%04x  \n", id[80], id[81], id[82], id[83], id[84]);
+	PRINTF ("88==0x%04x  " "93==0x%04x\n", id[88], id[93]);
+}
+#endif
+
+#ifdef SATA_DECL		/*SATA library specific declarations */
+int sata_bus_softreset (int num);
+void sata_identify (int num, int dev);
+void sata_port (struct sata_ioports *ioport);
+void set_Feature_cmd (int num, int dev);
+int sata_devchk (struct sata_ioports *ioaddr, int dev);
+void dev_select (struct sata_ioports *ioaddr, int dev);
+u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
+u8 sata_chk_status (struct sata_ioports *ioaddr);
+ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
+ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
+void msleep (int count);
+#else
+extern int sata_bus_softreset (int num);
+extern void sata_identify (int num, int dev);
+extern void sata_port (struct sata_ioports *ioport);
+extern void set_Feature_cmd (int num, int dev);
+extern ulong sata_read (int device, ulong blknr,
+			lbaint_t blkcnt, void * buffer);
+extern ulong sata_write (int device, ulong blknr,
+			lbaint_t blkcnt, void * buffer);
+extern void msleep (int count);
+#endif
+
+/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
+
+#ifdef DRV_DECL			/*Driver specific declaration */
+int init_sata (void);
+#else
+extern int init_sata (void);
+#endif
+
+#ifdef DRV_DECL			/*Defines Driver Specific variables */
+struct sata_port port[CFG_SATA_MAXBUS];
+block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
+int curr_dev = -1;
+#else
+extern struct sata_port port[CFG_SATA_MAXBUS];
+extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
+extern int curr_dev;
+#endif
diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c
index b14d661..8354411 100644
--- a/lib_ppc/extable.c
+++ b/lib_ppc/extable.c
@@ -52,30 +52,27 @@ search_one_table(const struct exception_table_entry *first,
 		 const struct exception_table_entry *last,
 		 unsigned long value)
 {
-	while (first <= last) {
-		const struct exception_table_entry *mid;
-		long diff;
-
-		mid = (last - first) / 2 + first;
-		if ((ulong) mid > CFG_MONITOR_BASE) {
-			/* exception occurs in FLASH, before u-boot relocation.
-			 * No relocation offset is needed.
-			 */
-			diff = mid->insn - value;
+	long diff;
+	if ((ulong) first > CFG_MONITOR_BASE) {
+		/* exception occurs in FLASH, before u-boot relocation.
+		 * No relocation offset is needed.
+		 */
+		while (first <= last) {
+			diff = first->insn - value;
 			if (diff == 0)
-				return mid->fixup;
-		} else {
-			/* exception occurs in RAM, after u-boot relocation.
-			 * A relocation offset should be added.
-			 */
-			diff = (mid->insn + gd->reloc_off) - value;
+				return first->fixup;
+			first++;
+		}
+	} else {
+		/* exception occurs in RAM, after u-boot relocation.
+		 * A relocation offset should be added.
+		 */
+		while (first <= last) {
+			diff = (first->insn + gd->reloc_off) - value;
 			if (diff == 0)
-				return (mid->fixup + gd->reloc_off);
+				return (first->fixup + gd->reloc_off);
+			first++;
 		}
-		if (diff < 0)
-			first = mid + 1;
-		else
-			last = mid - 1;
 	}
 	return 0;
 }
diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile
index 0d6828a..926476f 100644
--- a/nand_spl/board/amcc/acadia/Makefile
+++ b/nand_spl/board/amcc/acadia/Makefile
@@ -30,7 +30,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o
+COBJS	= gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -39,7 +39,8 @@ LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
 
 nandobj	:= $(OBJTREE)/nand_spl/
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
+	$(nandobj)System.map
 
 all:	$(obj).depend $(ALL)
 
@@ -54,6 +55,11 @@ $(nandobj)u-boot-spl:	$(OBJS)
 		-Map $(nandobj)u-boot-spl.map \
 		-o $(nandobj)u-boot-spl
 
+$(nandobj)System.map:	$(nandobj)u-boot-spl
+		@$(NM) $< | \
+		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+		sort > $(nandobj)System.map
+
 # create symbolic links for common files
 
 # from cpu directory
@@ -78,6 +84,10 @@ $(obj)memory.c:
 	@rm -f $(obj)memory.c
 	ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
 
+$(obj)pll.c:
+	@rm -f $(obj)pll.c
+	ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c
+
 # from nand_spl directory
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk
index 55069b4..3b140fa 100644
--- a/nand_spl/board/amcc/acadia/config.mk
+++ b/nand_spl/board/amcc/acadia/config.mk
@@ -32,11 +32,11 @@
 # We will copy this SPL into internal SRAM in start.S. So we set
 # TEXT_BASE to starting address in internal SRAM here.
 #
-TEXT_BASE = 0xF8003000
+TEXT_BASE = 0xf8004000
 
 # PAD_TO used to generate a 16kByte binary needed for the combined image
 # -> PAD_TO = TEXT_BASE + 0x4000
-PAD_TO	= 0xF8007000
+PAD_TO	= 0xf8008000
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds
index 018def1..a07a773 100644
--- a/nand_spl/board/amcc/acadia/u-boot.lds
+++ b/nand_spl/board/amcc/acadia/u-boot.lds
@@ -24,7 +24,7 @@
 OUTPUT_ARCH(powerpc:common)
 SECTIONS
 {
-  .resetvec 0xF8003FFC :
+  .resetvec 0xf8004ffc :
   {
     *(.resetvec)
   } = 0xffff
diff --git a/net/eth.c b/net/eth.c
index 0fc2211..ab56dcf 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -173,28 +173,20 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_SK98)
 	skge_initialize(bis);
 #endif
-#if defined(CONFIG_MPC85XX_TSEC1)
-	tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME);
-#elif defined(CONFIG_MPC83XX_TSEC1)
-	tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME);
+#if defined(CONFIG_TSEC1)
+	tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
 #endif
-#if defined(CONFIG_MPC85XX_TSEC2)
-	tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME);
-#elif defined(CONFIG_MPC83XX_TSEC2)
-	tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME);
+#if defined(CONFIG_TSEC2)
+	tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
 #endif
 #if defined(CONFIG_MPC85XX_FEC)
 	tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
 #else
-#    if defined(CONFIG_MPC85XX_TSEC3)
-	tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME);
-#    elif defined(CONFIG_MPC83XX_TSEC3)
-	tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME);
+#    if defined(CONFIG_TSEC3)
+	tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
 #    endif
-#    if defined(CONFIG_MPC85XX_TSEC4)
-	tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME);
-#    elif defined(CONFIG_MPC83XX_TSEC4)
-	tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
+#    if defined(CONFIG_TSEC4)
+	tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
 #    endif
 #endif
 #if defined(CONFIG_UEC_ETH1)
@@ -203,21 +195,6 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_UEC_ETH2)
 	uec_initialize(1);
 #endif
-#if defined(CONFIG_MPC86XX_TSEC1)
-       tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME);
-#endif
-
-#if defined(CONFIG_MPC86XX_TSEC2)
-       tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME);
-#endif
-
-#if defined(CONFIG_MPC86XX_TSEC3)
-       tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME);
-#endif
-
-#if defined(CONFIG_MPC86XX_TSEC4)
-       tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME);
-#endif
 
 #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 	fec_initialize(bis);
diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile
index 9dd3f0f..f871cba 100644
--- a/post/cpu/mpc8xx/Makefile
+++ b/post/cpu/mpc8xx/Makefile
@@ -24,6 +24,6 @@
 LIB	= libpostmpc8xx.a
 
 AOBJS	= cache_8xx.o
-COBJS	= ether.o spr.o uart.o usb.o watchdog.o
+COBJS	= cache.o ether.o spr.o uart.o usb.o watchdog.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/drivers/cache.c b/post/cpu/mpc8xx/cache.c
index 501465c..501465c 100644
--- a/post/drivers/cache.c
+++ b/post/cpu/mpc8xx/cache.c
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
new file mode 100644
index 0000000..f1034da
--- /dev/null
+++ b/post/cpu/ppc4xx/Makefile
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LIB	= libpostppc4xx.a
+
+AOBJS   = cache_4xx.o
+COBJS	= cache.o ether.o fpu.o spr.o uart.o watchdog.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
new file mode 100644
index 0000000..e1f989e
--- /dev/null
+++ b/post/cpu/ppc4xx/cache.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Cache test
+ *
+ * This test verifies the CPU data and instruction cache using
+ * several test scenarios.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_CACHE
+
+#include <asm/mmu.h>
+#include <watchdog.h>
+
+#define CACHE_POST_SIZE	1024
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+
+int cache_post_test1 (int tlb, void *p, int size);
+int cache_post_test2 (int tlb, void *p, int size);
+int cache_post_test3 (int tlb, void *p, int size);
+int cache_post_test4 (int tlb, void *p, int size);
+int cache_post_test5 (int tlb, void *p, int size);
+int cache_post_test6 (int tlb, void *p, int size);
+
+static int tlb = -1;		/* index to the victim TLB entry */
+
+static unsigned char testarea[CACHE_POST_SIZE]
+__attribute__((__aligned__(CACHE_POST_SIZE)));
+
+int cache_post_test (int flags)
+{
+	void* virt = (void*)CFG_POST_CACHE_ADDR;
+	int ints, i, res = 0;
+	u32 word0;
+
+	if (tlb < 0) {
+		/*
+		 * Allocate a new TLB entry, since we are going to modify
+		 * the write-through and caching inhibited storage attributes.
+		 */
+		program_tlb((u32)testarea, (u32)virt,
+			    CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
+
+		/* Find the TLB entry */
+		for (i = 0;; i++) {
+			if (i >= PPC4XX_TLB_SIZE) {
+				printf ("Failed to program tlb entry\n");
+				return -1;
+			}
+			word0 = mftlb1(i);
+			if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
+				tlb = i;
+				break;
+			}
+		}
+	}
+	ints = disable_interrupts ();
+
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
+
+	if (ints)
+		enable_interrupts ();
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_CACHE */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S
new file mode 100644
index 0000000..785b8d6
--- /dev/null
+++ b/post/cpu/ppc4xx/cache_4xx.S
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#if CONFIG_POST & CFG_POST_CACHE
+
+	.text
+
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+	tlbre	r0, r3, 0x0002
+	ori	r0, r0, TLB_WORD2_I_ENABLE@l
+	tlbwe	r0, r3, 0x0002
+	sync
+	isync
+	blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+	tlbre	r0, r3, 0x0002
+	ori	r0, r0, TLB_WORD2_W_ENABLE@l
+	andi.	r0, r0, ~TLB_WORD2_I_ENABLE@l
+	tlbwe	r0, r3, 0x0002
+	sync
+	isync
+	blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+	tlbre	r0, r3, 0x0002
+	andi.	r0, r0, ~TLB_WORD2_W_ENABLE@l
+	andi.	r0, r0, ~TLB_WORD2_I_ENABLE@l
+	tlbwe	r0, r3, 0x0002
+	sync
+	isync
+	blr
+
+/* void cache_post_dinvalidate (void *p, int size)
+ */
+cache_post_dinvalidate:
+	dcbi	r0, r3
+	addi	r3, r3, CFG_CACHELINE_SIZE
+	subic.	r4, r4, CFG_CACHELINE_SIZE
+	bgt	cache_post_dinvalidate
+	sync
+	blr
+
+/* void cache_post_dstore (void *p, int size)
+ */
+cache_post_dstore:
+	dcbst	r0, r3
+	addi	r3, r3, CFG_CACHELINE_SIZE
+	subic.	r4, r4, CFG_CACHELINE_SIZE
+	bgt	cache_post_dstore
+	sync
+	blr
+
+/* void cache_post_dtouch (void *p, int size)
+ */
+cache_post_dtouch:
+	dcbt	r0, r3
+	addi	r3, r3, CFG_CACHELINE_SIZE
+	subic.	r4, r4, CFG_CACHELINE_SIZE
+	bgt	cache_post_dtouch
+	sync
+	blr
+
+/* void cache_post_iinvalidate (void)
+ */
+cache_post_iinvalidate:
+	iccci	r0, r0
+	sync
+	blr
+
+/* void cache_post_memset (void *p, int val, int size)
+ */
+cache_post_memset:
+	mtctr	r5
+1:
+	stb	r4, 0(r3)
+	addi	r3, r3, 1
+	bdnz	1b
+	blr
+
+/* int cache_post_check (void *p, int size)
+ */
+cache_post_check:
+	mtctr	r4
+1:
+	lbz	r0, 0(r3)
+	addi	r3, r3, 1
+	cmpwi	r0, 0xff
+	bne	2f
+	bdnz	1b
+	li	r3, 0
+	blr
+2:
+	li	r3, -1
+	blr
+
+#define CACHE_POST_DISABLE()		\
+	mr	r3, r10;		\
+	bl	cache_post_disable
+
+#define CACHE_POST_WT()			\
+	mr	r3, r10;		\
+	bl	cache_post_wt
+
+#define CACHE_POST_WB()			\
+	mr	r3, r10;		\
+	bl	cache_post_wb
+
+#define CACHE_POST_DINVALIDATE()	\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dinvalidate
+
+#define CACHE_POST_DFLUSH()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dflush
+
+#define CACHE_POST_DSTORE()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dstore
+
+#define CACHE_POST_DTOUCH()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dtouch
+
+#define CACHE_POST_IINVALIDATE()	\
+	bl	cache_post_iinvalidate
+
+#define CACHE_POST_MEMSET(val)		\
+	mr	r3, r11;		\
+	li	r4, val;		\
+	mr	r5, r12;		\
+	bl	cache_post_memset
+
+#define CACHE_POST_CHECK()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_check;	\
+	mr	r13, r3
+
+/*
+ * Write and read 0xff pattern with caching enabled.
+ */
+	.global cache_post_test1
+cache_post_test1:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WB()
+	CACHE_POST_DINVALIDATE()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Write zeroes with caching enabled.
+ * Write 0xff pattern with caching disabled.
+ * Read 0xff pattern with caching enabled.
+ */
+	.global cache_post_test2
+cache_post_test2:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WB()
+	CACHE_POST_DINVALIDATE()
+
+	/* Write the zero pattern to the test area */
+	CACHE_POST_MEMSET(0)
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	CACHE_POST_WB()
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Write-through mode test.
+ * Write zeroes, store the cache, write 0xff pattern.
+ * Invalidate the cache.
+ * Check that 0xff pattern is read.
+ */
+	.global cache_post_test3
+cache_post_test3:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WT()
+	CACHE_POST_DINVALIDATE()
+
+	/* Cache the test area */
+	CACHE_POST_DTOUCH()
+
+	/* Write the zero pattern to the test area */
+	CACHE_POST_MEMSET(0)
+
+	CACHE_POST_DSTORE()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Write-back mode test.
+ * Write 0xff pattern, store the cache, write zeroes.
+ * Invalidate the cache.
+ * Check that 0xff pattern is read.
+ */
+	.global cache_post_test4
+cache_post_test4:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WB()
+	CACHE_POST_DINVALIDATE()
+
+	/* Cache the test area */
+	CACHE_POST_DTOUCH()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	CACHE_POST_DSTORE()
+
+	/* Write the zero pattern to the test area */
+	CACHE_POST_MEMSET(0)
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Load the test instructions into the instruction cache.
+ * Replace the test instructions.
+ * Check that the original instructions are executed.
+ */
+	.global cache_post_test5
+cache_post_test5:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WT()
+	CACHE_POST_IINVALIDATE()
+
+	/* Compute r13 = cache_post_test_inst */
+	bl	cache_post_test5_reloc
+cache_post_test5_reloc:
+	mflr	r13
+	lis	r0, (cache_post_test_inst - cache_post_test5_reloc)@h
+	ori	r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
+	add	r13, r13, r0
+
+	/* Copy the test instructions to the test area */
+	lwz	r0, 0(r13)
+	stw	r0, 0(r11)
+	lwz	r0, 8(r13)
+	stw	r0, 4(r11)
+	sync
+
+	/* Invalidate the cache line */
+	icbi	r0, r11
+	sync
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+
+	/* Replace the test instruction */
+	lwz	r0, 4(r13)
+	stw	r0, 0(r11)
+	sync
+
+	/* Do not invalidate the cache line */
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+	mr	r13, r3
+
+	CACHE_POST_IINVALIDATE()
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Load the test instructions into the instruction cache.
+ * Replace the test instructions and invalidate the cache.
+ * Check that the replaced instructions are executed.
+ */
+	.global cache_post_test6
+cache_post_test6:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WT()
+	CACHE_POST_IINVALIDATE()
+
+	/* Compute r13 = cache_post_test_inst */
+	bl	cache_post_test6_reloc
+cache_post_test6_reloc:
+	mflr	r13
+	lis	r0, (cache_post_test_inst - cache_post_test6_reloc)@h
+	ori	r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
+	add	r13, r13, r0
+
+	/* Copy the test instructions to the test area */
+	lwz	r0, 4(r13)
+	stw	r0, 0(r11)
+	lwz	r0, 8(r13)
+	stw	r0, 4(r11)
+	sync
+
+	/* Invalidate the cache line */
+	icbi	r0, r11
+	sync
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+
+	/* Replace the test instruction */
+	lwz	r0, 0(r13)
+	stw	r0, 0(r11)
+	sync
+
+	/* Invalidate the cache line */
+	icbi	r0, r11
+	sync
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+	mr	r13, r3
+
+	CACHE_POST_IINVALIDATE()
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/* Test instructions.
+ */	
+cache_post_test_inst:
+	li	r3, 0
+	li	r3, -1
+	blr
+
+#endif /* CONFIG_POST & CFG_POST_CACHE */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
new file mode 100644
index 0000000..391c815
--- /dev/null
+++ b/post/cpu/ppc4xx/ether.c
@@ -0,0 +1,395 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Ethernet test
+ *
+ * The Ethernet Media Access Controllers (EMAC) are tested in the
+ * internal loopback mode.
+ * The controllers are configured accordingly and several packets
+ * are transmitted. The configurable test parameters are:
+ *   MIN_PACKET_LENGTH - minimum size of packet to transmit
+ *   MAX_PACKET_LENGTH - maximum size of packet to transmit
+ *   TEST_NUM - number of tests
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_ETHER
+
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <405_mal.h>
+#include <ppc4xx_enet.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
+#endif
+
+#define MIN_PACKET_LENGTH	64
+#define MAX_PACKET_LENGTH	256
+#define TEST_NUM		1
+
+static volatile mal_desc_t tx __cacheline_aligned;
+static volatile mal_desc_t rx __cacheline_aligned;
+static char *tx_buf;
+static char *rx_buf;
+
+static void ether_post_init (int devnum, int hw_addr)
+{
+	int i;
+	unsigned mode_reg;
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	sys_info_t sysinfo;
+#endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+	unsigned long mfr;
+#endif
+
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	/* Need to get the OPB frequency so we can access the PHY */
+	get_sys_info (&sysinfo);
+#endif
+
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	/* provide clocks for EMAC internal loopback  */
+	mfsdr (sdr_mfr, mfr);
+	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
+	mtsdr (sdr_mfr, mfr);
+	sync ();
+#endif
+	/* reset emac */
+	out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+	sync ();
+
+	for (i = 0;; i++) {
+		if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
+			break;
+		if (i >= 1000) {
+			printf ("Timeout resetting EMAC\n");
+			break;
+		}
+		udelay (1000);
+	}
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	/* Whack the M1 register */
+	mode_reg = 0x0;
+	if (sysinfo.freqOPB <= 50000000);
+	else if (sysinfo.freqOPB <= 66666667)
+		mode_reg |= EMAC_M1_OBCI_66;
+	else if (sysinfo.freqOPB <= 83333333)
+		mode_reg |= EMAC_M1_OBCI_83;
+	else if (sysinfo.freqOPB <= 100000000)
+		mode_reg |= EMAC_M1_OBCI_100;
+	else
+		mode_reg |= EMAC_M1_OBCI_GT100;
+
+	out32 (EMAC_M1 + hw_addr, mode_reg);
+
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
+
+	/* set the Mal configuration reg */
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+	       MAL_CR_PLBLT_DEFAULT | 0x00330000);
+#else
+	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
+	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
+	if (get_pvr() == PVR_440GP_RB) {
+		mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
+	}
+#endif
+	/* setup buffer descriptors */
+	tx.ctrl = MAL_TX_CTRL_WRAP;
+	tx.data_len = 0;
+	tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
+
+	rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
+	rx.data_len = 0;
+	rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
+
+	switch (devnum) {
+	case 1:
+		/* setup MAL tx & rx channel pointers */
+#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
+		mtdcr (maltxctp2r, &tx);
+#else
+		mtdcr (maltxctp1r, &tx);
+#endif
+#if defined(CONFIG_440)
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+#endif
+		mtdcr (malrxctp1r, &rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
+		break;
+	case 0:
+	default:
+		/* setup MAL tx & rx channel pointers */
+#if defined(CONFIG_440)
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+#endif
+		mtdcr (maltxctp0r, &tx);
+		mtdcr (malrxctp0r, &rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
+		break;
+	}
+
+	/* Enable MAL transmit and receive channels */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
+#else
+	mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
+#endif
+	mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
+
+	/* set internal loopback mode */
+	out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
+	       EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+	       EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+	       in32 (EMAC_M1));
+
+	/* set transmit enable & receive enable */
+	out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+
+	/* enable broadcast address */
+	out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
+
+	/* set transmit request threshold register */
+	out32 (EMAC_TRTR + hw_addr, 0x18000000);	/* 256 byte threshold */
+
+	/* set receive	low/high water mark register */
+#if defined(CONFIG_440)
+	/* 440s has a 64 byte burst length */
+	out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
+#else
+	/* 405s have a 16 byte burst length */
+	out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
+#endif /* defined(CONFIG_440) */
+	out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
+
+	/* Set fifo limit entry in tx mode 0 */
+	out32 (EMAC_TXM0 + hw_addr, 0x00000003);
+	/* Frame gap set */
+	out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
+	sync ();
+}
+
+static void ether_post_halt (int devnum, int hw_addr)
+{
+	int i = 0;
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	unsigned long mfr;
+#endif
+
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
+#else
+	mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
+#endif
+	mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
+
+	/* wait for reset */
+	while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
+		if (i++ >= 1000)
+			break;
+		udelay (1000);
+	}
+	/* emac reset */
+	out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	/* remove clocks for EMAC internal loopback  */
+	mfsdr (sdr_mfr, mfr);
+	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
+	mtsdr (sdr_mfr, mfr);
+#endif
+}
+
+static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
+{
+	int i = 0;
+
+	while (tx.ctrl & MAL_TX_CTRL_READY) {
+		if (i++ > 100) {
+			printf ("TX timeout\n");
+			return;
+		}
+		udelay (1000);
+	}
+	tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
+		EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
+	tx.data_len = length;
+	memcpy (tx.data_ptr, packet, length);
+	sync ();
+
+	out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
+	sync ();
+}
+
+static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
+{
+	int length;
+	int i = 0;
+
+	while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
+		if (i++ > 100) {
+			printf ("RX timeout\n");
+			return 0;
+		}
+		udelay (1000);
+	}
+	length = rx.data_len - 4;
+	if (length <= max_length)
+		memcpy(packet, rx.data_ptr, length);
+	sync ();
+
+	rx.ctrl |= MAL_RX_CTRL_EMPTY;
+	sync ();
+
+	return length;
+}
+
+  /*
+   * Test routines
+   */
+
+static void packet_fill (char *packet, int length)
+{
+	char c = (char) length;
+	int i;
+
+	/* set up ethernet header */
+	memset (packet, 0xff, 14);
+
+	for (i = 14; i < length; i++) {
+		packet[i] = c++;
+	}
+}
+
+static int packet_check (char *packet, int length)
+{
+	char c = (char) length;
+	int i;
+
+	for (i = 14; i < length; i++) {
+		if (packet[i] != c++)
+			return -1;
+	}
+
+	return 0;
+}
+
+static int test_ctlr (int devnum, int hw_addr)
+{
+	int res = -1;
+	char packet_send[MAX_PACKET_LENGTH];
+	char packet_recv[MAX_PACKET_LENGTH];
+	int length;
+	int i;
+	int l;
+
+	ether_post_init (devnum, hw_addr);
+
+	for (i = 0; i < TEST_NUM; i++) {
+		for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
+			packet_fill (packet_send, l);
+
+			ether_post_send (devnum, hw_addr, packet_send, l);
+
+			length = ether_post_recv (devnum, hw_addr, packet_recv,
+						  sizeof (packet_recv));
+
+			if (length != l || packet_check (packet_recv, length) < 0) {
+				goto Done;
+			}
+		}
+	}
+
+	res = 0;
+
+Done:
+
+	ether_post_halt (devnum, hw_addr);
+
+	if (res != 0) {
+		post_log ("EMAC%d test failed\n", devnum);
+	}
+
+	return res;
+}
+
+int ether_post_test (int flags)
+{
+	int res = 0;
+
+	/* Allocate tx & rx packet buffers */
+	tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
+	rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
+
+	if (!tx_buf || !rx_buf) {
+		printf ("Failed to allocate packet buffers\n");
+		res = -1;
+		goto out_free;
+	}
+
+	/* EMAC0 */
+	if (test_ctlr (0, 0))
+		res = -1;
+
+	/* EMAC1 */
+	if (test_ctlr (1, 0x100))
+		res = -1;
+
+out_free:
+	free (tx_buf);
+	free (rx_buf);
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_ETHER */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
new file mode 100644
index 0000000..c2eb4a9
--- /dev/null
+++ b/post/cpu/ppc4xx/fpu.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Sergei Poselenov <sposelenov@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_POST
+#if defined(CONFIG_440EP) || \
+    defined(CONFIG_440EPX)
+
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+int fpu_status(void)
+{
+	if (mfspr(ccr0) & CCR0_DAPUIB)
+		return 0; /* Disabled */
+	else 
+		return 1; /* Enabled */
+}
+
+
+void fpu_disable(void)
+{
+	mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
+	mtmsr(mfmsr() & ~MSR_FP);
+}
+
+
+void fpu_enable(void)
+{
+	mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
+	mtmsr(mfmsr() | MSR_FP);
+}
+
+#endif
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
new file mode 100644
index 0000000..be5a701
--- /dev/null
+++ b/post/cpu/ppc4xx/spr.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * SPR test
+ *
+ * The test checks the contents of Special Purpose Registers (SPR) listed
+ * in the spr_test_list array below.
+ * Each SPR value is read using mfspr instruction, some bits are masked
+ * according to the table and the resulting value is compared to the
+ * corresponding table value.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_SPR
+
+#include <asm/processor.h>
+
+static struct
+{
+    int number;
+    char * name;
+    unsigned long mask;
+    unsigned long value;
+} spr_test_list [] = {
+	/* Standard Special-Purpose Registers */
+
+	{0x001,	"XER",		0x00000000,	0x00000000},
+	{0x008,	"LR",		0x00000000,	0x00000000},
+	{0x009,	"CTR",		0x00000000,	0x00000000},
+	{0x016,	"DEC",		0x00000000,	0x00000000},
+	{0x01a,	"SRR0",		0x00000000,	0x00000000},
+	{0x01b,	"SRR1",		0x00000000,	0x00000000},
+	{0x110,	"SPRG0",	0x00000000,	0x00000000},
+	{0x111,	"SPRG1",	0x00000000,	0x00000000},
+	{0x112,	"SPRG2",	0x00000000,	0x00000000},
+	{0x113,	"SPRG3",	0x00000000,	0x00000000},
+	{0x11f,	"PVR",		0x00000000,	0x00000000},
+
+	/* Additional Special-Purpose Registers.
+	 * The values must match the initialization 
+	 * values from cpu/ppc4xx/start.S
+	 */
+	{0x30,	"PID",		0x00000000,	0x00000000},
+	{0x3a,	"CSRR0",	0x00000000,	0x00000000},
+	{0x3b,	"CSRR1",	0x00000000,	0x00000000},
+	{0x3d,	"DEAR",		0x00000000,	0x00000000},
+	{0x3e,	"ESR",		0x00000000,	0x00000000},
+	{0x3f,	"IVPR",		0xffff0000,	0x00000000},
+	{0x100,	"USPRG0",	0x00000000,	0x00000000},
+	{0x104,	"SPRG4",	0x00000000,	0x00000000},
+	{0x105,	"SPRG5",	0x00000000,	0x00000000},
+	{0x106,	"SPRG6",	0x00000000,	0x00000000},
+	{0x107,	"SPRG7",	0x00000000,	0x00000000},
+	{0x10c,	"TBL",		0x00000000,	0x00000000},
+	{0x10d,	"TBU",		0x00000000,	0x00000000},
+	{0x11e,	"PIR",		0x0000000f,	0x00000000},
+	{0x130,	"DBSR",		0x00000000,	0x00000000},
+	{0x134,	"DBCR0",	0x00000000,	0x00000000},
+	{0x135,	"DBCR1",	0x00000000,	0x00000000},
+	{0x136,	"DBCR2",	0x00000000,	0x00000000},
+	{0x138,	"IAC1",		0x00000000,	0x00000000},
+	{0x139,	"IAC2",		0x00000000,	0x00000000},
+	{0x13a,	"IAC3",		0x00000000,	0x00000000},
+	{0x13b,	"IAC4",		0x00000000,	0x00000000},
+	{0x13c,	"DAC1",		0x00000000,	0x00000000},
+	{0x13d,	"DAC2",		0x00000000,	0x00000000},
+	{0x13e,	"DVC1",		0x00000000,	0x00000000},
+	{0x13f,	"DVC2",		0x00000000,	0x00000000},
+	{0x150,	"TSR",		0x00000000,	0x00000000},
+	{0x154,	"TCR",		0x00000000,	0x00000000},
+	{0x190,	"IVOR0",	0x0000fff0,	0x00000100},
+	{0x191,	"IVOR1",	0x0000fff0,	0x00000200},
+	{0x192,	"IVOR2",	0x0000fff0,	0x00000300},
+	{0x193,	"IVOR3",	0x0000fff0,	0x00000400},
+	{0x194,	"IVOR4",	0x0000fff0,	0x00000500},
+	{0x195,	"IVOR5",	0x0000fff0,	0x00000600},
+	{0x196,	"IVOR6",	0x0000fff0,	0x00000700},
+	{0x197,	"IVOR7",	0x0000fff0,	0x00000800},
+	{0x198,	"IVOR8",	0x0000fff0,	0x00000c00},
+	{0x199,	"IVOR9",	0x00000000,	0x00000000},
+	{0x19a,	"IVOR10",	0x0000fff0,	0x00000900},
+	{0x19b,	"IVOR11",	0x00000000,	0x00000000},
+	{0x19c,	"IVOR12",	0x00000000,	0x00000000},
+	{0x19d,	"IVOR13",	0x0000fff0,	0x00001300},
+	{0x19e,	"IVOR14",	0x0000fff0,	0x00001400},
+	{0x19f,	"IVOR15",	0x0000fff0,	0x00002000},
+	{0x23a,	"MCSRR0",	0x00000000,	0x00000000},
+	{0x23b,	"MCSRR1",	0x00000000,	0x00000000},
+	{0x23c,	"MCSR",		0x00000000,	0x00000000},
+	{0x370,	"INV0",		0x00000000,	0x00000000},
+	{0x371,	"INV1",		0x00000000,	0x00000000},
+	{0x372,	"INV2",		0x00000000,	0x00000000},
+	{0x373,	"INV3",		0x00000000,	0x00000000},
+	{0x374,	"ITV0",		0x00000000,	0x00000000},
+	{0x375,	"ITV1",		0x00000000,	0x00000000},
+	{0x376,	"ITV2",		0x00000000,	0x00000000},
+	{0x377,	"ITV3",		0x00000000,	0x00000000},
+	{0x378,	"CCR1",		0x00000000,	0x00000000},
+	{0x390,	"DNV0",		0x00000000,	0x00000000},
+	{0x391,	"DNV1",		0x00000000,	0x00000000},
+	{0x392,	"DNV2",		0x00000000,	0x00000000},
+	{0x393,	"DNV3",		0x00000000,	0x00000000},
+	{0x394,	"DTV0",		0x00000000,	0x00000000},
+	{0x395,	"DTV1",		0x00000000,	0x00000000},
+	{0x396,	"DTV2",		0x00000000,	0x00000000},
+	{0x397,	"DTV3",		0x00000000,	0x00000000},
+	{0x398,	"DVLIM",	0x0fc1f83f,	0x0001f800},
+	{0x399,	"IVLIM",	0x0fc1f83f,	0x0001f800},
+	{0x39b,	"RSTCFG",	0x00000000,	0x00000000},
+	{0x39c,	"DCDBTRL",	0x00000000,	0x00000000},
+	{0x39d,	"DCDBTRH",	0x00000000,	0x00000000},
+	{0x39e,	"ICDBTRL",	0x00000000,	0x00000000},
+	{0x39f,	"ICDBTRH",	0x00000000,	0x00000000},
+	{0x3b2,	"MMUCR",	0x00000000,	0x00000000},
+	{0x3b3,	"CCR0",		0x00000000,	0x00000000},
+	{0x3d3,	"ICDBDR",	0x00000000,	0x00000000},
+	{0x3f3,	"DBDR",		0x00000000,	0x00000000},
+};
+
+static int spr_test_list_size =
+		sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+
+int spr_post_test (int flags)
+{
+	int ret = 0;
+	int i;
+
+	unsigned long code[] = {
+		0x7c6002a6,				/* mfspr r3,SPR */
+		0x4e800020				/* blr          */
+	};
+	unsigned long (*get_spr) (void) = (void *) code;
+
+	for (i = 0; i < spr_test_list_size; i++) {
+		int num = spr_test_list[i].number;
+
+		/* mfspr r3,num */
+		code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
+
+		asm volatile ("isync");
+
+		if ((get_spr () & spr_test_list[i].mask) !=
+			(spr_test_list[i].value & spr_test_list[i].mask)) {
+			post_log ("The value of %s special register "
+				  "is incorrect: 0x%08X\n",
+					spr_test_list[i].name, get_spr ());
+			ret = -1;
+		}
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_POST & CFG_POST_SPR */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c
new file mode 100644
index 0000000..b047d42
--- /dev/null
+++ b/post/cpu/ppc4xx/uart.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * UART test
+ *
+ * The controllers are configured to loopback mode and several
+ * characters are transmitted.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_UART
+
+#include <asm/processor.h>
+#include <serial.h>
+
+#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
+#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000500
+#define UART3_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#define UDIV_SUBTRACT	0
+#define UART0_SDR	sdr_uart0
+#define UART1_SDR	sdr_uart1
+#define UART2_SDR	sdr_uart2
+#define UART3_SDR	sdr_uart3
+#define MFREG(a, d)	mfsdr(a, d)
+#define MTREG(a, d)	mtsdr(a, d)
+
+#define UART_RBR    0x00
+#define UART_THR    0x00
+#define UART_IER    0x01
+#define UART_IIR    0x02
+#define UART_FCR    0x02
+#define UART_LCR    0x03
+#define UART_MCR    0x04
+#define UART_LSR    0x05
+#define UART_MSR    0x06
+#define UART_SCR    0x07
+#define UART_DLL    0x00
+#define UART_DLM    0x01
+
+/*
+  Line Status Register.
+*/
+#define asyncLSRDataReady1            0x01
+#define asyncLSROverrunError1         0x02
+#define asyncLSRParityError1          0x04
+#define asyncLSRFramingError1         0x08
+#define asyncLSRBreakInterrupt1       0x10
+#define asyncLSRTxHoldEmpty1          0x20
+#define asyncLSRTxShiftEmpty1         0x40
+#define asyncLSRRxFifoError1          0x80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int uart_post_init (unsigned long dev_base)
+{
+	unsigned long reg;
+	unsigned long udiv;
+	unsigned short bdiv;
+	volatile char val;
+#ifdef CFG_EXT_SERIAL_CLOCK
+	unsigned long tmp;
+#endif
+	int i;
+
+	for (i = 0; i < 3500; i++) {
+		if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
+			break;
+		udelay (100);
+	}
+	MFREG(UART0_SDR, reg);
+	reg &= ~CR0_MASK;
+
+#ifdef CFG_EXT_SERIAL_CLOCK
+	reg |= CR0_EXTCLK_ENA;
+	udiv = 1;
+	tmp  = gd->baudrate * 16;
+	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+#else
+	/* For 440, the cpu clock is on divider chain A, UART on divider
+	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
+	 * values that are subject to the 1/2 opb clock constraint
+	 */
+	serial_divs (gd->baudrate, &udiv, &bdiv);
+#endif
+
+	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
+
+	/*
+	 * Configure input clock to baudrate generator for all
+	 * available serial ports here
+	 */
+	MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+	MTREG(UART1_SDR, reg);
+#endif
+#if defined(UART2_SDR)
+	MTREG(UART2_SDR, reg);
+#endif
+#if defined(UART3_SDR)
+	MTREG(UART3_SDR, reg);
+#endif
+
+	out8(dev_base + UART_LCR, 0x80);	/* set DLAB bit */
+	out8(dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8(dev_base + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
+	out8(dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8(dev_base + UART_FCR, 0x00);	/* disable FIFO */
+	out8(dev_base + UART_MCR, 0x10);	/* enable loopback mode */
+	val = in8(dev_base + UART_LSR);		/* clear line status */
+	val = in8(dev_base + UART_RBR);		/* read receive buffer */
+	out8(dev_base + UART_SCR, 0x00);	/* set scratchpad */
+	out8(dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
+
+	return 0;
+}
+
+static void uart_post_putc (unsigned long dev_base, char c)
+{
+	int i;
+
+	out8 (dev_base + UART_THR, c);	/* put character out */
+
+	/* Wait for transfer completion */
+	for (i = 0; i < 3500; i++) {
+		if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
+			break;
+		udelay (100);
+	}
+}
+
+static int uart_post_getc (unsigned long dev_base)
+{
+	int i;
+
+	/* Wait for character available */
+	for (i = 0; i < 3500; i++) {
+		if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
+			break;
+		udelay (100);
+	}
+	return 0xff & in8 (dev_base + UART_RBR);
+}
+
+static int test_ctlr (unsigned long dev_base, int index)
+{
+	int res = -1;
+	char test_str[] = "*** UART Test String ***\r\n";
+	int i;
+
+	uart_post_init (dev_base);
+
+	for (i = 0; i < sizeof (test_str) - 1; i++) {
+		uart_post_putc (dev_base, test_str[i]);
+		if (uart_post_getc (dev_base) != test_str[i])
+			goto done;
+	}
+	res = 0;
+done:
+	if (res)
+		post_log ("uart%d test failed\n", index);
+
+	return res;
+}
+
+int uart_post_test (int flags)
+{
+	int i, res = 0;
+	static unsigned long base[] = {
+		UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
+	};
+
+	for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
+		if (test_ctlr (base[i], i))
+			res = -1;
+	}
+	serial_reinit_all ();
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_UART */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c
new file mode 100644
index 0000000..bd4f4c9
--- /dev/null
+++ b/post/cpu/ppc4xx/watchdog.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Watchdog test
+ *
+ * The test verifies the watchdog timer operation.
+ * On the first iteration, the test routine disables interrupts and
+ * makes a 10-second delay. If the system does not reboot during this delay,
+ * the watchdog timer is not operational and the test fails. If the system
+ * reboots, on the second iteration the test routine reports a success.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_WATCHDOG
+
+#include <watchdog.h>
+
+int watchdog_post_test (int flags)
+{
+	if (flags & POST_REBOOT) {
+		/* Test passed */
+		return 0;
+	}
+	else {
+		/* 10-second delay */
+		int ints = disable_interrupts ();
+		ulong base = post_time_ms (0);
+
+		while (post_time_ms (base) < 10000)
+			;
+		if (ints)
+			enable_interrupts ();
+
+		/*
+		 * If we have reached this point, the watchdog timer
+		 * does not work
+		 */
+		return -1;
+	}
+}
+
+#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
+#endif /* CONFIG_POST */
diff --git a/post/drivers/Makefile b/post/drivers/Makefile
index 068fa98..cb2f1de 100644
--- a/post/drivers/Makefile
+++ b/post/drivers/Makefile
@@ -26,6 +26,6 @@ SUBDIRS =
 
 LIB	= libpostdrivers.a
 
-COBJS	= cache.o i2c.o memory.o rtc.o
+COBJS	= i2c.o memory.o rtc.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/lib_ppc/Makefile b/post/lib_ppc/Makefile
index 14354a0..9f1b329 100644
--- a/post/lib_ppc/Makefile
+++ b/post/lib_ppc/Makefile
@@ -21,6 +21,7 @@
 # MA 02111-1307 USA
 #
 
+SUBDIRS = fpu
 
 LIB	= libpostppc.a
 
diff --git a/post/lib_ppc/asm.S b/post/lib_ppc/asm.S
index a0815a4..5e72b34 100644
--- a/post/lib_ppc/asm.S
+++ b/post/lib_ppc/asm.S
@@ -34,6 +34,7 @@
 /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
 	.global	cpu_post_exec_02
 cpu_post_exec_02:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 
@@ -56,6 +57,7 @@ cpu_post_exec_02:
 /* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
 	.global	cpu_post_exec_04
 cpu_post_exec_04:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 
@@ -80,6 +82,7 @@ cpu_post_exec_04:
 /* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
 	.global	cpu_post_exec_12
 cpu_post_exec_12:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -100,6 +103,7 @@ cpu_post_exec_12:
 /* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
 	.global	cpu_post_exec_11
 cpu_post_exec_11:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -119,6 +123,7 @@ cpu_post_exec_11:
 /* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
 	.global	cpu_post_exec_21
 cpu_post_exec_21:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -148,6 +153,7 @@ cpu_post_exec_21:
     ulong op2); */
 	.global	cpu_post_exec_22
 cpu_post_exec_22:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -177,6 +183,7 @@ cpu_post_exec_22:
 /* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
 	.global	cpu_post_exec_12w
 cpu_post_exec_12w:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -198,6 +205,7 @@ cpu_post_exec_12w:
 /* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
 	.global	cpu_post_exec_11w
 cpu_post_exec_11w:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -218,6 +226,7 @@ cpu_post_exec_11w:
 /* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
 	.global	cpu_post_exec_22w
 cpu_post_exec_22w:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -241,6 +250,7 @@ cpu_post_exec_22w:
 /* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
 	.global	cpu_post_exec_21w
 cpu_post_exec_21w:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -263,6 +273,7 @@ cpu_post_exec_21w:
 /* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
 	.global	cpu_post_exec_21x
 cpu_post_exec_21x:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
@@ -286,6 +297,7 @@ cpu_post_exec_21x:
     ulong cr); */
 	.global	cpu_post_exec_31
 cpu_post_exec_31:
+	isync
 	mflr	r0
 	stwu	r0, -4(r1)
 	stwu	r4, -4(r1)
diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c
index b4b17c8..6e276c4 100644
--- a/post/lib_ppc/b.c
+++ b/post/lib_ppc/b.c
@@ -49,7 +49,7 @@ extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
     ulong cr);
 
 static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
-    int pjump, int dec, int link, ulong pctr, ulong cr)
+    int pjump, int decr, int link, ulong pctr, ulong cr)
 {
     int ret = 0;
     ulong lr = 0;
@@ -77,7 +77,7 @@ static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
 	ret = pjump == jump ? 0 : -1;
     if (ret == 0)
     {
-	if (dec)
+	if (decr)
 	    ret = pctr == ctr + 1 ? 0 : -1;
 	else
 	    ret = pctr == ctr ? 0 : -1;
@@ -163,7 +163,7 @@ int cpu_post_test_b (void)
 		    {
 			for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
 			{
-			    int dec = cd < 2;
+			    int decr = cd < 2;
 			    int cr = cond ? 0x80000000 : 0x00000000;
 			    int jumpc = cc >= 2 ||
 					(cc == 0 && !cond) ||
@@ -174,7 +174,7 @@ int cpu_post_test_b (void)
 			    int jump = jumpc && jumpd;
 
 			    ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
-				(cc << 3) + (cd << 1), 0, jump, dec, link,
+				(cc << 3) + (cd << 1), 0, jump, decr, link,
 				ctr, cr);
 
 			    if (ret != 0)
diff --git a/post/lib_ppc/fpu/20001122-1.c b/post/lib_ppc/fpu/20001122-1.c
new file mode 100644
index 0000000..f689b82
--- /dev/null
+++ b/post/lib_ppc/fpu/20001122-1.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * This file is originally a part of the GCC testsuite.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+int fpu_post_test_math1 (void)
+{
+	volatile double a, *p;
+	double c, d;
+	volatile double b;
+
+	d = 1.0;
+	p = &b;
+
+	do
+	{
+		c = d;
+		d = c * 0.5;
+		b = 1 + d;
+	} while (b != 1.0);
+
+	a = 1.0 + c;
+
+	if (a == 1.0) {
+		post_log ("Error in FPU math1 test\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/20010114-2.c b/post/lib_ppc/fpu/20010114-2.c
new file mode 100644
index 0000000..6e60507
--- /dev/null
+++ b/post/lib_ppc/fpu/20010114-2.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * This file is originally a part of the GCC testsuite.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+static float rintf (float x)
+{
+	volatile float TWO23 = 8388608.0;
+
+	if (__builtin_fabs (x) < TWO23)
+	{
+		if (x > 0.0)
+		{
+			x += TWO23;
+			x -= TWO23;
+		}
+		else if (x < 0.0)
+		{
+			x = TWO23 - x;
+			x = -(x - TWO23);
+		}
+	}
+
+	return x;
+}
+
+int fpu_post_test_math2 (void)
+{
+	if (rintf (-1.5) != -2.0) {
+		post_log ("Error in FPU math2 test\n");
+		return -1;
+	}
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/20010226-1.c b/post/lib_ppc/fpu/20010226-1.c
new file mode 100644
index 0000000..b2c47e3
--- /dev/null
+++ b/post/lib_ppc/fpu/20010226-1.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * This file is originally a part of the GCC testsuite.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+int fpu_post_test_math3 (void)
+{
+	volatile long double dfrom = 1.1;
+	volatile long double m1;
+	volatile long double m2;
+	volatile unsigned long mant_long;
+
+	m1 = dfrom / 2.0;
+	m2 = m1 * 4294967296.0;
+	mant_long = ((unsigned long) m2) & 0xffffffff;
+
+	if (mant_long != 0x8ccccccc) {
+		post_log ("Error in FPU math3 test\n");
+		return -1;
+	}
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/980619-1.c b/post/lib_ppc/fpu/980619-1.c
new file mode 100644
index 0000000..990aa0c
--- /dev/null
+++ b/post/lib_ppc/fpu/980619-1.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * This file is originally a part of the GCC testsuite.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+int fpu_post_test_math4 (void)
+{
+	volatile float reale = 1.0f;
+	volatile float oneplus;
+	int i;
+
+	if (sizeof (float) != 4)
+		return 0;
+
+	for (i = 0; ; i++)
+	{
+		oneplus = 1.0f + reale;
+		if (oneplus == 1.0f)
+			break;
+		reale = reale / 2.0f;
+	}
+	/* Assumes ieee754 accurate arithmetic above.  */
+	if (i != 24) {
+		post_log ("Error in FPU math4 test\n");
+		return -1;
+	}
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/Makefile b/post/lib_ppc/fpu/Makefile
new file mode 100644
index 0000000..82646c8
--- /dev/null
+++ b/post/lib_ppc/fpu/Makefile
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+LIB	= libpostppcfpu.a
+
+COBJS	+= fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
+COBJS	+= acc1.o compare-fp-1.o mul-subnormal-single-1.o
+
+include $(TOPDIR)/post/rules.mk
+
+CFLAGS += -mhard-float -fkeep-inline-functions
diff --git a/post/lib_ppc/fpu/acc1.c b/post/lib_ppc/fpu/acc1.c
new file mode 100644
index 0000000..4cecbf6
--- /dev/null
+++ b/post/lib_ppc/fpu/acc1.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * This file is originally a part of the GCC testsuite.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+static double func (const double *array)
+{
+	double d = *array;
+
+	if (d == 0.0)
+		return d;
+	else
+		return d + func (array + 1);
+}
+
+int fpu_post_test_math5 (void)
+{
+	double values[] = { 0.1e-100, 1.0, -1.0, 0.0 };
+
+	if (func (values) != 0.1e-100) {
+		post_log ("Error in FPU math5 test\n");
+		return -1;
+	}
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/compare-fp-1.c b/post/lib_ppc/fpu/compare-fp-1.c
new file mode 100644
index 0000000..d866ad5
--- /dev/null
+++ b/post/lib_ppc/fpu/compare-fp-1.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Test for correctness of composite floating-point comparisons.
+ * Written by Paolo Bonzini, 26th May 2004.
+ * This file is originally a part of the GCC testsuite.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+static int failed;
+
+#define TEST(c) if ((c) != ok) failed++
+#define ORD(a, b) (!__builtin_isunordered ((a), (b)))
+#define UNORD(a, b) (__builtin_isunordered ((a), (b)))
+#define UNEQ(a, b) (__builtin_isunordered ((a), (b)) || ((a) == (b)))
+#define UNLT(a, b) (__builtin_isunordered ((a), (b)) || ((a) < (b)))
+#define UNLE(a, b) (__builtin_isunordered ((a), (b)) || ((a) <= (b)))
+#define UNGT(a, b) (__builtin_isunordered ((a), (b)) || ((a) > (b)))
+#define UNGE(a, b) (__builtin_isunordered ((a), (b)) || ((a) >= (b)))
+#define LTGT(a, b) (__builtin_islessgreater ((a), (b)))
+
+static float pinf;
+static float ninf;
+static float NaN;
+
+static void iuneq (float x, float y, int ok)
+{
+	TEST (UNEQ (x, y));
+	TEST (!LTGT (x, y));
+	TEST (UNLE (x, y) && UNGE (x,y));
+}
+
+static void ieq (float x, float y, int ok)
+{
+	TEST (ORD (x, y) && UNEQ (x, y));
+}
+
+static void iltgt (float x, float y, int ok)
+{
+	TEST (!UNEQ (x, y)); /* Not optimizable. */
+	TEST (LTGT (x, y)); /* Same, __builtin_islessgreater does not trap. */
+	TEST (ORD (x, y) && (UNLT (x, y) || UNGT (x,y)));
+}
+
+static void ine (float x, float y, int ok)
+{
+	TEST (UNLT (x, y) || UNGT (x, y));
+}
+
+static void iunlt (float x, float y, int ok)
+{
+	TEST (UNLT (x, y));
+	TEST (UNORD (x, y) || (x < y));
+}
+
+static void ilt (float x, float y, int ok)
+{
+	TEST (ORD (x, y) && UNLT (x, y)); /* Not optimized */
+	TEST ((x <= y) && (x != y));
+	TEST ((x <= y) && (y != x));
+	TEST ((x != y) && (x <= y)); /* Not optimized */
+	TEST ((y != x) && (x <= y)); /* Not optimized */
+}
+
+static void iunle (float x, float y, int ok)
+{
+	TEST (UNLE (x, y));
+	TEST (UNORD (x, y) || (x <= y));
+}
+
+static void ile (float x, float y, int ok)
+{
+	TEST (ORD (x, y) && UNLE (x, y)); /* Not optimized */
+	TEST ((x < y) || (x == y));
+	TEST ((y > x) || (x == y));
+	TEST ((x == y) || (x < y)); /* Not optimized */
+	TEST ((y == x) || (x < y)); /* Not optimized */
+}
+
+static void iungt (float x, float y, int ok)
+{
+	TEST (UNGT (x, y));
+	TEST (UNORD (x, y) || (x > y));
+}
+
+static void igt (float x, float y, int ok)
+{
+	TEST (ORD (x, y) && UNGT (x, y)); /* Not optimized */
+	TEST ((x >= y) && (x != y));
+	TEST ((x >= y) && (y != x));
+	TEST ((x != y) && (x >= y)); /* Not optimized */
+	TEST ((y != x) && (x >= y)); /* Not optimized */
+}
+
+static void iunge (float x, float y, int ok)
+{
+	TEST (UNGE (x, y));
+	TEST (UNORD (x, y) || (x >= y));
+}
+
+static void ige (float x, float y, int ok)
+{
+	TEST (ORD (x, y) && UNGE (x, y)); /* Not optimized */
+	TEST ((x > y) || (x == y));
+	TEST ((y < x) || (x == y));
+	TEST ((x == y) || (x > y)); /* Not optimized */
+	TEST ((y == x) || (x > y)); /* Not optimized */
+}
+
+int fpu_post_test_math6 (void)
+{
+	pinf = __builtin_inf ();
+	ninf = -__builtin_inf ();
+	NaN = __builtin_nan ("");
+
+	iuneq (ninf, pinf, 0);
+	iuneq (NaN, NaN, 1);
+	iuneq (pinf, ninf, 0);
+	iuneq (1, 4, 0);
+	iuneq (3, 3, 1);
+	iuneq (5, 2, 0);
+
+	ieq (1, 4, 0);
+	ieq (3, 3, 1);
+	ieq (5, 2, 0);
+
+	iltgt (ninf, pinf, 1);
+	iltgt (NaN, NaN, 0);
+	iltgt (pinf, ninf, 1);
+	iltgt (1, 4, 1);
+	iltgt (3, 3, 0);
+	iltgt (5, 2, 1);
+
+	ine (1, 4, 1);
+	ine (3, 3, 0);
+	ine (5, 2, 1);
+
+	iunlt (NaN, ninf, 1);
+	iunlt (pinf, NaN, 1);
+	iunlt (pinf, ninf, 0);
+	iunlt (pinf, pinf, 0);
+	iunlt (ninf, ninf, 0);
+	iunlt (1, 4, 1);
+	iunlt (3, 3, 0);
+	iunlt (5, 2, 0);
+
+	ilt (1, 4, 1);
+	ilt (3, 3, 0);
+	ilt (5, 2, 0);
+
+	iunle (NaN, ninf, 1);
+	iunle (pinf, NaN, 1);
+	iunle (pinf, ninf, 0);
+	iunle (pinf, pinf, 1);
+	iunle (ninf, ninf, 1);
+	iunle (1, 4, 1);
+	iunle (3, 3, 1);
+	iunle (5, 2, 0);
+
+	ile (1, 4, 1);
+	ile (3, 3, 1);
+	ile (5, 2, 0);
+
+	iungt (NaN, ninf, 1);
+	iungt (pinf, NaN, 1);
+	iungt (pinf, ninf, 1);
+	iungt (pinf, pinf, 0);
+	iungt (ninf, ninf, 0);
+	iungt (1, 4, 0);
+	iungt (3, 3, 0);
+	iungt (5, 2, 1);
+
+	igt (1, 4, 0);
+	igt (3, 3, 0);
+	igt (5, 2, 1);
+
+	iunge (NaN, ninf, 1);
+	iunge (pinf, NaN, 1);
+	iunge (ninf, pinf, 0);
+	iunge (pinf, pinf, 1);
+	iunge (ninf, ninf, 1);
+	iunge (1, 4, 0);
+	iunge (3, 3, 1);
+	iunge (5, 2, 1);
+
+	ige (1, 4, 0);
+	ige (3, 3, 1);
+	ige (5, 2, 1);
+
+	if (failed) {
+		post_log ("Error in FPU math6 test\n");
+		return -1;
+	}
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/fpu.c b/post/lib_ppc/fpu/fpu.c
new file mode 100644
index 0000000..07dcba8
--- /dev/null
+++ b/post/lib_ppc/fpu/fpu.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Sergei Poselenov <sposelenov@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * FPU test
+ *
+ * This test checks the arithmetic logic unit (ALU) of CPU.
+ * It tests independently various groups of instructions using
+ * run-time modification of the code to reduce the memory footprint.
+ * For more details refer to post/cpu/ *.c files.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+#include <watchdog.h>
+
+extern int fpu_status (void);
+extern void fpu_enable (void);
+extern void fpu_disable (void);
+
+extern int fpu_post_test_math1 (void);
+extern int fpu_post_test_math2 (void);
+extern int fpu_post_test_math3 (void);
+extern int fpu_post_test_math4 (void);
+extern int fpu_post_test_math5 (void);
+extern int fpu_post_test_math6 (void);
+extern int fpu_post_test_math7 (void);
+
+int fpu_post_test (int flags)
+{
+	int fpu = fpu_status ();
+
+	int ret = 0;
+
+	WATCHDOG_RESET ();
+
+	if (!fpu)
+		fpu_enable ();
+
+	if (ret == 0)
+		ret = fpu_post_test_math1 ();
+	if (ret == 0)
+		ret = fpu_post_test_math2 ();
+	if (ret == 0)
+		ret = fpu_post_test_math3 ();
+	if (ret == 0)
+		ret = fpu_post_test_math4 ();
+	if (ret == 0)
+		ret = fpu_post_test_math5 ();
+	if (ret == 0)
+		ret = fpu_post_test_math6 ();
+	if (ret == 0)
+		ret = fpu_post_test_math7 ();
+
+	if (!fpu)
+		fpu_disable ();
+
+	WATCHDOG_RESET ();
+
+	return ret;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/mul-subnormal-single-1.c b/post/lib_ppc/fpu/mul-subnormal-single-1.c
new file mode 100644
index 0000000..67f48da
--- /dev/null
+++ b/post/lib_ppc/fpu/mul-subnormal-single-1.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * This file is originally a part of the GCC testsuite.
+ * Check that certain subnormal numbers (formerly known as denormalized
+ * numbers) are rounded to within 0.5 ulp.  PR other/14354.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_FPU
+
+union uf
+{
+	unsigned int u;
+	float f;
+};
+
+static float
+u2f (unsigned int v)
+{
+	union uf u;
+	u.u = v;
+	return u.f;
+}
+
+static unsigned int
+f2u (float v)
+{
+	union uf u;
+	u.f = v;
+	return u.u;
+}
+
+static int ok = 1;
+
+static void
+tstmul (unsigned int ux, unsigned int uy, unsigned int ur)
+{
+	float x = u2f (ux);
+	float y = u2f (uy);
+
+	if (f2u (x * y) != ur)
+	/* Set a variable rather than aborting here, to simplify tracing when
+	   several computations are wrong.  */
+		ok = 0;
+}
+
+/* We don't want to make this const and static, or else we risk inlining
+   causing the test to fold as constants at compile-time.  */
+struct
+{
+  unsigned int p1, p2, res;
+} static volatile expected[] =
+{
+	{0xfff, 0x3f800400, 0xfff},
+	{0xf, 0x3fc88888, 0x17},
+	{0xf, 0x3f844444, 0xf}
+};
+
+int fpu_post_test_math7 (void)
+{
+	unsigned int i;
+
+	for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++)
+	{
+		tstmul (expected[i].p1, expected[i].p2, expected[i].res);
+		tstmul (expected[i].p2, expected[i].p1, expected[i].res);
+	}
+
+	if (!ok) {
+		post_log ("Error in FPU math7 test\n");
+		return -1;
+	}
+	return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_FPU */
+#endif /* CONFIG_POST */
diff --git a/post/post.c b/post/post.c
index ac41990..28435cc 100644
--- a/post/post.c
+++ b/post/post.c
@@ -428,7 +428,7 @@ void post_reloc (void)
 unsigned long post_time_ms (unsigned long base)
 {
 #ifdef CONFIG_PPC
-	return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base;
+	return (unsigned long)(get_ticks () / (get_tbclk () / CFG_HZ)) - base;
 #else
 #warning "Not implemented yet"
 	return 0; /* Not implemented yet */
diff --git a/post/tests.c b/post/tests.c
index 3bccd1a..f3604b2 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -37,6 +37,7 @@ extern int i2c_post_test (int flags);
 extern int rtc_post_test (int flags);
 extern int memory_post_test (int flags);
 extern int cpu_post_test (int flags);
+extern int fpu_post_test (int flags);
 extern int uart_post_test (int flags);
 extern int ether_post_test (int flags);
 extern int spi_post_test (int flags);
@@ -126,6 +127,19 @@ struct post_test post_list[] =
 	CFG_POST_CPU
     },
 #endif
+#if CONFIG_POST & CFG_POST_FPU
+    {
+	"FPU test",
+	"fpu",
+	"This test verifies the arithmetic logic unit of"
+	" FPU.",
+	POST_RAM | POST_ALWAYS,
+	&fpu_post_test,
+	NULL,
+	NULL,
+	CFG_POST_FPU
+    },
+#endif
 #if CONFIG_POST & CFG_POST_UART
     {
 	"UART test",
diff --git a/tools/Makefile b/tools/Makefile
index 6177f90..5e26bd7 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -74,7 +74,7 @@ TOOLSUBDIRS =
 ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
 HOST_CFLAGS = -traditional-cpp -Wall
 HOST_LDFLAGS =-multiply_defined suppress
-HOST_ENVIRO_CFLAGS = -traditional-cpp
+HOST_ENVIRO_CFLAGS =
 
 else
 ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 416e658..2125130 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -446,7 +446,7 @@ NXTARG:		;
 	}
 
 	/* We're a bit of paranoid */
-#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__)
+#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__)
 	(void) fdatasync (ifd);
 #else
 	(void) fsync (ifd);
@@ -496,7 +496,7 @@ NXTARG:		;
 	(void) munmap((void *)ptr, sbuf.st_size);
 
 	/* We're a bit of paranoid */
-#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__)
+#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__)
 	(void) fdatasync (ifd);
 #else
 	(void) fsync (ifd);