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authorSimon Glass <sjg@chromium.org>2014-11-12 22:42:08 -0700
committerSimon Glass <sjg@chromium.org>2014-11-21 07:34:11 +0100
commitfce7b2768364366bd4c4af9188186f6b3f9c2fe8 (patch)
tree995131c544b4157faaaeec77983dd48660914b14
parent8ef07571a0300e6ae84931c63d5eb3b2310c8aba (diff)
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x86: Build a .rom file which can be flashed to an x86 machine
On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically. Unfortunately it relies on binary blobs so we cannot require this for the default build as yet. Create a u-boot.rom output file for this purpose. Signed-off-by: Simon Glass <sjg@chromium.org>
-rw-r--r--Makefile36
-rw-r--r--arch/x86/Kconfig13
-rw-r--r--include/configs/chromebook_link.h2
3 files changed, 50 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index ddea534..23590d9 100644
--- a/Makefile
+++ b/Makefile
@@ -749,6 +749,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
+# We can't do this yet due to the need for binary blobs
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
@@ -817,7 +820,8 @@ OBJCOPYFLAGS_u-boot.srec := -O srec
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
-OBJCOPYFLAGS_u-boot.bin := -O binary
+OBJCOPYFLAGS_u-boot.bin := -O binary \
+ $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
binary_size_check: u-boot.bin FORCE
@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
@@ -956,6 +960,36 @@ u-boot-nand.gph: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
+# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
+# the middle.
+ifneq ($(CONFIG_X86_RESET_VECTOR),)
+rom: u-boot.rom FORCE
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
+ $(srctree)/board/$(BOARDDIR)/mrc.bin
+ $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
+ if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
+ $(objtree)/tools/ifdtool -D \
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
+ $(objtree)/tools/ifdtool \
+ -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
+ fi
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
+ u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
+ u-boot.tmp
+ mv u-boot.tmp $@
+
+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
+u-boot-x86-16bit.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a5f24d0..aa7cf77 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -34,6 +34,19 @@ config TARGET_CHROMEBOOK_LINK
endchoice
+config ROM_SIZE
+ hex
+ default 0x800000
+
+config HAVE_INTEL_ME
+ bool "Platform requires Intel Management Engine"
+ help
+ Newer higher-end devices have an Intel Management Engine (ME)
+ which is a very large binary blob (typically 1.5MB) which is
+ required for the platform to work. This enforces a particular
+ SPI flash format. You will need to supply the me.bin file in
+ your board directory.
+
source "arch/x86/cpu/ivybridge/Kconfig"
source "board/chromebook-x86/coreboot/Kconfig"
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 394e27b..3137ef0 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -18,8 +18,10 @@
#define CONFIG_SYS_CAR_ADDR 0xff7e0000
#define CONFIG_SYS_CAR_SIZE (128 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_COREBOOT_SERIAL