Merge branch 'master' of git://git.denx.de/u-boot-arm

Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and serial. Conflicts: arch/arm/dts/exynos5250.dtsi Signed-off-by: Tom Rini <trini@ti.com>
author: Tom Rini <trini@ti.com> 2013-07-12 10:36:48 -0400
committer: Tom Rini <trini@ti.com> 2013-07-12 10:36:48 -0400
commit: fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc (patch)
tree: 9c91526cefd027d9bd964572d4f92bd2d1376c5d
parent: d72da1582895ca226b995758426ec3769b54a9b8 (diff)
parent: efc284e32503b240dbd35c6e8b8d098d702b4be7 (diff)
download: u-boot-imx-fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc.zip
u-boot-imx-fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc.tar.gz
u-boot-imx-fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc.tar.bz2
118 files changed, 5294 insertions, 2359 deletions
diff --git a/CREDITS b/CREDITS
index 7c1458f..3b657e9 100644
--- a/CREDITS
+++ b/CREDITS
@@ -124,6 +124,10 @@ N: James F. Dougherty
 E: jfd@GigabitNetworks.COM
 D: Port to the MOUSSE board
 
+N: Mike Dunn
+E: mikedunn@newsguy.com
+D: Palmtreo680 board, docg4 nand flash driver
+
 N: Dave Ellis
 E: DGE@sixnetio.com
 D: EEPROM Speedup, SXNI855T port
diff --git a/MAINTAINERS b/MAINTAINERS
index 7820375..3e70b03 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -651,6 +651,9 @@ Wolfgang Denk <wd@denx.de>
 	imx27lite	i.MX27
 	qong		i.MX31
 
+Mike Dunn <mikedunn@newsguy.com>
+	palmtreo680	pxa270
+
 Kristoffer Ericson <kristoffer.ericson@gmail.com>
 
 	jornada	SA1110
@@ -662,9 +665,9 @@ Fabio Estevam <fabio.estevam@freescale.com>
 	mx31pdk		i.MX31
 	mx53ard		i.MX53
 	mx53smd		i.MX53
-	mx6qsabresd	i.MX6Q
+	mx6sabresd	i.MX6Q/DL
 	mx6qsabreauto	i.MX6Q
-	wandboard	i.MX6DL/S
+	wandboard	i.MX6DL/S/Q
 	mx6slevk	i.MX6SL
 
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
index 41bb84b..a9a13cb 100644
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -159,6 +159,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	switch (clk) {
 	case MXC_ARM_CLK:
 		return imx_get_armclk();
+	case MXC_I2C_CLK:
+		return imx_get_ahbclk()/2;
 	case MXC_UART_CLK:
 		return imx_get_perclk1();
 	case MXC_FEC_CLK:
@@ -380,3 +382,11 @@ void mx27_sd2_init_pins(void)
 
 }
 #endif /* CONFIG_MXC_MMC */
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index b2f9152..4661155 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,10 +22,19 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+COBJS-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
+COBJS-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
+COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+COBJS-y	+= spl_boot.o
+COBJS-y	+= lowlevel_init.o
+endif
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	 $(obj).depend $(LIB)
 
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index e1c4246..9f07181 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -27,6 +27,10 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/periph.h>
 
+#define PLL_DIV_1024	1024
+#define PLL_DIV_65535	65535
+#define PLL_DIV_65536	65536
+
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers
@@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
 	unsigned long m, p, s = 0, mask, fout;
+	unsigned int div;
 	unsigned int freq;
 	/*
 	 * APLL_CON: MIDV [25:16]
@@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	if (pllreg == EPLL) {
 		k = k & 0xffff;
 		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 65536) * (freq / (p * (1 << s)));
+		fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
 	} else if (pllreg == VPLL) {
 		k = k & 0xfff;
-		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+		/*
+		 * Exynos4210
+		 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412
+		 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos5250
+		 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+		 */
+		if (proid_is_exynos4210())
+			div = PLL_DIV_1024;
+		else if (proid_is_exynos4412())
+			div = PLL_DIV_65535;
+		else if (proid_is_exynos5250())
+			div = PLL_DIV_65536;
+		else
+			return 0;
+
+		fout = (m + k / div) * (freq / (p * (1 << s)));
 	} else {
-		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-		fout = m * (freq / (p * (1 << s)));
+		/*
+		 * Exynos4210
+		 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412 / Exynos5250
+		 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+		 */
+		if (proid_is_exynos4210())
+			fout = m * (freq / (p * (1 << s)));
+		else
+			fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
 	return fout;
diff --git a/board/samsung/smdk5250/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h
index 20a1d47..20a1d47 100644
--- a/board/samsung/smdk5250/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
new file mode 100644
index 0000000..3161090
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
@@ -0,0 +1,95 @@
+/*
+ * Clock Initialization for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+void system_clock_init(void)
+{
+	struct exynos4_clock *clk =
+			(struct exynos4_clock *)samsung_get_base_clock();
+
+	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+	sdelay(0x10000);
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+	writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+	writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+	writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+	writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+	writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
+	writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+	writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+
+	sdelay(0x10000);
+
+	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+	writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+	writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+	writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+	writel(CLK_DIV_TOP_VAL, &clk->div_top);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+	writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+	writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+	writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
+	writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+	writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+
+	/* Set PLL locktime */
+	writel(PLL_LOCKTIME, &clk->apll_lock);
+	writel(PLL_LOCKTIME, &clk->mpll_lock);
+	writel(PLL_LOCKTIME, &clk->epll_lock);
+	writel(PLL_LOCKTIME, &clk->vpll_lock);
+
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON0_VAL, &clk->apll_con0);
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON0_VAL, &clk->mpll_con0);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON0_VAL, &clk->epll_con0);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON0_VAL, &clk->vpll_con0);
+
+	sdelay(0x30000);
+}
diff --git a/board/samsung/smdk5250/clock_init.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b288e66..0f9c572 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -31,7 +31,8 @@
 #include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define FSYS1_MMC0_DIV_MASK	0xff0f
 #define FSYS1_MMC0_DIV_VAL	0x0701
@@ -214,10 +215,10 @@ struct mem_timings mem_timings[] = {
 			DMC_MEMCONTROL_BL_8 |
 			DMC_MEMCONTROL_PZQ_DISABLE |
 			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
 		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
 		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
 		.prechconfig_tp_cnt = 0xff,
@@ -317,10 +318,10 @@ struct mem_timings mem_timings[] = {
 			DMC_MEMCONTROL_BL_8 |
 			DMC_MEMCONTROL_PZQ_DISABLE |
 			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
 		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
 		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
 		.prechconfig_tp_cnt = 0xff,
@@ -350,9 +351,8 @@ struct mem_timings mem_timings[] = {
  * @param frequency_mhz	Returns memory speed in MHz
  * @param arm_freq	Returns ARM clock speed in MHz
  * @param mem_manuf	Return Memory Manufacturer name
- * @return 0 if all ok
  */
-static int clock_get_mem_selection(enum ddr_mode *mem_type,
+static void clock_get_mem_selection(enum ddr_mode *mem_type,
 		unsigned *frequency_mhz, unsigned *arm_freq,
 		enum mem_manuf *mem_manuf)
 {
@@ -363,8 +363,6 @@ static int clock_get_mem_selection(enum ddr_mode *mem_type,
 	*frequency_mhz = params->frequency_mhz;
 	*arm_freq = params->arm_freq_mhz;
 	*mem_manuf = params->mem_manuf;
-
-	return 0;
 }
 
 /* Get the ratios for setting ARM clock */
@@ -376,9 +374,9 @@ struct arm_clk_ratios *get_arm_ratios(void)
 	unsigned frequency_mhz, arm_freq;
 	int i;
 
-	if (clock_get_mem_selection(&mem_type, &frequency_mhz,
-					&arm_freq, &mem_manuf))
-		;
+	clock_get_mem_selection(&mem_type, &frequency_mhz,
+				&arm_freq, &mem_manuf);
+
 	for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
 		i++, arm_ratio++) {
 		if (arm_ratio->arm_freq_mhz == arm_freq)
@@ -400,15 +398,14 @@ struct mem_timings *clock_get_mem_timings(void)
 	unsigned frequency_mhz, arm_freq;
 	int i;
 
-	if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
-						&arm_freq, &mem_manuf)) {
-		for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
-				i++, mem++) {
-			if (mem->mem_type == mem_type &&
-					mem->frequency_mhz == frequency_mhz &&
-					mem->mem_manuf == mem_manuf)
-				return mem;
-		}
+	clock_get_mem_selection(&mem_type, &frequency_mhz,
+				&arm_freq, &mem_manuf);
+	for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+	     i++, mem++) {
+		if (mem->mem_type == mem_type &&
+		    mem->frequency_mhz == frequency_mhz &&
+		    mem->mem_manuf == mem_manuf)
+			return mem;
 	}
 
 	/* will hang if failed to find memory timings */
@@ -420,7 +417,8 @@ struct mem_timings *clock_get_mem_timings(void)
 
 void system_clock_init()
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
 	struct mem_timings *mem;
 	struct arm_clk_ratios *arm_clk_ratio;
 	u32 val, tmp;
@@ -660,7 +658,8 @@ void system_clock_init()
 
 void clock_init_dp_clock(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
 
 	/* DP clock enable */
 	setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
@@ -675,7 +674,8 @@ void clock_init_dp_clock(void)
  */
 void emmc_boot_clk_div_set(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned int div_mmc;
 
 	div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h
new file mode 100644
index 0000000..e6318c0
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/common_setup.h
@@ -0,0 +1,45 @@
+/*
+ * Common APIs for EXYNOS based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DMC_OFFSET	0x10000
+
+/*
+ * Memory initialization
+ *
+ * @param reset     Reset PHY during initialization.
+ */
+void mem_ctrl_init(int reset);
+
+ /* System Clock initialization */
+void system_clock_init(void);
+
+/*
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int do_lowlevel_init(void);
+
+void sdelay(unsigned long);
diff --git a/board/samsung/smdk5250/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
index 109602a..645f57e 100644
--- a/board/samsung/smdk5250/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -26,7 +26,8 @@
 #include <asm/arch/spl.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define ZQ_INIT_TIMEOUT	10000
 
@@ -175,7 +176,7 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
 	writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
 }
 
-void mem_ctrl_init()
+void mem_ctrl_init(int reset)
 {
 	struct spl_machine_param *param = spl_get_machine_params();
 	struct mem_timings *mem;
@@ -185,7 +186,7 @@ void mem_ctrl_init()
 
 	/* If there are any other memory variant, add their init call below */
 	if (param->mem_type == DDR_MODE_DDR3) {
-		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
+		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
 		if (ret) {
 			/* will hang if failed to init memory control */
 			while (1)
diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index e050790..e03d74b 100644
--- a/board/samsung/smdk5250/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -27,31 +27,36 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 #include "clock_init.h"
 
 #define RDLVL_COMPLETE_TIMEOUT	10000
 
 static void reset_phy_ctrl(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
 
 	writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
 	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
 	struct exynos5_dmc *dmc;
 	int i;
 
-	phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
-	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
-	dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
+	phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+	phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+							+ DMC_OFFSET);
+	dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
 
-	reset_phy_ctrl();
+	if (reset)
+		reset_phy_ctrl();
 
 	/* Set Impedance Output Driver */
 	val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
@@ -100,14 +105,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
 	/* Start DLL locking */
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy0_ctrl->phy_con12);
+	       &phy0_ctrl->phy_con12);
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy1_ctrl->phy_con12);
+	       &phy1_ctrl->phy_con12);
 
 	update_reset_dll(dmc, DDR_MODE_DDR3);
 
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&dmc->concontrol);
+	       &dmc->concontrol);
 
 	/* Memory Channel Inteleaving Size */
 	writel(mem->iv_size, &dmc->ivcontrol);
@@ -119,7 +124,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
 	/* Precharge Configuration */
 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&dmc->prechconfig);
+	       &dmc->prechconfig);
 
 	/* Power Down mode Configuration */
 	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
new file mode 100644
index 0000000..ecddc72
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
@@ -0,0 +1,213 @@
+/*
+ * Memory setup for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+struct mem_timings mem = {
+	.direct_cmd_msr = {
+		DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
+	},
+	.timingref = TIMINGREF_VAL,
+	.timingrow = TIMINGROW_VAL,
+	.timingdata = TIMINGDATA_VAL,
+	.timingpower = TIMINGPOWER_VAL,
+	.zqcontrol = ZQ_CONTROL_VAL,
+	.control0 = CONTROL0_VAL,
+	.control1 = CONTROL1_VAL,
+	.control2 = CONTROL2_VAL,
+	.concontrol = CONCONTROL_VAL,
+	.prechconfig = PRECHCONFIG,
+	.memcontrol = MEMCONTROL_VAL,
+	.memconfig0 = MEMCONFIG0_VAL,
+	.memconfig1 = MEMCONFIG1_VAL,
+	.dll_resync = FORCE_DLL_RESYNC,
+	.dll_on = DLL_CONTROL_ON,
+};
+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
+{
+	if (ctrl_no) {
+		writel((mem.control1 | (1 << mem.dll_resync)),
+		       &dmc->phycontrol1);
+		writel((mem.control1 | (0 << mem.dll_resync)),
+		       &dmc->phycontrol1);
+	} else {
+		writel((mem.control0 | (0 << mem.dll_on)),
+		       &dmc->phycontrol0);
+		writel((mem.control0 | (1 << mem.dll_on)),
+		       &dmc->phycontrol0);
+	}
+}
+
+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
+{
+	int i;
+	unsigned long mask = 0;
+
+	if (chip)
+		mask = DIRECT_CMD_CHIP1_SHIFT;
+
+	for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+		writel(mem.direct_cmd_msr[i] | mask,
+		       &dmc->directcmd);
+	}
+}
+
+static void dmc_init(struct exynos4_dmc *dmc)
+{
+	/*
+	 * DLL Parameter Setting:
+	 * Termination: Enable R/W
+	 * Phase Delay for DQS Cleaning: 180' Shift
+	 */
+	writel(mem.control1, &dmc->phycontrol1);
+
+	/*
+	 * ZQ Calibration
+	 * Termination: Disable
+	 * Auto Calibration Start: Enable
+	 */
+	writel(mem.zqcontrol, &dmc->phyzqcontrol);
+	sdelay(0x100000);
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	phy_control_reset(1, dmc);
+	phy_control_reset(0, dmc);
+
+	/* Set DLL Parameters */
+	writel(mem.control1, &dmc->phycontrol1);
+
+	/* DLL Start */
+	writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
+
+	writel(mem.control2, &dmc->phycontrol2);
+
+	/* Set Clock Ratio of Bus clock to Memory Clock */
+	writel(mem.concontrol, &dmc->concontrol);
+
+	/*
+	 * Memor Burst length: 8
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: DDR3
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	writel(mem.memcontrol, &dmc->memcontrol);
+
+	writel(mem.memconfig0, &dmc->memconfig0);
+	writel(mem.memconfig1, &dmc->memconfig1);
+
+	/* Config Precharge Policy */
+	writel(mem.prechconfig, &dmc->prechconfig);
+	/*
+	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	writel(mem.timingref, &dmc->timingref);
+	writel(mem.timingrow, &dmc->timingrow);
+	writel(mem.timingdata, &dmc->timingdata);
+	writel(mem.timingpower, &dmc->timingpower);
+
+	/* Chip0: NOP Command: Assert and Hold CKE to high level */
+	writel(DIRECT_CMD_NOP, &dmc->directcmd);
+	sdelay(0x100000);
+
+	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	dmc_config_mrs(dmc, 0);
+	sdelay(0x100000);
+
+	/* Chip0: ZQINIT */
+	writel(DIRECT_CMD_ZQ, &dmc->directcmd);
+	sdelay(0x100000);
+
+	writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
+	sdelay(0x100000);
+
+	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	dmc_config_mrs(dmc, 1);
+	sdelay(0x100000);
+
+	/* Chip1: ZQINIT */
+	writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
+	sdelay(0x100000);
+
+	phy_control_reset(1, dmc);
+	sdelay(0x100000);
+
+	/* turn on DREX0, DREX1 */
+	writel((mem.concontrol | AREF_EN), &dmc->concontrol);
+}
+
+void mem_ctrl_init(int reset)
+{
+	struct exynos4_dmc *dmc;
+
+	/*
+	 * Async bridge configuration at CPU_core:
+	 * 1: half_sync
+	 * 0: full_sync
+	 */
+	writel(1, ASYNC_CONFIG);
+#ifdef CONFIG_ORIGEN
+	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_INTERLEAVE_CONF_OFFSET);
+	/* Update MIU Configuration */
+	writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_ARBRITATION_CONF_OFFSET);
+#else
+	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_INTERLEAVE_CONF_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#ifdef CONFIG_MIU_LINEAR
+	writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
+	writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
+	writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);
+	writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
+	writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#endif
+#endif
+	/* DREX0 */
+	dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
+	dmc_init(dmc);
+	dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
+					+ DMC_OFFSET);
+	dmc_init(dmc);
+}
diff --git a/board/samsung/origen/origen_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h
index 926a4cc..6d25058 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h
@@ -1,5 +1,5 @@
 /*
- * Machine Specific Values for ORIGEN board based on S5PV310
+ * Machine Specific Values for EXYNOS4012 based board
  *
  * Copyright (C) 2011 Samsung Electronics
  *
@@ -29,98 +29,22 @@
 #include <version.h>
 #include <asm/arch/cpu.h>
 
-/* Offsets of clock registers (sources and dividers) */
-#define CLK_SRC_CPU_OFFSET	0x14200
-#define CLK_DIV_CPU0_OFFSET	0x14500
-#define CLK_DIV_CPU1_OFFSET	0x14504
-
-#define CLK_SRC_DMC_OFFSET	0x10200
-#define CLK_DIV_DMC0_OFFSET	0x10500
-#define CLK_DIV_DMC1_OFFSET	0x10504
-
-#define CLK_SRC_TOP0_OFFSET	0xC210
-#define CLK_SRC_TOP1_OFFSET	0xC214
-#define CLK_DIV_TOP_OFFSET	0xC510
-
-#define CLK_SRC_LEFTBUS_OFFSET	0x4200
-#define CLK_DIV_LEFTBUS_OFFSET	0x4500
-
-#define CLK_SRC_RIGHTBUS_OFFSET	0x8200
-#define CLK_DIV_RIGHTBUS_OFFSET	0x8500
-
-#define CLK_SRC_FSYS_OFFSET	0xC240
-#define CLK_DIV_FSYS1_OFFSET	0xC544
-#define CLK_DIV_FSYS2_OFFSET	0xC548
-#define CLK_DIV_FSYS3_OFFSET	0xC54C
-
-#define CLK_SRC_CAM_OFFSET	0xC220
-#define CLK_SRC_TV_OFFSET	0xC224
-#define CLK_SRC_MFC_OFFSET	0xC228
-#define CLK_SRC_G3D_OFFSET	0xC22C
-#define CLK_SRC_LCD0_OFFSET	0xC234
-#define CLK_SRC_PERIL0_OFFSET	0xC250
-
-#define CLK_DIV_CAM_OFFSET	0xC520
-#define CLK_DIV_TV_OFFSET	0xC524
-#define CLK_DIV_MFC_OFFSET	0xC528
-#define CLK_DIV_G3D_OFFSET	0xC52C
-#define CLK_DIV_LCD0_OFFSET	0xC534
-#define CLK_DIV_PERIL0_OFFSET	0xC550
-
-#define CLK_SRC_LCD0_OFFSET	0xC234
-
-#define APLL_LOCK_OFFSET	0x14000
-#define MPLL_LOCK_OFFSET	0x14008
-#define APLL_CON0_OFFSET	0x14100
-#define APLL_CON1_OFFSET	0x14104
-#define MPLL_CON0_OFFSET	0x14108
-#define MPLL_CON1_OFFSET	0x1410C
-
-#define EPLL_LOCK_OFFSET	0xC010
-#define VPLL_LOCK_OFFSET	0xC020
-#define EPLL_CON0_OFFSET	0xC110
-#define EPLL_CON1_OFFSET	0xC114
-#define VPLL_CON0_OFFSET	0xC120
-#define VPLL_CON1_OFFSET	0xC124
-
-/* DMC: DRAM Controllor Register offsets */
-#define DMC_CONCONTROL		0x00
-#define DMC_MEMCONTROL		0x04
-#define DMC_MEMCONFIG0		0x08
-#define DMC_MEMCONFIG1		0x0C
-#define DMC_DIRECTCMD		0x10
-#define DMC_PRECHCONFIG		0x14
-#define DMC_PHYCONTROL0		0x18
-#define DMC_PHYCONTROL1		0x1C
-#define DMC_PHYCONTROL2		0x20
-#define DMC_TIMINGAREF		0x30
-#define DMC_TIMINGROW		0x34
-#define DMC_TIMINGDATA		0x38
-#define DMC_TIMINGPOWER		0x3C
-#define DMC_PHYZQCONTROL	0x44
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
 
 /* Bus Configuration Register Address */
 #define ASYNC_CONFIG		0x10010350
 
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET		0xC00
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET			0x800
-#define INFORM1_OFFSET			0x804
-
-/* GPIO Offsets for UART: GPIO Contol Register */
-#define EXYNOS4_GPIO_A0_CON_OFFSET	0x00
-#define EXYNOS4_GPIO_A1_CON_OFFSET	0x20
-
-/* UART Register offsets */
-#define ULCON_OFFSET		0x00
-#define UCON_OFFSET		0x04
-#define UFCON_OFFSET		0x08
-#define UBRDIV_OFFSET		0x28
-#define UFRACVAL_OFFSET		0x2C
-
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL		0x0
 #define MUX_HPM_SEL_SCLKMPLL		0x1
@@ -485,123 +409,186 @@
 				| (VPLL_MRR << 24) \
 				| (VPLL_MFR << 16) \
 				| (VPLL_K << 0))
-/*
- * UART GPIO_A0/GPIO_A1 Control Register Value
- * 0x2: UART Function
- */
-#define EXYNOS4_GPIO_A0_CON_VAL	0x22222222
-#define EXYNOS4_GPIO_A1_CON_VAL	0x222222
-
-/* ULCON: UART Line Control Value 8N1 */
-#define WORD_LEN_5_BIT		0x00
-#define WORD_LEN_6_BIT		0x01
-#define WORD_LEN_7_BIT		0x02
-#define WORD_LEN_8_BIT		0x03
-
-#define STOP_BIT_1		0x00
-#define STOP_BIT_2		0x01
-
-#define NO_PARITY			0x00
-#define ODD_PARITY			0x4
-#define EVEN_PARITY			0x5
-#define FORCED_PARITY_CHECK_AS_1	0x6
-#define FORCED_PARITY_CHECK_AS_0	0x7
-
-#define INFRAMODE_NORMAL		0x00
-#define INFRAMODE_INFRARED		0x01
-
-#define ULCON_VAL		((INFRAMODE_NORMAL << 6) \
-				| (NO_PARITY << 3) \
-				| (STOP_BIT_1 << 2) \
-				| (WORD_LEN_8_BIT << 0))
 
-/*
- * UCON: UART Control Value
- * Tx_interrupt Type: Level
- * Rx_interrupt Type: Level
- * Rx Timeout Enabled: Yes
- * Rx-Error Atatus_Int Enable: Yes
- * Loop_Back: No
- * Break Signal: No
- * Transmit mode : Interrupt request/polling
- * Receive mode : Interrupt request/polling
- */
-#define TX_PULSE_INTERRUPT	0
-#define TX_LEVEL_INTERRUPT	1
-#define RX_PULSE_INTERRUPT	0
-#define RX_LEVEL_INTERRUPT	1
-
-#define RX_TIME_OUT		ENABLE
-#define RX_ERROR_STATE_INT_ENB	ENABLE
-#define LOOP_BACK		DISABLE
-#define BREAK_SIGNAL		DISABLE
-
-#define TX_MODE_DISABLED	0X00
-#define TX_MODE_IRQ_OR_POLL	0X01
-#define TX_MODE_DMA		0X02
-
-#define RX_MODE_DISABLED	0X00
-#define RX_MODE_IRQ_OR_POLL	0X01
-#define RX_MODE_DMA		0X02
-
-#define UCON_VAL		((TX_LEVEL_INTERRUPT << 9) \
-				| (RX_LEVEL_INTERRUPT << 8) \
-				| (RX_TIME_OUT << 7) \
-				| (RX_ERROR_STATE_INT_ENB << 6) \
-				| (LOOP_BACK << 5) \
-				| (BREAK_SIGNAL << 4) \
-				| (TX_MODE_IRQ_OR_POLL << 2) \
-				| (RX_MODE_IRQ_OR_POLL << 0))
+/* DMC */
+#define DIRECT_CMD_NOP	0x07000000
+#define DIRECT_CMD_ZQ	0x0a000000
+#define DIRECT_CMD_CHIP1_SHIFT	(1 << 20)
+#define MEM_TIMINGS_MSR_COUNT	4
+#define CTRL_START	(1 << 0)
+#define CTRL_DLL_ON	(1 << 1)
+#define AREF_EN		(1 << 5)
+#define DRV_TYPE	(1 << 6)
+
+struct mem_timings {
+	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+	unsigned timingref;
+	unsigned timingrow;
+	unsigned timingdata;
+	unsigned timingpower;
+	unsigned zqcontrol;
+	unsigned control0;
+	unsigned control1;
+	unsigned control2;
+	unsigned concontrol;
+	unsigned prechconfig;
+	unsigned memcontrol;
+	unsigned memconfig0;
+	unsigned memconfig1;
+	unsigned dll_resync;
+	unsigned dll_on;
+};
+
+/* MIU */
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET	0xC00
+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET	0x800
+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET	0x808
+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET	0x810
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET	0x818
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET	0x820
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET	0x828
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET	0x830
+
+#ifdef CONFIG_ORIGEN
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x20001507
+#define APB_SFR_ARBRITATION_CONF_VAL	0x00000001
+#endif
 
-/*
- * UFCON: UART FIFO Control Value
- * Tx FIFO Trigger LEVEL: 2 Bytes (001)
- * Rx FIFO Trigger LEVEL: 2 Bytes (001)
- * Tx Fifo Reset: No
- * Rx Fifo Reset: No
- * FIFO Enable: Yes
- */
-#define TX_FIFO_TRIGGER_LEVEL_0_BYTES	0x00
-#define TX_FIFO_TRIGGER_LEVEL_2_BYTES	0x1
-#define TX_FIFO_TRIGGER_LEVEL_4_BYTES	0x2
-#define TX_FIFO_TRIGGER_LEVEL_6_BYTES	0x3
-#define TX_FIFO_TRIGGER_LEVEL_8_BYTES	0x4
-#define TX_FIFO_TRIGGER_LEVEL_10_BYTES	0x5
-#define TX_FIFO_TRIGGER_LEVEL_12_BYTES	0x6
-#define TX_FIFO_TRIGGER_LEVEL_14_BYTES	0x7
-
-#define RX_FIFO_TRIGGER_LEVEL_2_BYTES	0x0
-#define RX_FIFO_TRIGGER_LEVEL_4_BYTES	0x1
-#define RX_FIFO_TRIGGER_LEVEL_6_BYTES	0x2
-#define RX_FIFO_TRIGGER_LEVEL_8_BYTES	0x3
-#define RX_FIFO_TRIGGER_LEVEL_10_BYTES	0x4
-#define RX_FIFO_TRIGGER_LEVEL_12_BYTES	0x5
-#define RX_FIFO_TRIGGER_LEVEL_14_BYTES	0x6
-#define RX_FIFO_TRIGGER_LEVEL_16_BYTES	0x7
-
-#define TX_FIFO_TRIGGER_LEVEL		TX_FIFO_TRIGGER_LEVEL_2_BYTES
-#define RX_FIFO_TRIGGER_LEVEL		RX_FIFO_TRIGGER_LEVEL_4_BYTES
-#define TX_FIFO_RESET			DISABLE
-#define RX_FIFO_RESET			DISABLE
-#define FIFO_ENABLE			ENABLE
-#define UFCON_VAL			((TX_FIFO_TRIGGER_LEVEL << 8) \
-					| (RX_FIFO_TRIGGER_LEVEL << 4) \
-					| (TX_FIFO_RESET << 2) \
-					| (RX_FIFO_RESET << 1) \
-					| (FIFO_ENABLE << 0))
-/*
- * Baud Rate Division Value
- * 115200 BAUD:
- * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
- * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
- */
-#define UBRDIV_VAL		0x35
+#define INTERLEAVE_ADDR_MAP_START_ADDR	0x40000000
+#define INTERLEAVE_ADDR_MAP_END_ADDR	0xbfffffff
+#define INTERLEAVE_ADDR_MAP_EN		0x00000001
 
-/*
- * Fractional Part of Baud Rate Divisor:
- * 115200 BAUD:
- * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
- * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
- */
-#define UFRACVAL_VAL		0x4
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+/* Interleave_bit0: 0xC*/
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x0000000c
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x2000150c
+#endif
+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR	0x40000000
+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR		0x7fffffff
+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR	0x80000000
+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR		0xbfffffff
+/* Enable SME0 and SME1*/
+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL		0x00000006
+
+#define FORCE_DLL_RESYNC	3
+#define DLL_CONTROL_ON		1
+
+#define DIRECT_CMD1	0x00020000
+#define DIRECT_CMD2	0x00030000
+#define DIRECT_CMD3	0x00010002
+#define DIRECT_CMD4	0x00000328
+
+#define CTRL_ZQ_MODE_NOTERM	(0x1 << 0)
+#define CTRL_ZQ_START		(0x1 << 1)
+#define CTRL_ZQ_DIV		(0 << 4)
+#define CTRL_ZQ_MODE_DDS	(0x7 << 8)
+#define CTRL_ZQ_MODE_TERM	(0x2 << 11)
+#define CTRL_ZQ_FORCE_IMPN	(0x5 << 14)
+#define CTRL_ZQ_FORCE_IMPP	(0x6 << 17)
+#define CTRL_DCC		(0xE38 << 20)
+#define ZQ_CONTROL_VAL		(CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
+				| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
+				| CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
+				| CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
+
+#define ASYNC			(0 << 0)
+#define CLK_RATIO		(1 << 1)
+#define DIV_PIPE		(1 << 3)
+#define AWR_ON			(1 << 4)
+#define AREF_DISABLE		(0 << 5)
+#define DRV_TYPE_DISABLE	(0 << 6)
+#define CHIP0_NOT_EMPTY		(0 << 8)
+#define CHIP1_NOT_EMPTY		(0 << 9)
+#define DQ_SWAP_DISABLE		(0 << 10)
+#define QOS_FAST_DISABLE	(0 << 11)
+#define RD_FETCH		(0x3 << 12)
+#define TIMEOUT_LEVEL0		(0xFFF << 16)
+#define CONCONTROL_VAL		(ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
+				| AREF_DISABLE | DRV_TYPE_DISABLE\
+				| CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
+				| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
+				| RD_FETCH | TIMEOUT_LEVEL0)
+
+#define CLK_STOP_DISABLE	(0 << 1)
+#define DPWRDN_DISABLE		(0 << 2)
+#define DPWRDN_TYPE		(0 << 3)
+#define TP_DISABLE		(0 << 4)
+#define DSREF_DIABLE		(0 << 5)
+#define ADD_LAT_PALL		(1 << 6)
+#define MEM_TYPE_DDR3		(0x6 << 8)
+#define MEM_WIDTH_32		(0x2 << 12)
+#define NUM_CHIP_2		(1 << 16)
+#define BL_8			(0x3 << 20)
+#define MEMCONTROL_VAL		(CLK_STOP_DISABLE | DPWRDN_DISABLE\
+				| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
+				| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
+				| NUM_CHIP_2 | BL_8)
+
+
+#define CHIP_BANK_8		(0x3 << 0)
+#define CHIP_ROW_14		(0x2 << 4)
+#define CHIP_COL_10		(0x3 << 8)
+#define CHIP_MAP_INTERLEAVED	(1 << 12)
+#define CHIP_MASK		(0xe0 << 16)
+#ifdef CONFIG_MIU_LINEAR
+#define CHIP0_BASE		(0x40 << 24)
+#define CHIP1_BASE		(0x60 << 24)
+#else
+#define CHIP0_BASE		(0x20 << 24)
+#define CHIP1_BASE		(0x40 << 24)
+#endif
+#define MEMCONFIG0_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
+#define MEMCONFIG1_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
+
+#define TP_CNT			(0xff << 24)
+#define PRECHCONFIG		TP_CNT
+
+#define CTRL_OFF		(0 << 0)
+#define CTRL_DLL_OFF		(0 << 1)
+#define CTRL_HALF		(0 << 2)
+#define CTRL_DFDQS		(1 << 3)
+#define DQS_DELAY		(0 << 4)
+#define CTRL_START_POINT	(0x10 << 8)
+#define CTRL_INC		(0x10 << 16)
+#define CTRL_FORCE		(0x71 << 24)
+#define CONTROL0_VAL		(CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
+				| CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
+				| CTRL_INC | CTRL_FORCE)
+
+#define CTRL_SHIFTC		(0x6 << 0)
+#define CTRL_REF		(8 << 4)
+#define CTRL_SHGATE		(1 << 29)
+#define TERM_READ_EN		(1 << 30)
+#define TERM_WRITE_EN		(1 << 31)
+#define CONTROL1_VAL		(CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
+				| TERM_READ_EN | TERM_WRITE_EN)
+
+#define CONTROL2_VAL		0x00000000
+
+#ifdef CONFIG_ORIGEN
+#define TIMINGREF_VAL		0x000000BB
+#define TIMINGROW_VAL		0x4046654f
+#define	TIMINGDATA_VAL		0x46400506
+#define	TIMINGPOWER_VAL		0x52000A3C
+#else
+#define TIMINGREF_VAL		0x000000BC
+#ifdef DRAM_CLK_330
+#define TIMINGROW_VAL		0x3545548d
+#define	TIMINGDATA_VAL		0x45430506
+#define	TIMINGPOWER_VAL		0x4439033c
+#endif
+#ifdef DRAM_CLK_400
+#define TIMINGROW_VAL		0x45430506
+#define	TIMINGDATA_VAL		0x56500506
+#define	TIMINGPOWER_VAL		0x5444033d
+#endif
+#endif
 #endif
diff --git a/board/samsung/smdk5250/setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index eb91d13..8f36c16 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -93,17 +93,17 @@
 #define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
 
 /* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED     (1 << 12)
-#define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
-#define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
-#define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
-#define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
-
-#define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)
-#define DMC_MEMBASECONFIGx_CHIP_MASK(x)         (x << 0)
+#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
+#define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
+#define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)
+
+#define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
+#define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
 #define DMC_MEMBASECONFIG_VAL(x)        (       \
-	DMC_MEMBASECONFIGx_CHIP_BASE(x) |       \
-	DMC_MEMBASECONFIGx_CHIP_MASK(0x780)     \
+	DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
+	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
 )
 
 #define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)
@@ -513,9 +513,11 @@ enum {
  *			which the DMC uses to decide how to split a memory
  *			chunk into smaller chunks to support concurrent
  *			accesses; may vary across boards.
+ * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+			int reset);
 
 /*
  * Configure ZQ I/O interface
@@ -562,8 +564,4 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
  * @param ddr_mode	Type of DDR memory
  */
 void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
-
-void sdelay(unsigned long);
-void mem_ctrl_init(void);
-void system_clock_init(void);
 #endif
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
new file mode 100644
index 0000000..11fe5b8
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -0,0 +1,73 @@
+/*
+ * Lowlevel setup for EXYNOS5 based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/tzpc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include "common_setup.h"
+
+/* These are the things we can do during low-level init */
+enum {
+	DO_WAKEUP	= 1 << 0,
+	DO_CLOCKS	= 1 << 1,
+	DO_MEM_RESET	= 1 << 2,
+	DO_UART		= 1 << 3,
+};
+
+int do_lowlevel_init(void)
+{
+	uint32_t reset_status;
+	int actions = 0;
+
+	arch_cpu_init();
+
+	reset_status = get_reset_status();
+
+	switch (reset_status) {
+	case S5P_CHECK_SLEEP:
+		actions = DO_CLOCKS | DO_WAKEUP;
+		break;
+	case S5P_CHECK_DIDLE:
+	case S5P_CHECK_LPA:
+		actions = DO_WAKEUP;
+		break;
+	default:
+		/* This is a normal boot (not a wake from sleep) */
+		actions = DO_CLOCKS | DO_MEM_RESET;
+	}
+
+	if (actions & DO_CLOCKS) {
+		system_clock_init();
+		mem_ctrl_init(actions & DO_MEM_RESET);
+		tzpc_init();
+	}
+
+	return actions & DO_WAKEUP;
+}
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index bd499b4..2042062 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -408,9 +408,49 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	return 0;
 }
 
+static void exynos4_uart_config(int peripheral)
+{
+	struct exynos4_gpio_part1 *gpio1 =
+		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->a0;
+		start = 4;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	}
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
 static int exynos4_pinmux_config(int peripheral, int flags)
 {
 	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos4_uart_config(peripheral);
+		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
 	case PERIPH_ID_I2C2:
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index 6375a81..5d3bda2 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -140,3 +140,53 @@ void set_hw_thermal_trip(void)
 		setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
 	}
 }
+
+static uint32_t exynos5_get_reset_status(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	return power->inform1;
+}
+
+static uint32_t exynos4_get_reset_status(void)
+{
+	struct exynos4_power *power =
+		(struct exynos4_power *)samsung_get_base_power();
+
+	return power->inform1;
+}
+
+uint32_t get_reset_status(void)
+{
+	if (cpu_is_exynos5())
+		return exynos5_get_reset_status();
+	else
+		return  exynos4_get_reset_status();
+}
+
+static void exynos5_power_exit_wakeup(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+	typedef void (*resume_func)(void);
+
+	((resume_func)power->inform0)();
+}
+
+static void exynos4_power_exit_wakeup(void)
+{
+	struct exynos4_power *power =
+		(struct exynos4_power *)samsung_get_base_power();
+	typedef void (*resume_func)(void);
+
+	((resume_func)power->inform0)();
+}
+
+void power_exit_wakeup(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_power_exit_wakeup();
+	else
+		exynos4_power_exit_wakeup();
+}
diff --git a/board/samsung/smdk5250/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index 98f2286..6e8dd3b 100644
--- a/board/samsung/smdk5250/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -23,12 +23,18 @@
 #include<common.h>
 #include<config.h>
 
-#include <asm/arch-exynos/dmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/spl.h>
 
+#include "common_setup.h"
 #include "clock_init.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+#define OM_STAT         (0x1f << 1)
+
 /* Index into irom ptr table */
 enum index {
 	MMC_INDEX,
@@ -48,20 +54,12 @@ u32 irom_ptr_table[] = {
 	[USB_INDEX] = 0x02020070,	/* iROM Function Pointer-USB boot*/
 	};
 
-enum boot_mode {
-	BOOT_MODE_MMC = 4,
-	BOOT_MODE_SERIAL = 20,
-	BOOT_MODE_EMMC = 8,     /* EMMC4.4 */
-	/* Boot based on Operating Mode pin settings */
-	BOOT_MODE_OM = 32,
-	BOOT_MODE_USB,	/* Boot using USB download */
-};
-
 void *get_irom_func(int index)
 {
 	return (void *)*(u32 *)irom_ptr_table[index];
 }
 
+#ifdef CONFIG_USB_BOOTING
 /*
  * Set/clear program flow prediction and return the previous state.
  */
@@ -75,6 +73,7 @@ static int config_branch_prediction(int set_cr_z)
 
 	return cr & CR_Z;
 }
+#endif
 
 /*
 * Copy U-boot from mmc to RAM:
@@ -83,35 +82,42 @@ static int config_branch_prediction(int set_cr_z)
 */
 void copy_uboot_to_ram(void)
 {
-	int is_cr_z_set;
-	unsigned int sec_boot_check;
 	enum boot_mode bootmode = BOOT_MODE_OM;
 
-	u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
-	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
+	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
+	u32 offset = 0, size = 0;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
 	u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
 	void (*end_bootop_from_emmc)(void);
+#endif
+#ifdef CONFIG_USB_BOOTING
 	u32 (*usb_copy)(void);
+	int is_cr_z_set;
+	unsigned int sec_boot_check;
 
 	/* Read iRAM location to check for secondary USB boot mode */
 	sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
 	if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
 		bootmode = BOOT_MODE_USB;
+#endif
 
 	if (bootmode == BOOT_MODE_OM)
-		bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
+		bootmode = readl(samsung_get_base_power()) & OM_STAT;
 
 	switch (bootmode) {
+#ifdef CONFIG_SPI_BOOTING
 	case BOOT_MODE_SERIAL:
-		spi_copy = get_irom_func(SPI_INDEX);
-		spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
-			 CONFIG_SYS_TEXT_BASE);
+		offset = SPI_FLASH_UBOOT_POS;
+		size = CONFIG_BL2_SIZE;
+		copy_bl2 = get_irom_func(SPI_INDEX);
 		break;
+#endif
 	case BOOT_MODE_MMC:
+		offset = BL2_START_OFFSET;
+		size = BL2_SIZE_BLOC_COUNT;
 		copy_bl2 = get_irom_func(MMC_INDEX);
-		copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
-			 CONFIG_SYS_TEXT_BASE);
 		break;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
 	case BOOT_MODE_EMMC:
 		/* Set the FSYS1 clock divisor value for EMMC boot */
 		emmc_boot_clk_div_set();
@@ -122,6 +128,8 @@ void copy_uboot_to_ram(void)
 		copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
 		end_bootop_from_emmc();
 		break;
+#endif
+#ifdef CONFIG_USB_BOOTING
 	case BOOT_MODE_USB:
 		/*
 		 * iROM needs program flow prediction to be disabled
@@ -132,14 +140,50 @@ void copy_uboot_to_ram(void)
 		usb_copy();
 		config_branch_prediction(is_cr_z_set);
 		break;
+#endif
 	default:
 		break;
 	}
+
+	if (copy_bl2)
+		copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
+}
+
+void memzero(void *s, size_t n)
+{
+	char *ptr = s;
+	size_t i;
+
+	for (i = 0; i < n; i++)
+		*ptr++ = '\0';
+}
+
+/**
+ * Set up the U-Boot global_data pointer
+ *
+ * This sets the address of the global data, and sets up basic values.
+ *
+ * @param gdp   Value to give to gd
+ */
+static void setup_global_data(gd_t *gdp)
+{
+	gd = gdp;
+	memzero((void *)gd, sizeof(gd_t));
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->have_console = 1;
 }
 
 void board_init_f(unsigned long bootflag)
 {
+	__aligned(8) gd_t local_gd;
 	__attribute__((noreturn)) void (*uboot)(void);
+
+	setup_global_data(&local_gd);
+
+	if (do_lowlevel_init())
+		power_exit_wakeup();
+
 	copy_uboot_to_ram();
 
 	/* Jump to U-Boot image */
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 652e5a7..9ede3f5 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1200,6 +1200,9 @@ void dmm_init(u32 base)
 	/* TRAP for invalid TILER mappings in section 0 */
 	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
+	if (omap_revision() >= OMAP4460_ES1_0)
+		lis_map_regs_calculated.is_ma_present = 1;
+
 	lisa_map_regs = &lis_map_regs_calculated;
 #endif
 	struct dmm_lisa_map_regs *hw_lisa_map_regs =
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 56cf1f8..07b1108 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -412,6 +412,8 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_l4per_gpio4_clkctrl,
 		(*prcm)->cm_l4per_gpio5_clkctrl,
 		(*prcm)->cm_l4per_gpio6_clkctrl,
+		(*prcm)->cm_l4per_gpio7_clkctrl,
+		(*prcm)->cm_l4per_gpio8_clkctrl,
 		0
 	};
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index daf124e..11ba36b 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -43,13 +43,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
-static struct gpio_bank gpio_bank_54xx[6] = {
+static struct gpio_bank gpio_bank_54xx[8] = {
 	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
index 0bbe295..ea55859 100644
--- a/arch/arm/cpu/pxa/config.mk
+++ b/arch/arm/cpu/pxa/config.mk
@@ -24,7 +24,7 @@
 
 PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
-PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
+PLATFORM_CPPFLAGS += -mcpu=xscale
 # =========================================================================
 #
 # Supply options according to compiler version
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 2e3f65e..2e623b1 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -208,10 +208,9 @@ cpu_init_crit:
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00003300	@ clear bits 13:12, 9:8 (--VI --RS)
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
 	mov	pc, lr		/* back to my caller */
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 2d6dfff..4fff5e3 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -202,6 +202,34 @@
 		interrupts = <0 78 0>;
 	};
 
+	serial@12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+		id = <0>;
+	};
+
+	serial@12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 52 0>;
+		id = <1>;
+	};
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 53 0>;
+		id = <2>;
+	};
+
+	serial@12C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C30000 0x100>;
+		interrupts = <0 54 0>;
+		id = <3>;
+	};
+
 	gpio: gpio {
 	};
 };
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index f86d18d..626cc3c 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -216,4 +216,31 @@
 		clocks = <&tegra_car 15>;
 		status = "disable";
 	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = <52>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = <53>;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = <129>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index ccf154f..fee1c36 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -216,4 +216,31 @@
 		clocks = <&tegra_car 15>;
 		status = "disabled";
 	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra30-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = <52>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra30-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = <53>;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra30-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = <129>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index bb53a6a..d2f3a78 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -284,7 +284,6 @@ void config_ddr_data(const struct ddr_data *data, int nr);
  * This structure represents the DDR io control on AM33XX devices.
  */
 struct ddr_cmdtctrl {
-	unsigned int resv1[1];
 	unsigned int cm0ioctl;
 	unsigned int cm1ioctl;
 	unsigned int cm2ioctl;
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
index 1a211e9..8346979 100644
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -21,6 +21,8 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO		128
+
 #define AM33XX_GPIO0_BASE       0x44E07000
 #define AM33XX_GPIO1_BASE       0x4804C000
 #define AM33XX_GPIO2_BASE       0x481AC000
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 1ff7642..1ff231b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -40,8 +40,7 @@
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
 #define EXYNOS4_TZPC_BASE		0x10110000
 #define EXYNOS4_MIU_BASE		0x10600000
-#define EXYNOS4_DMC0_BASE		0x10400000
-#define EXYNOS4_DMC1_BASE		0x10410000
+#define EXYNOS4_DMC_CTRL_BASE		0x10400000
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
@@ -64,6 +63,7 @@
 #define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 
 /* EXYNOS4X12 */
 #define EXYNOS4X12_GPIO_PART3_BASE	0x03860000
@@ -76,8 +76,7 @@
 #define EXYNOS4X12_SYSTIMER_BASE	0x10050000
 #define EXYNOS4X12_WATCHDOG_BASE	0x10060000
 #define EXYNOS4X12_TZPC_BASE		0x10110000
-#define EXYNOS4X12_DMC0_BASE		0x10600000
-#define EXYNOS4X12_DMC1_BASE		0x10610000
+#define EXYNOS4X12_DMC_CTRL_BASE	0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
 #define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
 #define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
@@ -99,6 +98,7 @@
 #define EXYNOS4X12_SPI_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000
@@ -112,8 +112,7 @@
 #define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
-#define EXYNOS5_DMC_PHY0_BASE		0x10C00000
-#define EXYNOS5_DMC_PHY1_BASE		0x10C10000
+#define EXYNOS5_DMC_PHY_BASE		0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
@@ -239,6 +238,8 @@ SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 SAMSUNG_BASE(tzpc, TZPC_BASE)
+SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
+SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
 #endif
 
 #endif	/* _EXYNOS4_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 3549667..44ad8d3 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -888,4 +888,16 @@ void set_ps_hold_ctrl(void);
  * source as XXTI
  */
 void set_xclkout(void);
+
+/*
+ *  Read inform1 to get the reset status.
+ *  @return: the value can be either S5P_CHECK_SLEEP or
+ *  S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1
+ *  if none of these then its normal booting.
+ */
+uint32_t get_reset_status(void);
+
+
+/* Read the resume function and call it */
+void power_exit_wakeup(void);
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h
index 46b25a6..59bb7e0 100644
--- a/arch/arm/include/asm/arch-exynos/spl.h
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -32,6 +32,7 @@ enum boot_mode {
 	 * pin values are the same across Exynos4 and Exynos5.
 	 */
 	BOOT_MODE_MMC = 4,
+	BOOT_MODE_EMMC = 8,     /* EMMC4.4 */
 	BOOT_MODE_SERIAL = 20,
 	/* Boot based on Operating Mode pin settings */
 	BOOT_MODE_OM = 32,
diff --git a/arch/arm/include/asm/arch-mx27/clock.h b/arch/arm/include/asm/arch-mx27/clock.h
index fd062d3..2b03a41 100644
--- a/arch/arm/include/asm/arch-mx27/clock.h
+++ b/arch/arm/include/asm/arch-mx27/clock.h
@@ -26,6 +26,7 @@
 
 enum mxc_clock {
 	MXC_ARM_CLK,
+	MXC_I2C_CLK,
 	MXC_UART_CLK,
 	MXC_ESDHC_CLK,
 	MXC_FEC_CLK,
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 03abb2a..45824f9 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -364,7 +364,7 @@ struct iomuxc {
 
 #define IOMUXC_GPR2_MODE_DISABLED	0
 #define IOMUXC_GPR2_MODE_ENABLED_DI0	1
-#define IOMUXC_GPR2_MODE_ENABLED_DI1	2
+#define IOMUXC_GPR2_MODE_ENABLED_DI1	3
 
 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index a4134a0..dbb7856 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -23,114 +23,1661 @@
 #include <asm/imx-common/iomux-v3.h>
 
 enum {
+	MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10	= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC	= IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT10__ECSPI2_MISO		= IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0),
 	MX6_PAD_CSI0_DAT10__UART1_TXD		= IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT10__UART1_RXD		= IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0),
+	MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4	= IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT10__GPIO_5_28		= IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33	= IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7	= IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11	= IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS	= IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT11__ECSPI2_SS0		= IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0),
+	MX6_PAD_CSI0_DAT11__UART1_TXD		= IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0),
 	MX6_PAD_CSI0_DAT11__UART1_RXD		= IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5	= IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT11__GPIO_5_29		= IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34	= IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8	= IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12	= IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8	= IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16	= IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__UART4_TXD		= IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__UART4_RXD		= IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0),
+	MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6	= IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__GPIO_5_30		= IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35	= IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9	= IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13	= IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9	= IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17	= IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__UART4_TXD		= IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__UART4_RXD		= IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0),
+	MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7	= IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__GPIO_5_31		= IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36	= IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10	= IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14	= IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10	= IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18	= IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__UART5_TXD		= IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__UART5_RXD		= IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0),
+	MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8	= IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__GPIO_6_0		= IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37	= IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11	= IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15	= IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11	= IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19	= IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__UART5_TXD		= IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__UART5_RXD		= IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0),
+	MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9	= IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__GPIO_6_1		= IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38	= IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12	= IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16	= IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12	= IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20	= IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__UART4_CTS		= IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__UART4_RTS		= IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0),
+	MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10	= IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__GPIO_6_2		= IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39	= IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13	= IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17	= IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13	= IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21	= IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__UART4_CTS		= IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__UART4_RTS		= IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0),
+	MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11	= IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__GPIO_6_3		= IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40	= IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14	= IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18	= IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14	= IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22	= IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__UART5_CTS		= IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__UART5_RTS		= IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0),
+	MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12	= IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__GPIO_6_4		= IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41	= IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15	= IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19	= IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15	= IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23	= IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__UART5_CTS		= IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__UART5_RTS		= IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0),
+	MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13	= IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__GPIO_6_5		= IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42	= IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9	= IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4	= IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2	= IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT4__ECSPI1_SCLK		= IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0),
+	MX6_PAD_CSI0_DAT4__KPP_COL_5		= IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0),
+	MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC	= IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT4__GPIO_5_22		= IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43	= IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1	= IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5	= IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3	= IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT5__ECSPI1_MOSI		= IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0),
+	MX6_PAD_CSI0_DAT5__KPP_ROW_5		= IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0),
+	MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD	= IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT5__GPIO_5_23		= IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44	= IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2	= IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6	= IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4	= IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT6__ECSPI1_MISO		= IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0),
+	MX6_PAD_CSI0_DAT6__KPP_COL_6		= IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0),
+	MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS	= IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT6__GPIO_5_24		= IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45	= IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3	= IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7	= IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5	= IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT7__ECSPI1_SS0		= IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0),
+	MX6_PAD_CSI0_DAT7__KPP_ROW_6		= IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0),
+	MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD	= IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT7__GPIO_5_25		= IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46	= IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4	= IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8	= IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6	= IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK		= IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0),
+	MX6_PAD_CSI0_DAT8__KPP_COL_7		= IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0),
+	MX6_PAD_CSI0_DAT8__I2C1_SDA		= IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0),
+	MX6_PAD_CSI0_DAT8__GPIO_5_26		= IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47	= IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5	= IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9	= IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7	= IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI		= IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0),
+	MX6_PAD_CSI0_DAT9__KPP_ROW_7		= IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0),
+	MX6_PAD_CSI0_DAT9__I2C1_SCL		= IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0),
+	MX6_PAD_CSI0_DAT9__GPIO_5_27		= IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48	= IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6	= IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN	= IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0	= IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14	= IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2	= IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__GPIO_5_20		= IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31	= IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK	= IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC	= IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13	= IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__CCM_CLKO		= IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1	= IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__GPIO_5_19		= IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30	= IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_MCLK__SIMBA_TRCTL		= IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	= IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12	= IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0	= IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_PIXCLK__GPIO_5_18		= IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29	= IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO	= IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC	= IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1	= IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15	= IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3	= IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__GPIO_5_21		= IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32	= IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0	= IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	= IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DI0_DISP_CLK__LCDIF_CLK		= IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28	= IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	= IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__GPIO_4_16		= IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0	= IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR	= IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
+	MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN	= IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0),
 	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15	= IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2	= IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3	= IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN4__GPIO_4_20		= IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DI0_PIN15__LCDIF_ENABLE		= IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC	= IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29	= IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	= IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__GPIO_4_17		= IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1	= IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0	= IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN15__LCDIF_RD_E		= IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2		= IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DI0_PIN2__LCDIF_HSYNC		= IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0),
+	MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD	= IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30	= IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	= IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__GPIO_4_18		= IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2	= IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9	= IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN2__LCDIF_RS		= IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3		= IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DI0_PIN3__LCDIF_VSYNC		= IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS	= IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31	= IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	= IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__GPIO_4_19		= IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3	= IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10	= IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN3__LCDIF_CS		= IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4		= IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DI0_PIN4__LCDIF_BUSY		= IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0),
+	MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD	= IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN4__USDHC1_WP		= IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0),
+	MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD	= IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN4__GPIO_4_20		= IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4	= IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11	= IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
+	MX6_PAD_DI0_PIN4__LCDIF_RESET		= IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0	= IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT0__LCDIF_DAT_0		= IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK		= IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0	= IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	= IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT0__GPIO_4_21		= IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5	= IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1	= IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1	= IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT1__LCDIF_DAT_1		= IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1	= IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	= IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT1__GPIO_4_22		= IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6	= IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12	= IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__LCDIF_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6	= IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	= IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__GPIO_4_31		= IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15	= IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21	= IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11	= IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT11__LCDIF_DAT_11	= IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7	= IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4	= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT11__GPIO_5_5		= IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16	= IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22	= IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12	= IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT12__LCDIF_DAT_12	= IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5	= IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT12__GPIO_5_6		= IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17	= IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23	= IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13	= IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT13__LCDIF_DAT_13	= IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0),
+	MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0	= IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT13__GPIO_5_7		= IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18	= IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24	= IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14	= IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT14__LCDIF_DAT_14	= IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0),
+	MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1	= IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT14__GPIO_5_8		= IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19	= IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2	= IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15	= IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT15__LCDIF_DAT_15	= IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT15__ECSPI1_SS1		= IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0),
+	MX6_PAD_DISP0_DAT15__ECSPI2_SS1		= IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0),
+	MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2	= IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT15__GPIO_5_9		= IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20	= IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25	= IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16	= IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT16__LCDIF_DAT_16	= IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT16__ECSPI2_MOSI	= IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0),
+	MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0),
+	MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0	= IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0),
+	MX6_PAD_DISP0_DAT16__GPIO_5_10		= IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21	= IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26	= IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17	= IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT17__LCDIF_DAT_17	= IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT17__ECSPI2_MISO	= IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0),
+	MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0),
+	MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1	= IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0),
+	MX6_PAD_DISP0_DAT17__GPIO_5_11		= IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22	= IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27	= IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18	= IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT18__LCDIF_DAT_18	= IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT18__ECSPI2_SS0		= IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0),
+	MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0),
+	MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS	= IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0),
+	MX6_PAD_DISP0_DAT18__GPIO_5_12		= IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23	= IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2	= IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19	= IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT19__LCDIF_DAT_19	= IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT19__ECSPI2_SCLK	= IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0),
+	MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0),
+	MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC	= IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0),
+	MX6_PAD_DISP0_DAT19__GPIO_5_13		= IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24	= IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3	= IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__LCDIF_DAT_2		= IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__ECSPI3_MISO		= IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2	= IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE	= IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__GPIO_4_23		= IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7	= IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13	= IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20	= IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT20__LCDIF_DAT_20	= IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT20__ECSPI1_SCLK	= IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0),
+	MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0),
+	MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7	= IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT20__GPIO_5_14		= IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25	= IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28	= IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21	= IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT21__LCDIF_DAT_21	= IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT21__ECSPI1_MOSI	= IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0),
+	MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0),
+	MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	= IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT21__GPIO_5_15		= IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26	= IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29	= IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22	= IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT22__LCDIF_DAT_22	= IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT22__ECSPI1_MISO	= IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0),
+	MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0),
+	MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	= IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT22__GPIO_5_16		= IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27	= IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30	= IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23	= IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT23__LCDIF_DAT_23	= IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT23__ECSPI1_SS0		= IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0),
+	MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0),
+	MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	= IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT23__GPIO_5_17		= IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28	= IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31	= IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3	= IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT3__LCDIF_DAT_3		= IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT3__ECSPI3_SS0		= IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3	= IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	= IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT3__GPIO_4_24		= IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8	= IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14	= IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4	= IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT4__LCDIF_DAT_4		= IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT4__ECSPI3_SS1		= IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4	= IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB	= IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT4__GPIO_4_25		= IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9	= IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15	= IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5	= IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT5__LCDIF_DAT_5		= IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT5__ECSPI3_SS2		= IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS	= IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	= IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT5__GPIO_4_26		= IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10	= IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16	= IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6	= IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT6__LCDIF_DAT_6		= IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT6__ECSPI3_SS3		= IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC	= IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	= IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT6__GPIO_4_27		= IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11	= IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17	= IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7	= IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT7__LCDIF_DAT_7		= IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT7__ECSPI3_RDY		= IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5	= IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	= IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT7__GPIO_4_28		= IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12	= IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18	= IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8	= IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT8__LCDIF_DAT_8		= IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT8__PWM1_PWMO		= IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B	= IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	= IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT8__GPIO_4_29		= IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13	= IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19	= IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9	= IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+	MX6_PAD_DISP0_DAT9__LCDIF_DAT_9		= IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT9__PWM2_PWMO		= IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B	= IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	= IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT9__GPIO_4_30		= IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14	= IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20	= IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A0__MMDC_DRAM_A_0		= IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A1__MMDC_DRAM_A_1		= IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A10__MMDC_DRAM_A_10	= IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A11__MMDC_DRAM_A_11	= IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A12__MMDC_DRAM_A_12	= IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A13__MMDC_DRAM_A_13	= IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A14__MMDC_DRAM_A_14	= IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A15__MMDC_DRAM_A_15	= IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A2__MMDC_DRAM_A_2		= IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A3__MMDC_DRAM_A_3		= IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A4__MMDC_DRAM_A_4		= IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A5__MMDC_DRAM_A_5		= IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A6__MMDC_DRAM_A_6		= IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A7__MMDC_DRAM_A_7		= IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A8__MMDC_DRAM_A_8		= IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_A9__MMDC_DRAM_A_9		= IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS		= IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0	= IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1	= IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D0__MMDC_DRAM_D_0		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D1__MMDC_DRAM_D_1		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D10__MMDC_DRAM_D_10	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D11__MMDC_DRAM_D_11	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D12__MMDC_DRAM_D_12	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D13__MMDC_DRAM_D_13	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D14__MMDC_DRAM_D_14	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D15__MMDC_DRAM_D_15	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D16__MMDC_DRAM_D_16	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D17__MMDC_DRAM_D_17	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D18__MMDC_DRAM_D_18	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D19__MMDC_DRAM_D_19	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D2__MMDC_DRAM_D_2		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D20__MMDC_DRAM_D_20	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D21__MMDC_DRAM_D_21	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D22__MMDC_DRAM_D_22	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D23__MMDC_DRAM_D_23	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D24__MMDC_DRAM_D_24	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D25__MMDC_DRAM_D_25	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D26__MMDC_DRAM_D_26	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D27__MMDC_DRAM_D_27	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D28__MMDC_DRAM_D_28	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D29__MMDC_DRAM_D_29	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D3__MMDC_DRAM_D_3		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D30__MMDC_DRAM_D_30	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D31__MMDC_DRAM_D_31	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D32__MMDC_DRAM_D_32	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D33__MMDC_DRAM_D_33	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D34__MMDC_DRAM_D_34	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D35__MMDC_DRAM_D_35	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D36__MMDC_DRAM_D_36	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D37__MMDC_DRAM_D_37	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D38__MMDC_DRAM_D_38	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D39__MMDC_DRAM_D_39	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D4__MMDC_DRAM_D_4		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D40__MMDC_DRAM_D_40	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D41__MMDC_DRAM_D_41	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D42__MMDC_DRAM_D_42	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D43__MMDC_DRAM_D_43	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D44__MMDC_DRAM_D_44	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D45__MMDC_DRAM_D_45	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D46__MMDC_DRAM_D_46	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D47__MMDC_DRAM_D_47	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D48__MMDC_DRAM_D_48	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D49__MMDC_DRAM_D_49	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D5__MMDC_DRAM_D_5		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D50__MMDC_DRAM_D_50	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D51__MMDC_DRAM_D_51	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D52__MMDC_DRAM_D_52	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D53__MMDC_DRAM_D_53	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D54__MMDC_DRAM_D_54	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D55__MMDC_DRAM_D_55	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D56__MMDC_DRAM_D_56	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D57__MMDC_DRAM_D_57	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D58__MMDC_DRAM_D_58	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D59__MMDC_DRAM_D_59	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D6__MMDC_DRAM_D_6		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D60__MMDC_DRAM_D_60	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D61__MMDC_DRAM_D_61	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D62__MMDC_DRAM_D_62	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D63__MMDC_DRAM_D_63	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D7__MMDC_DRAM_D_7		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D8__MMDC_DRAM_D_8		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_D9__MMDC_DRAM_D_9		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0	= IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1	= IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2	= IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3	= IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4	= IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5	= IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6	= IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7	= IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS		= IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET	= IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0	= IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1	= IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2	= IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0	= IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1	= IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0	= IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1	= IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0	= IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1	= IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0	= IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1	= IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2	= IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3	= IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4	= IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5	= IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6	= IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7	= IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE	= IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__WEIM_WEIM_A_16		= IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK	= IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK	= IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0),
+	MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23	= IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__GPIO_2_22		= IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__TPSMP_HDATA_6		= IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__SRC_BT_CFG_16		= IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A16__EPDC_SDDO_0		= IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__WEIM_WEIM_A_17		= IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12	= IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__IPU1_CSI1_D_12		= IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0),
+	MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22	= IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__GPIO_2_21		= IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__TPSMP_HDATA_5		= IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__SRC_BT_CFG_17		= IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A17__EPDC_PWRSTAT		= IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__WEIM_WEIM_A_18		= IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13	= IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__IPU1_CSI1_D_13		= IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0),
+	MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21	= IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__GPIO_2_20		= IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__TPSMP_HDATA_4		= IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__SRC_BT_CFG_18		= IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A18__EPDC_PWRCTRL_0		= IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__WEIM_WEIM_A_19		= IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14	= IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__IPU1_CSI1_D_14		= IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0),
+	MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20	= IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__GPIO_2_19		= IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__TPSMP_HDATA_3		= IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__SRC_BT_CFG_19		= IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A19__EPDC_PWRCTRL_1		= IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__WEIM_WEIM_A_20		= IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15	= IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__IPU1_CSI1_D_15		= IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0),
+	MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19	= IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__GPIO_2_18		= IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__TPSMP_HDATA_2		= IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__SRC_BT_CFG_20		= IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A20__EPDC_PWRCTRL_2		= IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__WEIM_WEIM_A_21		= IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16	= IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__IPU1_CSI1_D_16		= IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0),
+	MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18	= IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__GPIO_2_17		= IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__TPSMP_HDATA_1		= IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__SRC_BT_CFG_21		= IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A21__EPDC_GDCLK		= IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A22__WEIM_WEIM_A_22		= IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17	= IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A22__IPU1_CSI1_D_17		= IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0),
+	MX6_PAD_EIM_A22__GPIO_2_16		= IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A22__TPSMP_HDATA_0		= IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A22__SRC_BT_CFG_22		= IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A22__EPDC_GDSP		= IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__WEIM_WEIM_A_23		= IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18	= IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__IPU1_CSI1_D_18		= IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0),
+	MX6_PAD_EIM_A23__IPU1_SISG_3		= IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__GPIO_6_6		= IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3	= IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__SRC_BT_CFG_23		= IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A23__EPDC_GDOE		= IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__WEIM_WEIM_A_24		= IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19	= IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__IPU1_CSI1_D_19		= IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0),
+	MX6_PAD_EIM_A24__IPU1_SISG_2		= IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__GPIO_5_4		= IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2	= IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__SRC_BT_CFG_24		= IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A24__EPDC_GDRL		= IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__WEIM_WEIM_A_25		= IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__ECSPI4_SS1		= IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__ECSPI2_RDY		= IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__IPU1_DI1_PIN12		= IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__IPU1_DI0_D1_CS		= IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__GPIO_5_2		= IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE	= IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0),
+	MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0	= IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__EPDC_SDDO_15		= IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN	= IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0),
+	MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK	= IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16	= IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_BCLK__GPIO_6_31		= IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_BCLK__TPSMP_HDATA_31	= IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_BCLK__EPDC_SDCE_9		= IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0		= IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS0__IPU1_DI1_PIN5		= IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS0__ECSPI2_SCLK		= IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0),
+	MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24	= IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS0__GPIO_2_23		= IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS0__TPSMP_HDATA_7		= IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS0__EPDC_SDDO_6		= IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1		= IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS1__IPU1_DI1_PIN6		= IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS1__ECSPI2_MOSI		= IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0),
+	MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25	= IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS1__GPIO_2_24		= IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS1__TPSMP_HDATA_8		= IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_CS1__EPDC_SDDO_8		= IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D16__WEIM_WEIM_D_16		= IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0),
 	MX6_PAD_EIM_D16__ECSPI1_SCLK		= IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+	MX6_PAD_EIM_D16__IPU1_DI0_PIN5		= IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D16__IPU1_CSI1_D_18		= IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0),
+	MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA	= IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0),
+	MX6_PAD_EIM_D16__GPIO_3_16		= IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D16__I2C2_SDA		= IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0),
+	MX6_PAD_EIM_D16__TPSMP_HTRANS_0		= IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D16__EPDC_SDDO_10		= IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D17__WEIM_WEIM_D_17		= IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0),
 	MX6_PAD_EIM_D17__ECSPI1_MISO		= IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+	MX6_PAD_EIM_D17__IPU1_DI0_PIN6		= IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK	= IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0),
+	MX6_PAD_EIM_D17__DCIC1_DCIC_OUT		= IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D17__GPIO_3_17		= IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D17__I2C3_SCL		= IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0),
+	MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1	= IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D17__EPDC_VCOM_0		= IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D18__WEIM_WEIM_D_18		= IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0),
 	MX6_PAD_EIM_D18__ECSPI1_MOSI		= IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+	MX6_PAD_EIM_D18__IPU1_DI0_PIN7		= IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D18__IPU1_CSI1_D_17		= IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0),
+	MX6_PAD_EIM_D18__IPU1_DI1_D0_CS		= IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D18__GPIO_3_18		= IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D18__I2C3_SDA		= IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0),
+	MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2	= IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D18__EPDC_VCOM_1		= IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__WEIM_WEIM_D_19		= IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__ECSPI1_SS1		= IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0),
+	MX6_PAD_EIM_D19__IPU1_DI0_PIN8		= IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__IPU1_CSI1_D_16		= IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0),
+	MX6_PAD_EIM_D19__UART1_CTS		= IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__UART1_RTS		= IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0),
 	MX6_PAD_EIM_D19__GPIO_3_19		= IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__EPIT1_EPITO		= IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP	= IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D19__EPDC_SDDO_12		= IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D20__WEIM_WEIM_D_20		= IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D20__ECSPI4_SS0		= IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0),
+	MX6_PAD_EIM_D20__IPU1_DI0_PIN16		= IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D20__IPU1_CSI1_D_15		= IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0),
+	MX6_PAD_EIM_D20__UART1_CTS		= IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D20__UART1_RTS		= IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0),
+	MX6_PAD_EIM_D20__GPIO_3_20		= IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D20__EPIT2_EPITO		= IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D20__TPSMP_HTRANS_1		= IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D21__WEIM_WEIM_D_21		= IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D21__ECSPI4_SCLK		= IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D21__IPU1_DI0_PIN17		= IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D21__IPU1_CSI1_D_11		= IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0),
+	MX6_PAD_EIM_D21__USBOH3_USBOTG_OC	= IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0),
 	MX6_PAD_EIM_D21__GPIO_3_21		= IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
 	MX6_PAD_EIM_D21__I2C1_SCL		= IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+	MX6_PAD_EIM_D21__SPDIF_IN1		= IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0),
+	MX6_PAD_EIM_D22__WEIM_WEIM_D_22		= IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__ECSPI4_MISO		= IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__IPU1_DI0_PIN1		= IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__IPU1_CSI1_D_10		= IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0),
+	MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR	= IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__GPIO_3_22		= IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__SPDIF_OUT1		= IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE	= IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D22__EPDC_SDCE_6		= IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__WEIM_WEIM_D_23		= IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__IPU1_DI0_D0_CS		= IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__UART3_CTS		= IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__UART3_RTS		= IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0),
+	MX6_PAD_EIM_D23__UART1_DCD		= IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN	= IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0),
 	MX6_PAD_EIM_D23__GPIO_3_23		= IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__IPU1_DI1_PIN2		= IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__IPU1_DI1_PIN14		= IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D23__EPDC_SDDO_11		= IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__WEIM_WEIM_D_24		= IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__ECSPI4_SS2		= IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__UART3_TXD		= IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__UART3_RXD		= IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0),
+	MX6_PAD_EIM_D24__ECSPI1_SS2		= IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0),
+	MX6_PAD_EIM_D24__ECSPI2_SS2		= IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__GPIO_3_24		= IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0),
+	MX6_PAD_EIM_D24__UART1_DTR		= IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D24__EPDC_SDCE_7		= IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__WEIM_WEIM_D_25		= IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__ECSPI4_SS3		= IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__UART3_TXD		= IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0),
+	MX6_PAD_EIM_D25__ECSPI1_SS3		= IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0),
+	MX6_PAD_EIM_D25__ECSPI2_SS3		= IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__GPIO_3_25		= IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0),
+	MX6_PAD_EIM_D25__UART1_DSR		= IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D25__EPDC_SDCE_8		= IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__WEIM_WEIM_D_26		= IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__IPU1_DI1_PIN11		= IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__IPU1_CSI0_D_1		= IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__IPU1_CSI1_D_14		= IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0),
 	MX6_PAD_EIM_D26__UART2_TXD		= IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__UART2_RXD		= IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0),
+	MX6_PAD_EIM_D26__GPIO_3_26		= IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__IPU1_SISG_2		= IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22	= IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D26__EPDC_SDOED		= IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__WEIM_WEIM_D_27		= IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__IPU1_DI1_PIN13		= IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__IPU1_CSI0_D_0		= IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__IPU1_CSI1_D_13		= IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0),
+	MX6_PAD_EIM_D27__UART2_TXD		= IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0),
 	MX6_PAD_EIM_D27__UART2_RXD		= IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+	MX6_PAD_EIM_D27__GPIO_3_27		= IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__IPU1_SISG_3		= IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23	= IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D27__EPDC_SDOE		= IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D28__WEIM_WEIM_D_28		= IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0),
 	MX6_PAD_EIM_D28__I2C1_SDA		= IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+	MX6_PAD_EIM_D28__ECSPI4_MOSI		= IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D28__IPU1_CSI1_D_12		= IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0),
+	MX6_PAD_EIM_D28__UART2_CTS		= IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D28__UART2_RTS		= IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0),
 	MX6_PAD_EIM_D28__GPIO_3_28		= IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D28__IPU1_EXT_TRIG		= IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D28__IPU1_DI0_PIN13		= IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D28__EPDC_PWRCTRL_3		= IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D29__WEIM_WEIM_D_29		= IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D29__IPU1_DI1_PIN15		= IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D29__ECSPI4_SS0		= IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0),
+	MX6_PAD_EIM_D29__UART2_CTS		= IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D29__UART2_RTS		= IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0),
 	MX6_PAD_EIM_D29__GPIO_3_29		= IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC	= IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0),
+	MX6_PAD_EIM_D29__IPU1_DI0_PIN14		= IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D29__EPDC_PWRWAKE		= IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__WEIM_WEIM_D_30		= IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21	= IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__IPU1_DI0_PIN11		= IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__IPU1_CSI0_D_3		= IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__UART3_CTS		= IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__UART3_RTS		= IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0),
+	MX6_PAD_EIM_D30__GPIO_3_30		= IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__USBOH3_USBH1_OC	= IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0),
+	MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0	= IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D30__EPDC_SDOEZ		= IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__WEIM_WEIM_D_31		= IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20	= IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__IPU1_DI0_PIN12		= IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__IPU1_CSI0_D_2		= IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__UART3_CTS		= IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__UART3_RTS		= IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0),
+	MX6_PAD_EIM_D31__GPIO_3_31		= IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__USBOH3_USBH1_PWR	= IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1	= IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__EPDC_SDCLK		= IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN	= IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0	= IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9	= IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__IPU1_CSI1_D_9		= IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2	= IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__GPIO_3_0		= IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__TPSMP_HDATA_14		= IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__SRC_BT_CFG_0		= IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA0__EPDC_SDCLKN		= IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1	= IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8	= IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__IPU1_CSI1_D_8		= IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3	= IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE	= IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__GPIO_3_1		= IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__TPSMP_HDATA_15		= IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__SRC_BT_CFG_1		= IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA1__EPDC_SDLE		= IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10	= IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15	= IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN	= IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0),
+	MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12	= IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__GPIO_3_10		= IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__TPSMP_HDATA_24	= IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__SRC_BT_CFG_10		= IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA10__EPDC_SDDO_1		= IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11	= IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__IPU1_DI1_PIN2		= IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC	= IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0),
+	MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13	= IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6	= IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__GPIO_3_11		= IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__TPSMP_HDATA_25	= IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__SRC_BT_CFG_11		= IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA11__EPDC_SDDO_3		= IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12	= IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__IPU1_DI1_PIN3		= IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC	= IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0),
+	MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14	= IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3	= IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__GPIO_3_12		= IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__TPSMP_HDATA_26	= IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__SRC_BT_CFG_12		= IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA12__EPDC_SDDO_2		= IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13	= IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS	= IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK	= IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0),
+	MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15	= IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4	= IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__GPIO_3_13		= IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__TPSMP_HDATA_27	= IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__SRC_BT_CFG_13		= IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA13__EPDC_SDDO_13		= IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14	= IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS	= IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK	= IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16	= IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5	= IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__GPIO_3_14		= IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__TPSMP_HDATA_28	= IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__SRC_BT_CFG_14		= IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA14__EPDC_SDDO_14		= IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15	= IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__IPU1_DI1_PIN1		= IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__IPU1_DI1_PIN4		= IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17	= IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__GPIO_3_15		= IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__TPSMP_HDATA_29	= IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__SRC_BT_CFG_15		= IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA15__EPDC_SDDO_9		= IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2	= IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7	= IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__IPU1_CSI1_D_7		= IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4	= IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE	= IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__GPIO_3_2		= IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__TPSMP_HDATA_16		= IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__SRC_BT_CFG_2		= IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA2__EPDC_BDR_0		= IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3	= IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6	= IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__IPU1_CSI1_D_6		= IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5	= IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ	= IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__GPIO_3_3		= IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__TPSMP_HDATA_17		= IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__SRC_BT_CFG_3		= IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA3__EPDC_BDR_1		= IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4	= IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5	= IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__IPU1_CSI1_D_5		= IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6	= IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN	= IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__GPIO_3_4		= IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__TPSMP_HDATA_18		= IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__SRC_BT_CFG_4		= IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA4__EPDC_SDCE_0		= IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5	= IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4	= IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__IPU1_CSI1_D_4		= IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7	= IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP	= IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__GPIO_3_5		= IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__TPSMP_HDATA_19		= IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__SRC_BT_CFG_5		= IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA5__EPDC_SDCE_1		= IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6	= IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3	= IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__IPU1_CSI1_D_3		= IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8	= IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN	= IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__GPIO_3_6		= IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__TPSMP_HDATA_20		= IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__SRC_BT_CFG_6		= IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA6__EPDC_SDCE_2		= IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7	= IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2	= IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__IPU1_CSI1_D_2		= IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9	= IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__GPIO_3_7		= IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__TPSMP_HDATA_21		= IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__SRC_BT_CFG_7		= IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA7__EPDC_SDCE_3		= IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8	= IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1	= IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__IPU1_CSI1_D_1		= IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10	= IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__GPIO_3_8		= IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__TPSMP_HDATA_22		= IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__SRC_BT_CFG_8		= IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA8__EPDC_SDCE_4		= IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9	= IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0	= IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__IPU1_CSI1_D_0		= IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11	= IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0),
 	MX6_PAD_EIM_DA9__GPIO_3_9		= IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__TPSMP_HDATA_23		= IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__SRC_BT_CFG_9		= IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__EPDC_SDCE_5		= IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0		= IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11	= IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__IPU1_CSI1_D_11		= IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0),
+	MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0	= IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__CCM_PMIC_RDY		= IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0),
+	MX6_PAD_EIM_EB0__GPIO_2_28		= IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__TPSMP_HDATA_12		= IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__SRC_BT_CFG_27		= IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB0__EPDC_PWRCOM		= IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1		= IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10	= IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__IPU1_CSI1_D_10		= IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0),
+	MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1	= IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__GPIO_2_29		= IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__TPSMP_HDATA_13		= IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__SRC_BT_CFG_28		= IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB1__EPDC_SDSHR		= IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2		= IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB2__ECSPI1_SS0		= IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0),
+	MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK	= IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0),
+	MX6_PAD_EIM_EB2__IPU1_CSI1_D_19		= IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0),
+	MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL	= IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0),
+	MX6_PAD_EIM_EB2__GPIO_2_30		= IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB2__I2C2_SCL		= IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0),
+	MX6_PAD_EIM_EB2__SRC_BT_CFG_30		= IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB2__EPDC_SDDO_5		= IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3		= IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__ECSPI4_RDY		= IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__UART3_CTS		= IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__UART3_RTS		= IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0),
+	MX6_PAD_EIM_EB3__UART1_RI		= IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC	= IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0),
+	MX6_PAD_EIM_EB3__GPIO_2_31		= IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__IPU1_DI1_PIN3		= IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__SRC_BT_CFG_31		= IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__EPDC_SDCE_0		= IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN	= IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0),
+	MX6_PAD_EIM_LBA__WEIM_WEIM_LBA		= IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_LBA__IPU1_DI1_PIN17		= IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_LBA__ECSPI2_SS1		= IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0),
+	MX6_PAD_EIM_LBA__GPIO_2_27		= IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_LBA__TPSMP_HDATA_11		= IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_LBA__SRC_BT_CFG_26		= IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_LBA__EPDC_SDDO_4		= IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_OE__WEIM_WEIM_OE		= IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_OE__IPU1_DI1_PIN7		= IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_OE__ECSPI2_MISO		= IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0),
+	MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26	= IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_OE__GPIO_2_25		= IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_OE__TPSMP_HDATA_9		= IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_OE__EPDC_PWRIRQ		= IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__WEIM_WEIM_RW		= IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__IPU1_DI1_PIN8		= IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__ECSPI2_SS0		= IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0),
+	MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27	= IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__GPIO_2_26		= IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__TPSMP_HDATA_10		= IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__SRC_BT_CFG_29		= IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0),
+	MX6_PAD_EIM_RW__EPDC_SDDO_7		= IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0),
+	MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT	= IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0),
+	MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B	= IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0),
+	MX6_PAD_EIM_WAIT__GPIO_5_0		= IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_WAIT__TPSMP_HDATA_30	= IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0),
+	MX6_PAD_EIM_WAIT__SRC_BT_CFG_25		= IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		= IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0),
+	MX6_PAD_ENET_CRS_DV__ESAI1_SCKT		= IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0),
+	MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK	= IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0),
+	MX6_PAD_ENET_CRS_DV__GPIO_1_25		= IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_CRS_DV__PHY_TDO		= IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD	= IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_MDC__MLB_MLBDAT		= IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0),
 	MX6_PAD_ENET_MDC__ENET_MDC		= IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0,  0),
+	MX6_PAD_ENET_MDC__ESAI1_TX5_RX0		= IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0),
+	MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN	= IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET_MDC__GPIO_1_31		= IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET	= IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0),
 	MX6_PAD_ENET_MDIO__ENET_MDIO		= IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+	MX6_PAD_ENET_MDIO__ESAI1_SCKR		= IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0),
+	MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3	= IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0),
+	MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT	= IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET_MDIO__GPIO_1_22		= IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_MDIO__SPDIF_PLOCK		= IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	= IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET_REF_CLK__ESAI1_FSR		= IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0),
+	MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	= IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0),
+	MX6_PAD_ENET_REF_CLK__GPIO_1_23		= IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK	= IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH	= IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID	= IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0),
+	MX6_PAD_ENET_RX_ER__ENET_RX_ER		= IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET_RX_ER__ESAI1_HCKR		= IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0),
+	MX6_PAD_ENET_RX_ER__SPDIF_IN1		= IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0),
+	MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT	= IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET_RX_ER__GPIO_1_24		= IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_RX_ER__PHY_TDI		= IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD	= IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD0__OSC32K_32K_OUT	= IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD0__ENET_RDATA_0		= IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0),
+	MX6_PAD_ENET_RXD0__ESAI1_HCKT		= IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0),
+	MX6_PAD_ENET_RXD0__SPDIF_OUT1		= IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
 	MX6_PAD_ENET_RXD0__GPIO_1_27		= IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD0__PHY_TMS		= IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV	= IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD1__MLB_MLBSIG		= IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0),
+	MX6_PAD_ENET_RXD1__ENET_RDATA_1		= IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0),
+	MX6_PAD_ENET_RXD1__ESAI1_FST		= IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0),
+	MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT	= IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD1__GPIO_1_26		= IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD1__PHY_TCK		= IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET	= IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_TX_EN__ENET_TX_EN		= IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2	= IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0),
+	MX6_PAD_ENET_TX_EN__GPIO_1_28		= IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH	= IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_TX_EN__I2C4_SCL		= IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0),
+	MX6_PAD_ENET_TXD0__ENET_TDATA_0		= IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1	= IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0),
+	MX6_PAD_ENET_TXD0__GPIO_1_30		= IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD	= IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD1__MLB_MLBCLK		= IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0),
+	MX6_PAD_ENET_TXD1__ENET_TDATA_1		= IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3	= IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0),
+	MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN	= IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD1__GPIO_1_29		= IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD	= IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
+	MX6_PAD_ENET_TXD1__I2C4_SDA		= IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0),
+	MX6_PAD_GPIO_0__CCM_CLKO		= IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO_0__KPP_COL_5		= IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0),
+	MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0),
+	MX6_PAD_GPIO_0__EPIT1_EPITO		= IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_0__GPIO_1_0		= IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_0__USBOH3_USBH1_PWR	= IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5	= IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_1__ESAI1_SCKR		= IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0),
+	MX6_PAD_GPIO_1__WDOG2_WDOG_B		= IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_1__KPP_ROW_5		= IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0),
+	MX6_PAD_GPIO_1__USBOTG_ID		= IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
+	MX6_PAD_GPIO_1__PWM2_PWMO		= IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_1__GPIO_1_1		= IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_1__USDHC1_CD		= IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_1__SRC_TESTER_ACK		= IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_16__ESAI1_TX3_RX2		= IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0),
+	MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN	= IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT	= IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0),
+	MX6_PAD_GPIO_16__USDHC1_LCTL		= IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_16__SPDIF_IN1		= IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0),
 	MX6_PAD_GPIO_16__GPIO_7_11		= IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_16__I2C3_SDA		= IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+	MX6_PAD_GPIO_16__SJC_DE_B		= IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_17__ESAI1_TX0		= IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0),
+	MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN	= IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_17__CCM_PMIC_RDY		= IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0),
+	MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0	= IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0),
+	MX6_PAD_GPIO_17__SPDIF_OUT1		= IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO_17__GPIO_7_12		= IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_17__SJC_JTAG_ACT		= IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_18__ESAI1_TX1		= IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0),
+	MX6_PAD_GPIO_18__ENET_RX_CLK		= IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0),
+	MX6_PAD_GPIO_18__USDHC3_VSELECT		= IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1	= IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0),
+	MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0),
 	MX6_PAD_GPIO_18__GPIO_7_13		= IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL	= IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_18__SRC_SYSTEM_RST		= IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_19__KPP_COL_5		= IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0),
+	MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT	= IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_19__SPDIF_OUT1		= IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO_19__CCM_CLKO		= IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_19__ECSPI1_RDY		= IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO_19__GPIO_4_5		= IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_19__ENET_TX_ER		= IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_19__SRC_INT_BOOT		= IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_2__ESAI1_FST		= IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0),
+	MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	= IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_2__KPP_ROW_6		= IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0),
+	MX6_PAD_GPIO_2__CCM_CCM_OUT_1		= IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0	= IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO_2__GPIO_1_2		= IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_2__USDHC2_WP		= IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_2__MLB_MLBDAT		= IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0),
+	MX6_PAD_GPIO_3__ESAI1_HCKR		= IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0),
+	MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	= IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_3__I2C3_SCL		= IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0),
+	MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT	= IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_3__CCM_CLKO2		= IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_3__GPIO_1_3		= IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_3__USBOH3_USBH1_OC		= IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0),
+	MX6_PAD_GPIO_3__MLB_MLBCLK		= IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0),
+	MX6_PAD_GPIO_4__ESAI1_HCKT		= IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0),
+	MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	= IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_4__KPP_COL_7		= IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0),
+	MX6_PAD_GPIO_4__CCM_CCM_OUT_2		= IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1	= IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_4__GPIO_1_4		= IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_4__USDHC2_CD		= IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED	= IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_5__ESAI1_TX2_RX3		= IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0),
+	MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	= IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_5__KPP_ROW_7		= IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0),
+	MX6_PAD_GPIO_5__CCM_CLKO		= IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2	= IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO_5__GPIO_1_5		= IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_5__I2C3_SCL		= IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+	MX6_PAD_GPIO_5__SIMBA_EVENTI		= IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_6__ESAI1_SCKT		= IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0),
+	MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	= IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_6__I2C3_SDA		= IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0),
+	MX6_PAD_GPIO_6__CCM_CCM_OUT_0		= IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_6__CSU_CSU_INT_DEB		= IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_6__GPIO_1_6		= IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_6__USDHC2_LCTL		= IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_6__MLB_MLBSIG		= IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0),
+	MX6_PAD_GPIO_7__ESAI1_TX4_RX1		= IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0),
+	MX6_PAD_GPIO_7__EPIT1_EPITO		= IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO_7__CAN1_TXCAN		= IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_7__UART2_TXD		= IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_7__UART2_RXD		= IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0),
+	MX6_PAD_GPIO_7__GPIO_1_7		= IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_7__SPDIF_PLOCK		= IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE	= IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_7__I2C4_SCL		= IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0),
+	MX6_PAD_GPIO_8__ESAI1_TX5_RX0		= IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0),
+	MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT	= IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_8__EPIT2_EPITO		= IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO_8__CAN1_RXCAN		= IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0),
+	MX6_PAD_GPIO_8__UART2_TXD		= IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_8__UART2_RXD		= IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0),
+	MX6_PAD_GPIO_8__GPIO_1_8		= IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_8__SPDIF_SRCLK		= IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP	= IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO_8__I2C4_SDA		= IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0),
+	MX6_PAD_GPIO_9__ESAI1_FSR		= IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0),
+	MX6_PAD_GPIO_9__WDOG1_WDOG_B		= IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO_9__KPP_COL_6		= IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0),
+	MX6_PAD_GPIO_9__CCM_REF_EN_B		= IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO_9__PWM1_PWMO		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO_9__GPIO_1_9		= IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_9__USDHC1_WP		= IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0),
+	MX6_PAD_GPIO_9__SRC_EARLY_RST		= IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__SJC_MOD		= IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__SJC_TCK		= IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__SJC_TDI		= IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__SJC_TDO		= IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__SJC_TMS		= IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRSTB__SJC_TRSTB		= IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL0__ECSPI1_SCLK		= IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0),
+	MX6_PAD_KEY_COL0__ENET_RDATA_3		= IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0),
+	MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0),
+	MX6_PAD_KEY_COL0__KPP_COL_0		= IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL0__UART4_TXD		= IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL0__UART4_RXD		= IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0),
+	MX6_PAD_KEY_COL0__GPIO_4_6		= IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT	= IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL0__SRC_ANY_PU_RST	= IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL1__ECSPI1_MISO		= IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0),
+	MX6_PAD_KEY_COL1__ENET_MDIO		= IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0),
+	MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0),
+	MX6_PAD_KEY_COL1__KPP_COL_1		= IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL1__UART5_TXD		= IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL1__UART5_RXD		= IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0),
+	MX6_PAD_KEY_COL1__GPIO_4_8		= IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL1__USDHC1_VSELECT	= IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1	= IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL2__ECSPI1_SS1		= IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0),
+	MX6_PAD_KEY_COL2__ENET_RDATA_2		= IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0),
+	MX6_PAD_KEY_COL2__CAN1_TXCAN		= IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL2__KPP_COL_2		= IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL2__ENET_MDC		= IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL2__GPIO_4_10		= IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP	= IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3	= IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL3__ECSPI1_SS3		= IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0),
+	MX6_PAD_KEY_COL3__ENET_CRS		= IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL	= IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0),
+	MX6_PAD_KEY_COL3__KPP_COL_3		= IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0),
 	MX6_PAD_KEY_COL3__I2C2_SCL		= IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
 	MX6_PAD_KEY_COL3__GPIO_4_12		= IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL3__SPDIF_IN1		= IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0),
+	MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5	= IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__CAN2_TXCAN		= IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__IPU1_SISG_4		= IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC	= IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0),
+	MX6_PAD_KEY_COL4__KPP_COL_4		= IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__UART5_CTS		= IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__UART5_RTS		= IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0),
+	MX6_PAD_KEY_COL4__GPIO_4_14		= IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49	= IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7	= IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW0__ECSPI1_MOSI		= IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0),
+	MX6_PAD_KEY_ROW0__ENET_TDATA_3		= IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0),
+	MX6_PAD_KEY_ROW0__KPP_ROW_0		= IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW0__UART4_TXD		= IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW0__UART4_RXD		= IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0),
+	MX6_PAD_KEY_ROW0__GPIO_4_7		= IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0	= IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__ECSPI1_SS0		= IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0),
+	MX6_PAD_KEY_ROW1__ENET_COL		= IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0),
+	MX6_PAD_KEY_ROW1__KPP_ROW_1		= IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__UART5_TXD		= IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__UART5_RXD		= IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0),
+	MX6_PAD_KEY_ROW1__GPIO_4_9		= IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__USDHC2_VSELECT	= IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2	= IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW2__ECSPI1_SS2		= IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0),
+	MX6_PAD_KEY_ROW2__ENET_TDATA_2		= IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW2__CAN1_RXCAN		= IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0),
+	MX6_PAD_KEY_ROW2__KPP_ROW_2		= IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW2__USDHC2_VSELECT	= IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW2__GPIO_4_11		= IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	= IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0),
+	MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4	= IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW3__OSC32K_32K_OUT	= IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0),
+	MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA	= IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0),
+	MX6_PAD_KEY_ROW3__KPP_ROW_3		= IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0),
 	MX6_PAD_KEY_ROW3__I2C2_SDA		= IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
 	MX6_PAD_KEY_ROW3__GPIO_4_13		= IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW3__USDHC1_VSELECT	= IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6	= IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__CAN2_RXCAN		= IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0),
+	MX6_PAD_KEY_ROW4__IPU1_SISG_5		= IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR	= IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__KPP_ROW_4		= IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__UART5_CTS		= IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__UART5_RTS		= IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0),
+	MX6_PAD_KEY_ROW4__GPIO_4_15		= IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50	= IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8	= IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0),
+	MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__RAWNAND_ALE		= IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__USDHC4_RST		= IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0	= IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12	= IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12	= IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__GPIO_6_8		= IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24	= IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_ALE__USDHC3_CLKI		= IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0),
+	MX6_PAD_NANDF_CLE__RAWNAND_CLE		= IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31	= IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11	= IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11	= IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CLE__GPIO_6_7		= IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23	= IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CLE__USDHC3_CLKO		= IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS0__RAWNAND_CE0N		= IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15	= IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15	= IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS0__GPIO_6_11		= IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS0__USDHC1_CLKO		= IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS1__RAWNAND_CE1N		= IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS1__USDHC4_VSELECT	= IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS1__USDHC3_VSELECT	= IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3	= IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_CS1__GPIO_6_14		= IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT	= IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS1__USDHC1_CLKI		= IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0),
+	MX6_PAD_NANDF_CS2__RAWNAND_CE2N		= IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS2__IPU1_SISG_0		= IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS2__ESAI1_TX0		= IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0),
+	MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE	= IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS2__CCM_CLKO2		= IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_CS2__GPIO_6_15		= IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS2__USDHC2_CLKO		= IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS3__RAWNAND_CE3N		= IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS3__IPU1_SISG_1		= IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS3__ESAI1_TX1		= IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0),
+	MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26	= IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4	= IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_CS3__GPIO_6_16		= IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS3__TPSMP_CLK		= IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0),
+	MX6_PAD_NANDF_CS3__USDHC2_CLKI		= IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0),
+	MX6_PAD_NANDF_CS3__I2C4_SDA		= IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0),
+	MX6_PAD_NANDF_D0__RAWNAND_D0		= IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D0__USDHC1_DAT4		= IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0	= IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16	= IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16	= IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D0__GPIO_2_0		= IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0	= IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D1__RAWNAND_D1		= IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D1__USDHC1_DAT5		= IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1	= IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17	= IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17	= IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_D1__GPIO_2_1		= IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1	= IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D2__RAWNAND_D2		= IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D2__USDHC1_DAT6		= IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2	= IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18	= IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18	= IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_D2__GPIO_2_2		= IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2	= IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D3__RAWNAND_D3		= IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D3__USDHC1_DAT7		= IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3	= IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19	= IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19	= IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_D3__GPIO_2_3		= IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3	= IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D4__RAWNAND_D4		= IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D4__USDHC2_DAT4		= IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4	= IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20	= IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20	= IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_D4__GPIO_2_4		= IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4	= IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__RAWNAND_D5		= IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__USDHC2_DAT5		= IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5	= IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21	= IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21	= IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__GPIO_2_5		= IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5	= IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D6__RAWNAND_D6		= IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D6__USDHC2_DAT6		= IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6	= IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22	= IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22	= IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0),
 	MX6_PAD_NANDF_D6__GPIO_2_6		= IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0     = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+	MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6	= IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__RAWNAND_D7		= IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__USDHC2_DAT7		= IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7	= IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23	= IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23	= IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__GPIO_2_7		= IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7	= IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__RAWNAND_READY0	= IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2	= IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14	= IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14	= IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__GPIO_6_10		= IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33	= IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_RB0__USDHC4_CLKI		= IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0),
+	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	= IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1	= IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13	= IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13	= IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__GPIO_6_9		= IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32	= IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__USDHC4_CLKO		= IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0),
+	MX6_PAD_NANDF_WP_B__I2C4_SCL		= IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0),
+	MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_POR_B__SRC_POR_B		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_RESET_IN_B__SRC_RESET_B		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY	= IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	= IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
 	MX6_PAD_RGMII_RD0__GPIO_6_25		= IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6	= IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG	= IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	= IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
 	MX6_PAD_RGMII_RD1__GPIO_6_27		= IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8	= IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD1__SJC_FAIL		= IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA	= IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	= IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
 	MX6_PAD_RGMII_RD2__GPIO_6_28		= IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9	= IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE	= IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	= IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
 	MX6_PAD_RGMII_RD3__GPIO_6_29		= IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10	= IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA	= IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	= IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
-	MX6_PAD_RGMII_RX_CTL__GPIO_6_24	= IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RX_CTL__GPIO_6_24		= IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5	= IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE	= IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START	= IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP),
 	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	= IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
 	MX6_PAD_RGMII_RXC__GPIO_6_30		= IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11	= IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY	= IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	= IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD0__GPIO_6_20		= IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1	= IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG	= IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	= IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD1__GPIO_6_21		= IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2	= IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD1__CCM_PLL3_BYP		= IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA	= IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	= IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD2__GPIO_6_22		= IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3	= IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD2__CCM_PLL2_BYP		= IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE	= IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	= IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD3__GPIO_6_23		= IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4	= IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE	= IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START	= IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	= IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TX_CTL__GPIO_6_26		= IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7	= IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT	= IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0),
+	MX6_PAD_RGMII_TXC__USBOH3_H2_DATA	= IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	= IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK	= IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0),
+	MX6_PAD_RGMII_TXC__GPIO_6_19		= IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0	= IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT	= IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
 	MX6_PAD_SD1_CLK__USDHC1_CLK		= IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
+	MX6_PAD_SD1_CLK__OSC32K_32K_OUT		= IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPT_CLKIN		= IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPIO_1_20		= IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__PHY_DTB_0		= IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
 	MX6_PAD_SD1_CMD__USDHC1_CMD		= IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__PWM4_PWMO		= IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__GPT_CMPOUT1		= IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
 	MX6_PAD_SD1_CMD__GPIO_1_18		= IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__GPIO_1_21		= IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5	= IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT0__USDHC1_DAT0		= IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS	= IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__GPT_CAPIN1		= IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8	= IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__GPIO_1_16		= IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1	= IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7	= IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT1__USDHC1_DAT1		= IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__PWM3_PWMO		= IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__GPT_CAPIN2		= IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7	= IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__GPIO_1_17		= IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0	= IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8	= IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT2__USDHC1_DAT2		= IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__GPT_CMPOUT2		= IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__PWM2_PWMO		= IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__WDOG1_WDOG_B		= IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__GPIO_1_19		= IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4	= IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT3__USDHC1_DAT3		= IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__GPT_CMPOUT3		= IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__PWM1_PWMO		= IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__WDOG2_WDOG_B		= IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__GPIO_1_21		= IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6	= IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
+	MX6_PAD_SD2_CLK__USDHC2_CLK		= IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0),
+	MX6_PAD_SD2_CLK__KPP_COL_5		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0),
+	MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS	= IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0),
+	MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9	= IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_CLK__GPIO_1_10		= IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_CLK__PHY_DTB_1		= IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__USDHC2_CMD		= IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__KPP_ROW_5		= IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0),
+	MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC	= IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0),
+	MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10	= IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__GPIO_1_11		= IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0		= IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0),
+	MX6_PAD_SD2_DAT0__KPP_ROW_7		= IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0),
+	MX6_PAD_SD2_DAT0__GPIO_1_15		= IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2	= IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2	= IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0),
+	MX6_PAD_SD2_DAT1__KPP_COL_7		= IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0),
+	MX6_PAD_SD2_DAT1__GPIO_1_14		= IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__CCM_WAIT		= IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0	= IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2		= IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3	= IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0),
+	MX6_PAD_SD2_DAT2__KPP_ROW_6		= IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0),
+	MX6_PAD_SD2_DAT2__GPIO_1_13		= IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__CCM_STOP		= IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1	= IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3		= IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__KPP_COL_6		= IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0),
+	MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0),
+	MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11	= IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__GPIO_1_12		= IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__SJC_DONE		= IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3	= IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
 	MX6_PAD_SD3_CLK__USDHC3_CLK		= IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+	MX6_PAD_SD3_CLK__UART2_CTS		= IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__UART2_RTS		= IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0),
+	MX6_PAD_SD3_CLK__CAN1_RXCAN		= IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0),
+	MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5	= IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5	= IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__GPIO_7_3		= IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17	= IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14	= IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
 	MX6_PAD_SD3_CMD__USDHC3_CMD		= IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__UART2_CTS		= IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__UART2_RTS		= IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0),
+	MX6_PAD_SD3_CMD__CAN1_TXCAN		= IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4	= IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4	= IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__GPIO_7_2		= IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16	= IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13	= IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT0__USDHC3_DAT0		= IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__UART1_CTS		= IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__UART1_RTS		= IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0),
+	MX6_PAD_SD3_DAT0__CAN2_TXCAN		= IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6	= IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6	= IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__GPIO_7_4		= IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18	= IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15	= IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT1__USDHC3_DAT1		= IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__UART1_CTS		= IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__UART1_RTS		= IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0),
+	MX6_PAD_SD3_DAT1__CAN2_RXCAN		= IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0),
+	MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7	= IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7	= IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__GPIO_7_5		= IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19	= IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0	= IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT2__USDHC3_DAT2		= IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28	= IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8	= IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8	= IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__GPIO_7_6		= IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20	= IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1	= IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT3__USDHC3_DAT3		= IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__UART3_CTS		= IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__UART3_RTS		= IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0),
+	MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29	= IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9	= IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9	= IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__GPIO_7_7		= IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21	= IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2	= IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__USDHC3_DAT4		= IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__UART2_TXD		= IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__UART2_RXD		= IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0),
+	MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27	= IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3	= IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3	= IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__GPIO_7_1		= IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15	= IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12	= IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__USDHC3_DAT5		= IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__UART2_TXD		= IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__UART2_RXD		= IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0),
+	MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26	= IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2	= IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2	= IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT5__GPIO_7_0		= IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14	= IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11	= IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__USDHC3_DAT6		= IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__UART1_TXD		= IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT6__UART1_RXD		= IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+	MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25	= IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1	= IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1	= IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__GPIO_6_18		= IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13	= IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10	= IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__USDHC3_DAT7		= IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT7__UART1_TXD		= IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__UART1_RXD		= IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0),
+	MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24	= IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0	= IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0	= IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__GPIO_6_17		= IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12	= IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV	= IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__USDHC3_RST		= IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__UART3_CTS		= IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__UART3_RTS		= IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0),
+	MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30	= IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10	= IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10	= IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__GPIO_7_8		= IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22	= IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
+	MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3	= IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
 	MX6_PAD_SD4_CLK__USDHC4_CLK		= IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+	MX6_PAD_SD4_CLK__RAWNAND_WRN		= IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_CLK__UART3_TXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_CLK__UART3_RXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0),
+	MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6	= IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_CLK__GPIO_7_10		= IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
 	MX6_PAD_SD4_CMD__USDHC4_CMD		= IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6_PAD_SD4_CMD__RAWNAND_RDN		= IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_CMD__UART3_TXD		= IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_CMD__UART3_RXD		= IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0),
+	MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5	= IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_CMD__GPIO_7_9		= IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT0__RAWNAND_D8		= IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
 	MX6_PAD_SD4_DAT0__USDHC4_DAT0		= IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT0__RAWNAND_DQS		= IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24	= IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24	= IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT0__GPIO_2_8		= IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8	= IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT1__RAWNAND_D9		= IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
 	MX6_PAD_SD4_DAT1__USDHC4_DAT1		= IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT1__PWM3_PWMO		= IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25	= IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25	= IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT1__GPIO_2_9		= IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9	= IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT2__RAWNAND_D10		= IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0),
 	MX6_PAD_SD4_DAT2__USDHC4_DAT2		= IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT2__PWM4_PWMO		= IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26	= IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26	= IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT2__GPIO_2_10		= IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10	= IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT3__RAWNAND_D11		= IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
 	MX6_PAD_SD4_DAT3__USDHC4_DAT3		= IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27	= IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27	= IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT3__GPIO_2_11		= IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11	= IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__RAWNAND_D12		= IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__USDHC4_DAT4		= IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__UART2_TXD		= IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__UART2_RXD		= IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0),
+	MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28	= IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28	= IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__GPIO_2_12		= IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12	= IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__RAWNAND_D13		= IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__USDHC4_DAT5		= IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__UART2_CTS		= IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__UART2_RTS		= IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0),
+	MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29	= IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29	= IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__GPIO_2_13		= IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13	= IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__RAWNAND_D14		= IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__USDHC4_DAT6		= IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__UART2_CTS		= IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__UART2_RTS		= IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0),
+	MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30	= IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30	= IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__GPIO_2_14		= IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14	= IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__RAWNAND_D15		= IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__USDHC4_DAT7		= IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__UART2_TXD		= IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__UART2_RXD		= IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0),
+	MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31	= IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31	= IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__GPIO_2_15		= IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15	= IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h
index 8bba3b0..d72f5e5 100644
--- a/arch/arm/include/asm/arch-omap3/gpio.h
+++ b/arch/arm/include/asm/arch-omap3/gpio.h
@@ -40,6 +40,8 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO			192
+
 #define OMAP34XX_GPIO1_BASE		0x48310000
 #define OMAP34XX_GPIO2_BASE		0x49050000
 #define OMAP34XX_GPIO3_BASE		0x49052000
diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h
index 26f19d1..fdf65ed 100644
--- a/arch/arm/include/asm/arch-omap4/gpio.h
+++ b/arch/arm/include/asm/arch-omap4/gpio.h
@@ -40,6 +40,8 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO			192
+
 #define OMAP44XX_GPIO1_BASE		0x4A310000
 #define OMAP44XX_GPIO2_BASE		0x48055000
 #define OMAP44XX_GPIO3_BASE		0x48057000
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
index c14dff0..7c82f90 100644
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -40,11 +40,15 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO			256
+
 #define OMAP54XX_GPIO1_BASE		0x4Ae10000
 #define OMAP54XX_GPIO2_BASE		0x48055000
 #define OMAP54XX_GPIO3_BASE		0x48057000
 #define OMAP54XX_GPIO4_BASE		0x48059000
 #define OMAP54XX_GPIO5_BASE		0x4805B000
 #define OMAP54XX_GPIO6_BASE		0x4805D000
+#define OMAP54XX_GPIO7_BASE		0x48051000
+#define OMAP54XX_GPIO8_BASE		0x48053000
 
 #endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index c754ec7..9b8de9c 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -225,6 +225,16 @@ enum {
 	IN_408_OUT_9_6_DIVISOR = 83,
 };
 
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define PLLU_POWERDOWN		(1 << 16)
+#define PLL_ENABLE_POWERDOWN	(1 << 14)
+#define PLL_ACTIVE_POWERDOWN	(1 << 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN		(1 << 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
+
 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
 #define OSC_XOBP_SHIFT		1
 #define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index ef6c089..cefe0d2 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -22,120 +23,6 @@
 #ifndef _TEGRA_USB_H_
 #define _TEGRA_USB_H_
 
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
-	/* 0x000 */
-	uint id;
-	uint reserved0;
-	uint host;
-	uint device;
-
-	/* 0x010 */
-	uint txbuf;
-	uint rxbuf;
-	uint reserved1[2];
-
-	/* 0x020 */
-	uint reserved2[56];
-
-	/* 0x100 */
-	u16 cap_length;
-	u16 hci_version;
-	uint hcs_params;
-	uint hcc_params;
-	uint reserved3[5];
-
-	/* 0x120 */
-	uint dci_version;
-	uint dcc_params;
-	uint reserved4[6];
-
-	/* 0x140 */
-	uint usb_cmd;
-	uint usb_sts;
-	uint usb_intr;
-	uint frindex;
-
-	/* 0x150 */
-	uint reserved5;
-	uint periodic_list_base;
-	uint async_list_addr;
-	uint async_tt_sts;
-
-	/* 0x160 */
-	uint burst_size;
-	uint tx_fill_tuning;
-	uint reserved6;   /* is this port_sc1 on some controllers? */
-	uint icusb_ctrl;
-
-	/* 0x170 */
-	uint ulpi_viewport;
-	uint reserved7;
-	uint endpt_nak;
-	uint endpt_nak_enable;
-
-	/* 0x180 */
-	uint reserved;
-	uint port_sc1;
-	uint reserved8[6];
-
-	/* 0x1a0 */
-	uint reserved9;
-	uint otgsc;
-	uint usb_mode;
-	uint endpt_setup_stat;
-
-	/* 0x1b0 */
-	uint reserved10[20];
-
-	/* 0x200 */
-	uint reserved11[0x80];
-
-	/* 0x400 */
-	uint susp_ctrl;
-	uint phy_vbus_sensors;
-	uint phy_vbus_wakeup_id;
-	uint phy_alt_vbus_sys;
-
-	/* 0x410 */
-	uint usb1_legacy_ctrl;
-	uint reserved12[4];
-
-	/* 0x424 */
-	uint ulpi_timing_ctrl_0;
-	uint ulpi_timing_ctrl_1;
-	uint reserved13[53];
-
-	/* 0x500 */
-	uint reserved14[64 * 3];
-
-	/* 0x800 */
-	uint utmip_pll_cfg0;
-	uint utmip_pll_cfg1;
-	uint utmip_xcvr_cfg0;
-	uint utmip_bias_cfg0;
-
-	/* 0x810 */
-	uint utmip_hsrx_cfg0;
-	uint utmip_hsrx_cfg1;
-	uint utmip_fslsrx_cfg0;
-	uint utmip_fslsrx_cfg1;
-
-	/* 0x820 */
-	uint utmip_tx_cfg0;
-	uint utmip_misc_cfg0;
-	uint utmip_misc_cfg1;
-	uint utmip_debounce_cfg0;
-
-	/* 0x830 */
-	uint utmip_bat_chrg_cfg0;
-	uint utmip_spare_cfg0;
-	uint utmip_xcvr_cfg1;
-	uint utmip_bias_cfg1;
-};
-
-
 /* USB1_LEGACY_CTRL */
 #define USB1_NO_LEGACY_MODE		1
 
@@ -146,25 +33,18 @@ struct usb_ctlr {
 #define VBUS_SENSE_CTL_AB_SESS_VLD		2
 #define VBUS_SENSE_CTL_A_SESS_VLD		3
 
-/* USB2_IF_ULPI_TIMING_CTRL_0 */
-#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
-
-/* USB2_IF_ULPI_TIMING_CTRL_1 */
-#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
-
 /* USBx_IF_USB_SUSP_CTRL_0 */
-#define ULPI_PHY_ENB				(1 << 13)
 #define UTMIP_PHY_ENB			        (1 << 12)
 #define UTMIP_RESET			        (1 << 11)
 #define USB_PHY_CLK_VALID			(1 << 7)
 #define USB_SUSP_CLR				(1 << 5)
 
+/* USB2_IF_USB_SUSP_CTRL_0 */
+#define ULPI_PHY_ENB				(1 << 13)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
+
 /* USBx_UTMIP_MISC_CFG1 */
 #define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
 #define UTMIP_PLLU_STABLE_COUNT_MASK		\
@@ -177,15 +57,28 @@ struct usb_ctlr {
 /* USBx_UTMIP_PLL_CFG1_0 */
 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
-				(0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
 #define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
 #define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
 
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
+#define UTMIP_OTGPD				(1 << 11)
+#define UTMIP_BIASPD				(1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT		2
+#define UTMIP_HSDISCON_LEVEL_MASK		\
+				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
+#define UTMIP_HSSQUELCH_LEVEL_MASK		\
+				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
 /* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN		1
 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
 #define UTMIP_BIAS_PDTRK_COUNT_MASK		\
 				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
 
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
 #define UTMIP_DEBOUNCE_CFG0_SHIFT		0
 #define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
 
@@ -195,9 +88,6 @@ struct usb_ctlr {
 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
 #define UTMIP_PD_CHRG				1
 
-/* USBx_UTMIP_XCVR_CFG0_0 */
-#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
-
 /* USBx_UTMIP_SPARE_CFG0_0 */
 #define FUSE_SETUP_SEL				(1 << 3)
 
@@ -208,23 +98,26 @@ struct usb_ctlr {
 #define UTMIP_ELASTIC_LIMIT_MASK		\
 				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
 
-/* USBx_UTMIP_HSRX_CFG0_1 */
+/* USBx_UTMIP_HSRX_CFG1_0 */
 #define UTMIP_HS_SYNC_START_DLY_SHIFT		1
 #define UTMIP_HS_SYNC_START_DLY_MASK		\
-				(0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
+				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
 
 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 #define IC_ENB1					(1 << 3)
 
-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
-#define PTS_SHIFT				30
-#define PTS_MASK				(3U << PTS_SHIFT)
-#define PTS_UTMI		0
+/* PORTSC1, USB1, defined for Tegra20 */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+#define PTS_UTMI	0
 #define PTS_RESERVED	1
-#define PTS_ULPI		2
+#define PTS_ULPI	2
 #define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
 
-#define STS					(1 << 29)
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
 #define WKOC				(1 << 22)
 #define WKDS				(1 << 21)
 #define WKCN				(1 << 20)
@@ -233,8 +126,19 @@ struct usb_ctlr {
 #define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
 #define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
 #define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
+			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
+#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT		0
+#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)
 
 /* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
+			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
 #define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
 #define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
 #define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h
new file mode 100644
index 0000000..d46048c
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/usb.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA114_USB_H_
+#define _TEGRA114_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+
+#define STS					(1 << 28)
+#endif /* _TEGRA114_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h
new file mode 100644
index 0000000..3d94cc7
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/usb.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA20_USB_H_
+#define _TEGRA20_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[6];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[4];
+
+	/* 0x424 */
+	uint ulpi_timing_ctrl_0;
+	uint ulpi_timing_ctrl_1;
+	uint reserved13[53];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT		30
+#define PTS_MASK		(3U << PTS_SHIFT)
+
+#define STS			(1 << 29)
+#endif /* _TEGRA20_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/usb.h b/arch/arm/include/asm/arch-tegra30/usb.h
new file mode 100644
index 0000000..ab9b760
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/usb.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_USB_H_
+#define _TEGRA30_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+
+#define STS					(1 << 28)
+#endif /* _TEGRA30_USB_H_ */
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 949b9e8..cd2bab6 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -70,6 +70,15 @@ fixnext:
 
 relocate_done:
 
+#ifdef __XSCALE__
+	/*
+	 * On xscale, icache must be invalidated and write buffers drained,
+	 * even with cache disabled - 4.2.7 of xscale core developer's manual
+	 */
+	mcr	p15, 0, r0, c7, c7, 0	/* invalidate icache */
+	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
+#endif
+
 	/* ARMv4- don't know bx lr but the assembler fails to see that */
 
 #ifdef __ARM_ARCH_4__
diff --git a/doc/README.m28 b/board/denx/m28evk/README
index 2a92226..cb3ae20 100644
--- a/doc/README.m28
+++ b/board/denx/m28evk/README
@@ -9,5 +9,5 @@ arch/arm/include/asm/arch-mxs/	- Header files for the Freescale i.MX28
 board/denx/m28evk/		- M28EVK board specific files
 include/configs/m28evk.h	- M28EVK configuration file
 
-Follow the instructions from doc/README.mx28_common to generate a bootable SD
-card or to boot from NAND flash.
+Follow the instructions from doc/README.mxs to generate a bootable SD card or to
+boot from NAND flash.
diff --git a/doc/README.mx28evk b/board/freescale/mx28evk/README
index 76db474..524f3fc 100644
--- a/doc/README.mx28evk
+++ b/board/freescale/mx28evk/README
@@ -41,7 +41,6 @@ Note: The mx28evk board does not come with a NAND flash populated from the
 factory. It comes with an empty slot (U23), which allows the insertion of a
 48-pin TSOP flash device.
 
-Follow the instructions from doc/README.mx28_common to generate a bootable SD
-card.
+Follow the instructions from doc/README.mxs to generate a bootable SD card.
 
 Insert the SD card in slot 0, power up the board and U-boot will boot.
diff --git a/board/freescale/mx6qsabresd/Makefile b/board/freescale/mx6sabresd/Makefile
index 5693772..ff3c94b 100644
--- a/board/freescale/mx6qsabresd/Makefile
+++ b/board/freescale/mx6sabresd/Makefile
@@ -23,7 +23,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-COBJS  := mx6qsabresd.o
+COBJS  := mx6sabresd.o
 
 SRCS   := $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2529826..222ee98 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -17,12 +17,10 @@
  * GNU General Public License for more details.
  */
 
-#include <common.h>
-#include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -291,7 +289,6 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX6Q-SabreSD\n");
-
+	puts("Board: MX6-SabreSD\n");
 	return 0;
 }
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 8d7a227..f60f21f 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -47,6 +47,7 @@
 #endif
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include <asm/arch-tegra/usb.h>
+#include <asm/arch/usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
 #include <asm/arch-tegra/tegra_mmc.h>
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
index 86e9459..435c01e 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -14,6 +14,7 @@
 		i2c4 = "/i2c@7000c700";
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000400";
+		usb0 = "/usb@7d008000";
 	};
 
 	memory {
@@ -61,4 +62,10 @@
 		bus-width = <8>;
 		status = "okay";
 	};
+
+	usb@7d008000 {
+		/* SPDIF_IN: USB_VBUS_EN1 */
+		nvidia,vbus-gpio = <&gpio 86 0>;
+		status = "okay";
+	};
 };
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index 7934e4a..b115f87 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -17,6 +17,17 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
@@ -70,4 +81,25 @@
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
 		bus-width = <8>;
 	};
+
+	lcd_panel: panel {
+		clock = <42430000>;
+		xres = <1024>;
+		yres = <600>;
+		left-margin = <138>;
+		right-margin = <34>;
+		hsync-len = <136>;
+		lower-margin = <4>;
+		upper-margin = <21>;
+		vsync-len = <4>;
+		hsync-active-high;
+		vsyncx-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 0>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>;	/* PB5 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
+		nvidia,panel-timings = <0 0 200 0 0>;
+	};
 };
diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts
index e1a3d1e..1a526ba 100644
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ b/board/nvidia/dts/tegra20-ventana.dts
@@ -16,6 +16,17 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
@@ -56,4 +67,25 @@
 		status = "okay";
 		bus-width = <8>;
 	};
+
+	lcd_panel: panel {
+		clock = <72072000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <58>;
+		right-margin = <58>;
+		hsync-len = <58>;
+		lower-margin = <4>;
+		upper-margin = <4>;
+		vsync-len = <4>;
+		hsync-active-high;
+		vsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 2 0>;
+		nvidia,backlight-enable-gpios = <&gpio 28 0>;	/* PD4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
+		nvidia,panel-timings = <0 0 200 0 0>;
+	};
 };
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
index 836169f..a7cc93e 100644
--- a/board/nvidia/dts/tegra30-beaver.dts
+++ b/board/nvidia/dts/tegra30-beaver.dts
@@ -14,6 +14,7 @@
 		i2c4 = "/i2c@7000c700";
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000000";
+		usb0 = "/usb@7d008000";
 	};
 
 	memory {
@@ -68,4 +69,9 @@
 		status = "okay";
 		bus-width = <8>;
 	};
+
+	usb@7d008000 {
+		nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
+		status = "okay";
+	};
 };
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
index 4d22b48..ea2cf76 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -14,6 +14,7 @@
 		i2c4 = "/i2c@7000c700";
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000000";
+		usb0 = "/usb@7d008000";
 	};
 
 	memory {
@@ -63,4 +64,9 @@
 		status = "okay";
 		bus-width = <8>;
 	};
+
+	usb@7d008000 {
+		nvidia,vbus-gpio = <&gpio 236 0>;	/* PDD4 */
+		status = "okay";
+	};
 };
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 3122441..dd8f99a 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <lcd.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
@@ -59,3 +60,9 @@ void pin_mux_usb(void)
 	/* USB2 PHY reset GPIO */
 	pinmux_tristate_disable(PINGRP_UAC);
 }
+
+void pin_mux_display(void)
+{
+	pinmux_set_func(PINGRP_SDC, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PINGRP_SDC);
+}
diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile
new file mode 100644
index 0000000..34ffb99
--- /dev/null
+++ b/board/palmtreo680/Makefile
@@ -0,0 +1,34 @@
+#
+# Palm Treo680 Support
+#
+# Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= palmtreo680.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/palmtreo680/README b/board/palmtreo680/README
new file mode 100644
index 0000000..159f1f6
--- /dev/null
+++ b/board/palmtreo680/README
@@ -0,0 +1,581 @@
+
+README for the Palm Treo 680.
+
+Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+
+You may reproduce the contents of this file entirely or in part, but please
+credit me by name if you do.  Thanks.
+
+
+Intro
+=====
+
+Yes, you can program u-boot onto the flash of your Palm Treo 680 so that u-boot
+(then Linux, Android, ...) runs at power-up.  This document describes how, and
+gives some implementation details on this port of u-boot and describes how the
+Treo 680 boots from reset.
+
+But first, I probably don't need to tell you that after doing this, your phone
+will no longer run PalmOS.  You *may* be able to later restore your phone to its
+original state by creating a backup image of the flash before writing u-boot
+(details below), but this is not heavily tested and should not be relied upon.
+There is also the possibility that something may go wrong during the process of
+programming u-boot, leaving you with a bricked phone.  If you follow these
+instructions carefully this chance will be minimized, but I do not recommend
+that you program u-boot onto a phone that you can not afford to lose, and
+certainly not one that contains important data that is not backed up elsewhere.
+I AM NOT RESPONSIBLE FOR THE LOSS OF YOUR PHONE.  DO THIS AT YOUR OWN RISK.
+Having said that, feel free to send me a note cursing me out if something does
+go wrong, but please tell me what happened exactly.  For that matter, I'd love
+to hear from you if you succeed.
+
+
+
+Details on the SPL
+==================
+
+The docg4 features a 2k region at the start of its address space that interfaces
+to the system bus like a NOR flash.  This allows the docg4 to function as a boot
+ROM.  The Treo 680 uses this feature.  The contents of this 2k region are
+write-protected and can not be reprogrammed.  Fortunately, the code it contains
+does what we need to do, at least partially.  After some essential hardware
+initialization (like the SDRAM controller), it runs an IPL (initial program
+loader) that copies 128K (no more, no less) from flash to a fixed address in
+SDRAM (0xa1700000) and jumps to it.  128K is too small for u-boot, so we use it
+to load a u-boot secondary program loader (SPL).  But since our SPL only
+occupies a little over 1k, we can economize on flash usage by having the IPL
+load a portion of u-boot proper as well.  We let the IPL load the first 128k of
+a concatenated spl + u-boot image, and because the SPL is placed before u-boot
+proper, the IPL jumps to the SPL, which copies the portion of u-boot that the
+IPL has already loaded to its correct SDRAM address, and then loads the
+remainder of u-boot and jumps to it.
+
+
+
+The docg4's "reliable mode"
+===========================
+
+This is a special mode of operation of the docg4's integrated controller whereby
+consecutive pairs of 2k regions are used in parallel (in some fashion) to store
+2k of data.  In other words, the normal capacity is halved, but the data
+integrity is improved.  In this mode, the data is read or written from pages in
+even-numbered 2k regions (regions starting at 0x000, 0x1000, 0x2000, ...).  The
+odd-numbered 2k regions (regions starting at 0x800, 0x1800, 0x2800, ...) are
+transparently used in parallel.  In reliable mode, the odd-numbered 2k regions
+are not meant to be read or written directly.
+
+Reliable mode is used by the IPL because there is not enough space in its 2k
+footprint to implement the BCH ecc algorithm.  Data that is read while reliable
+mode is enabled must have been written in reliable mode, or the read fails.
+However, data written in reliable mode can also be read in normal mode (just not
+as reliably), but only from the even-numbered 2k regions; the odd-numbered 2k
+regions appear to contain junk, and will generate ecc errors.  When the IPL and
+SPL read from flash, the odd-numbered 2k regions are explicitly skipped.  The
+same is true for the flash_u-boot utility when it writes the u-boot image in
+reliable mode.
+
+The docg4 Linux driver supports writing in reliable mode (it is enabled by the
+module parameter), but not reading.  However, the u-boot docg4_spl driver does
+read in reliable mode, in the same fashion as the IPL.
+
+
+
+Details on the IPL and its data format
+======================================
+
+Starting from block 5 and counting upward, the IPL will search for and load the
+first two blocks it finds that contain a magic number in the oob of the first
+page of the block.  The contents are loaded to SDRAM starting at address
+0xa1700000.  After two blocks have been loaded, it jumps to 0xa1700000.  The
+number of blocks loaded and the load address in SDRAM are hard-coded; only the
+flash offset of the blocks can vary at run-time (based on the presence of the
+magic number).
+
+In addition to using the docg4's reliable mode, the IPL expects each 512 byte
+page to be written redundantly in the subsequent page.  The hardware is capable
+of detecting bit errors (but not correcting them), and if a bit error is
+detected when a page is read, the page contents are discarded and the subsequent
+page is read.
+
+Reliable mode reduces the capacity of a block by half, and the redundant pages
+reduce it by half again.  As a result, the normal 256k capacity of a block is
+reduced to 64k for the purposes of the IPL/SPL.
+
+For the sake of simplicity and uniformity, the u-boot SPL mimics the operation
+of the IPL, and expects the image to be stored in the same format.
+
+
+
+Instructions on Programming u-boot to flash
+===========================================
+
+To program u-boot to your flash, you will need to boot the Linux kernel on your
+phone using a PalmOS bootloader such as cocoboot.  The details of building and
+running Linux on your Treo (cross-compiling, creating a root filesystem,
+configuring the kernel, etc) are beyond the scope of this document.  The
+remainder of this document describes in detail how to program u-boot to the
+flash using Linux running on the Treo.
+
+
+
+Hardware Prerequisites
+======================
+
+A Palm Treo 680:
+  (dugh)
+
+A Palm usb cable:
+  You'll need this to establish a usbtty console connection to u-boot from a
+  desktop PC.  Currently there is no support in u-boot for the pxa27x keypad
+  (coming soon), so a serial link must be used for the console.
+  These cables are still widely available if you don't already have one.
+
+A Linux desktop PC.
+  You may be able to use Windows for the u-boot console if you have a usb driver
+  that is compatible with the Linux usbserial driver, but for programming u-boot
+  to flash, you'll really want to use a Linux PC.
+
+
+
+Treo-side Software Prerequisites
+================================
+
+Linux bootloader for PalmOS:
+
+  Cocoboot is the only one I'm aware of.  If you don't already have this, you
+  can download it from
+  https://download.enlightenment.org/misc/Illume/Treo-650/2008-11-13/sdcard-base.tar.gz
+  which is a compressed tar archive of the contents of an sd card containing
+  cocoboot.  Use mkdosfs to create a fat16 filesystem on the first primary
+  partition of the card, mount the partition, and extract the tar file to it.
+  You will probably need to edit the cocoboot.conf file to customize the
+  parameters passed to the kernel.
+
+
+
+Linux kernel:
+
+  The kernel on the Treo 680 is still a little rough around the edges, and the
+  official kernel frequently breaks on the Treo :(  A development kernel
+  specifically for the Treo 680 can be found on github:
+    http://github.com/mike-dunn/linux-treo680
+  The master branch of this tree has been tested on the Treo, and I recommend
+  using this kernel for programming u-boot.  As of this writing, there may be a
+  bug in the docg4 nand flash driver that sometimes causes block erasures to
+  fail.  This has been fixed in the above tree.
+
+  If you choose to use the official kernel, it must contain the docg4 driver that
+  includes the reliable_mode module parameter.  This was a later enhancement to
+  the driver, and was merged to the kernel as of v3.8.  Do not try to use an
+  earlier kernel that contains the docg4 driver without support for writing in
+  reliable mode.  If you try to program u-boot to flash with the docg4 driver
+  loaded without the reliable_mode parameter enabled, you *will* brick your
+  phone!
+
+  For the purpose of programming u-boot to flash, the following options must be
+  enabled in the Treo kernel's .config:
+
+     CONFIG_MTD=y
+     CONFIG_MTD_CMDLINE_PARTS=y
+     CONFIG_MTD_CHAR=y
+     CONFIG_MTD_NAND_DOCG4=m
+
+  Note that the docg4 nand driver is configured as a module, because we will
+  want to load and unload it with reliable_mode enabled or disabled as needed.
+
+  You will also need to specify mtd partitions on the kernel command line.  In
+  the instructions that follow, we will assume that the flash blocks to which
+  u-boot will be programmed are defined by the second partition on the device.
+  The u-boot config file (include/configs/palmtreo680.h) places the u-boot image
+  at the start of block 6 (offset 0x180000), which is the first writable
+  (non-protected) block on the flash (this is also where the PalmOS SPL starts).
+  The u-boot image occupies four blocks, so to create the u-boot partition, pass
+  this command line to the kernel:
+    mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part)
+  This will create three partitions:
+    protected_part: the first six blocks, which are read-only
+    bootloader_part: the next four blocks, for the u-boot image
+    filesys_part: the remainder of the device
+  The mtdchar kernel device driver will use device nodes /dev/mtd0, /dev/mtd1,
+  and /dev/mtd2 for these partitions, respectively.  Ensure that your root file
+  system at least has /dev/mtd1 if you are not running udev or mdev.
+
+
+Userspace Utilities:
+
+  In addition to everything necessary to provide a useful userspace environment
+  (busybox is indispensable, of course), you will need the mtd-utils package on
+  your root filesystem.  I use version 1.5.0 of mtd-utils, and I suggest you use
+  this version as well, or at leat a version very close to this one, as
+  mtd-utils has tended to be fluid.
+
+  Note that busybox includes a version of mtd-utils.  These are deficient and
+  should not be used.  When you run one of these utilities (nanddump, etc),
+  ensure you are invoking the separate executable from mtd-utils, and not the
+  one built into busybox.  I recommend that you configure busybox with its
+  mtd-utils disabled to avoid any possibility of confusion.
+
+  You will also need to cross-compile the userspace Linux utility in
+  tools/palmtreo680/flash_u-boot.c, which we will run on the Treo to perform the
+  actual write of the u-boot image to flash.  This utility links against libmtd
+  from the mtd-utils package.
+
+
+
+Desktop PC-side Software Prerequisites
+======================================
+
+Terminal emulator application:
+  minicom, kermit, etc.
+
+
+Linux kernel:
+  Compiled with CONFIG_USB_SERIAL enabled.  Build this as a module.
+
+
+
+Recommended (Not directly related to u-boot)
+============================================
+
+Working directly on the Treo's tiny screen and keypad is difficult and
+error-prone.  I recommend that you log into the Linux kernel running on your
+Treo from your desktop PC using ethernet over usb.  The desktop's kernel must be
+configured with CONFIG_USB_USBNET, CONFIG_USB_NET_CDCETHER, and
+CONFIG_USB_NET_CDC_SUBSET.  The Treo's kernel will need CONFIG_USB_ETH, and its
+init script will need to start an ssh daemon like dropbear.  Note that the usb0
+network interface will not appear on the desktop PC until the Treo kernel's usb
+ethernet gadget driver has initialized.  You must wait for this to occur (watch
+the PC's kernel log) before you can assign usb0 an ip address and log in to the
+Treo.  If you also build the Treo's kernel with CONFIG_IP_PNP enabled, you can
+pass its ip address on the kernel command line, and obviate the need to
+initialize the network interface in your init script.
+
+Having the Palm usb cable connected to the host has the added benefit of keeping
+power supplied to your Treo, reducing the drain on the battery.  If something
+goes wrong while you're programming u-boot to the flash, you will have lots of
+time to correct it before the battery dies.
+
+I have encountered a situation where the kernel is sometimes unable to mount a
+root filesystem on the mmc card due to the mmc controller not initializing in
+time, (and CONFIG_MMC_UNSAFE_RESUME doesn't seem to help) so I recommend that
+you build a minimal root filesystem into the kernel using the kernel's initramfs
+feature (CONFIG_BLK_DEV_INITRD).  If you want your root filesystem on the mmc
+card, your init script can mount and switch_root to the mmc card after a short
+sleep.  But keep in mind that in this case you won't be able to use an mmc card
+to transfer files between your desktop and the Treo once Linux is running.
+Another option for transfering files is to mount an nfs filesystem exported by
+the desktop PC.  For greatest convenience, you can export the root filesystem
+itself from your desktop PC and switch_root to it in your init script.  This
+will work if your initramfs init script contains a loop that waits for you to
+initialize the usb0 network interface on the desktop PC; e.g., loop while a ping
+to the desktop PC returns an error.  After the loop exits, do the nfs mount and
+call switch_root.  (You can not use the kernel nfsroot feature because the
+network will not be up when the kernel expects it to be; i.e., not until you
+configure the usb0 interface on the desktop.)  Use the nfs 'nolock' option when
+mounting to avoid the need to run a portmapper like rpcbind.
+
+
+
+Preliminaries
+=============
+
+Once Linux is running on your Treo, you may want to perform a few sanity checks
+before programming u-boot.  These checks will verify my assumptions regarding
+all the Treo 680s out there, and also ensure that the flash and mtd-utils are
+working correctly.  If you are impatient and reckless, you may skip this
+section, but see disclaimer at the top of this file!
+
+Load the docg4 driver:
+
+  $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
+
+We tell the driver to use the docg4's "reliable mode" when writing because this
+is the format required by the IPL, which runs from power-up and loads the first
+portion of u-boot.  We must ignore bad blocks because linux mtd uses out-of-band
+(oob) bytes to mark bad blocks, which will cause the blocks written by PalmOS to
+be misidentified as "bad" by libmtd.
+
+Check the kernel log to ensure that all's well:
+
+  $ dmesg | tail
+   	      <... snip ...>
+  docg4 docg4: NAND device: 128MiB Diskonchip G4 detected
+  3 cmdlinepart partitions found on MTD device Msys_Diskonchip_G4
+  Creating 3 MTD partitions on "Msys_Diskonchip_G4":
+  0x000000000000-0x000000180000 : "protected_part"
+  0x000000180000-0x000000280000 : "bootloader_part"
+  0x000000280000-0x000008000000 : "filesys_part"
+
+Ensure that the partition boundaries are as shown.  (If no partitions are shown,
+did you remember to pass them to the kernel on the command line?)  We will write
+u-boot to bootloader_part, which starts at offset 0x180000 (block 6) and spans 4
+256k blocks.  This partition is accessed through the device node /dev/mtd1.
+
+The docg4 contains a read-only table that identifies blocks that were marked as
+bad at the factory.  This table is in the page at offset 0x2000, which is within
+the partition protected_part (/dev/mtd0).  There is a slight chance that one or
+more of the four blocks that we will use for u-boot is listed in the table, so
+use nanddump to inspect the table to see if this is the case:
+
+  $ nanddump -p -l 512 -s 0x2000 -o /dev/mtd0
+  ECC failed: 0
+  ECC corrected: 0
+  Number of bad blocks: 0
+  Number of bbt blocks: 0
+  Block size 262144, page size 512, OOB size 16
+  Dumping data starting at 0x00002000 and ending at 0x00002200...
+  0x00002000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+   	      <... snip ...>
+
+The format of the table is simple: one bit per block, with block numbers
+increasing from left to right, starting with block 0 as the most significant bit
+of the first byte.  A bit will be clear if the corresponding block is bad.  We
+want to use blocks 6 throgh 9, so both of the two least significant bits of the
+first byte must be set, as must the two most significant bits of the second
+byte.  If this is not true in your case (you are very unlucky), you should use
+the first contiguous set of four good blocks after block 6, and adjust the
+partition boundaries accordingly.  You will also have to change the value of
+CONFIG_SYS_NAND_U_BOOT_OFFS in include/configs/palmtreo680.h and recompile
+u-boot.  Because the two blocks loaded by the IPL do not have to be contiguous,
+but our SPL expects them to be, you will need to erase any good blocks that are
+at an offset prior to CONFIG_SYS_NAND_U_BOOT_OFFS, so that the IPL does not find
+the magic number in oob and load it.  Once you have done all this, the
+instructions in this file still apply, except that the instructions below for
+restoring the original PalmOS block contents may need to be modified.
+
+Next, use nanddump to verify that the PalmOS SPL is where we expect it to be.
+The SPL can be identified by a magic number in the oob bytes of the first page
+of each of the two blocks containing the SPL image.  Pages are 512 bytes in
+size, so to dump the first page, plus the oob:
+
+  $ nanddump -p -l 512 -s 0 -o /dev/mtd1
+  ECC failed: 0
+  ECC corrected: 0
+  Number of bad blocks: 0
+  Number of bbt blocks: 0
+  Block size 262144, page size 512, OOB size 16
+  Dumping data starting at 0x00000000 and ending at 0x00000200...
+  0x00000000: 0a 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
+   	      <... snip ...>
+  0x000001f0: 13 4c 21 60 13 4d 2a 69 13 4b 29 69 89 1a 99 42
+    OOB Data: 42 49 50 4f 30 30 30 10 3a e2 00 92 be a0 11 ff
+
+Verify that the first seven bytes of oob data match those in the above line.
+(This is ASCII "BIPO000".)
+
+Do the same for the next block:
+  $ nanddump -p -l 512 -s 0x40000 -o /dev/mtd1
+
+The first seven oob bytes in last line should read:
+
+    OOB Data: 42 49 50 4f 30 30 31 81 db 8e 8f 46 07 9b 59 ff
+
+(This is ASCII "BIPO001".)
+
+For additional assurance, verify that the next block does *not* contain SPL
+data.
+
+  $ nanddump -p -l 512 -s 0x80000 -o /dev/mtd1
+
+It doesn't matter what the oob contains, as long as the first four bytes are
+*not* ASCII "BIPO".  PalmOS should only be using two blocks for the SPL
+(although we will need four for u-boot).
+
+If you want, you can back up the contents of bootloader_part to a file.  You may
+be able to restore it later, if desired (see "Restoring PalmOS" below).
+
+  $ nanddump -l 0x100000 -s 0 -o -f bootloader_part.orig /dev/mtd1
+
+nanddump will spew voluminous warnings about uncorrectable ecc errors.  This is
+a consequence of reading pages that were written in reliable mode, and is
+expected (these should all occur on pages in odd-numbered 2k regions; i.e.,
+0x800, 0xa00, 0xc00, 0xe00, 0x1800, 0x1a00, ...).  The size of the file
+bootloader_part.orig should be 1081344, which is 2048 pages, each of size 512
+plus 16 oob bytes.  If you are using initramfs for the root filesystem, don't
+forget to copy the file to permanent storage, such as an mmc card.
+
+If all of the above went well, you can now program u-boot.
+
+
+
+Programming u-boot
+==================
+
+Our u-boot includes a small SPL that must be prepended to u-boot proper.  From
+the base u-boot source directory on your desktop PC:
+
+  $ cat spl/u-boot-spl.bin u-boot.bin > u-boot-concat.bin
+
+cd to the tools/palmtreo680/ directory, and cross-compile flash_u-boot.c for the
+Treo:
+
+  $(CC) -o flash_u-boot $(CFLAGS) $(INCLUDEPATH) $(LIBPATH) flash_u-boot.c -lmtd
+
+Substitute variable values from your cross-compilation environment as
+appropriate.  Note that it links to libmtd from mtd-utils, and this must be
+included in $(LIBPATH) and $(INCLUDEPATH).
+
+Transfer u-boot-concat.bin and the compiled flash_u-boot utility to the Treo's
+root filesystem.  On the Treo, cd to the directory where these files were
+placed.
+
+Load the docg4 driver if you have not already done so.
+
+  $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
+
+Erase the blocks to which we will write u-boot:
+
+  $ flash_erase /dev/mtd1 0x00 4
+
+If no errors are reported, write u-boot to the flash:
+
+  $ ./flash_u-boot u-boot-concat.bin /dev/mtd1
+
+You can use nanddump (see above) to verify that the data was written.  This
+time, "BIPO" should be seen in the first four oob bytes of the first page of all
+four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000.
+
+Shutdown linux, remove and re-insert the battery, hold your breath...
+
+
+
+Enjoying u-boot
+===============
+
+After you insert the battery, the u-boot splash screen should appear on the lcd
+after a few seconds.  With the usb cable connecting the Treo to your PC, in the
+kernel log of your PC you should see
+
+  <6>usb 3-1: New USB device found, idVendor=0525, idProduct=a4a6
+  <6>usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+  <6>usb 3-1: Product: U-Boot 2013.01-00167-gd62ef56-dirty
+  <6>usb 3-1: Manufacturer: Das U-Boot
+
+Load the usbserial module on your desktop PC:
+
+  $ modprobe usbserial vendor=0x0525 product=0xa4a6
+
+and run your favorite terminal emulation utility (minicom, kermit, etc) with the
+serial device set to /dev/ttyUSB0 (assuming this is your only usb serial
+device).  You should be at the u-boot console (type 'help').
+
+There is not much that is unique about using u-boot on the palm treo 680.
+Kernels can be loaded from mmc, flash, and from the desktop PC via kermit.  You
+can expand the size of the second partition on the flash to contain a kernel, or
+else put the kernel(s) in their own partition.
+
+Nand commands work as expected, with the excepton that blocks not written by the
+linux mtd subsystem may be misidentified by the u-boot docg4 driver as "bad" if
+they contain data in the oob bytes.  This will be the case for the blocks
+containing the u-boot image, for example.  To work around this, use 'nand scrub'
+instead of 'nand erase' to erase these blocks, and 'nand read.raw' to read them
+to memory.  (It would be useful if u-boot's nand commands provided a way to
+explicitly ignore "bad" blocks, because read.raw does not perform ecc.)  The
+'nand dump' command will read these "bad" blocks, however.
+
+Currently u-boot itself can only be programmed to flash from Linux; there is no
+support for reliable mode in u-boot's docg4 flash driver.  This should be
+corrected soon.
+
+
+
+Customizing
+===========
+
+If you change u-boot's configuration significantly (adding or removing
+features), you may have to adjust the value of CONFIG_SYS_NAND_U_BOOT_SIZE.
+This is the size of the concatenated spl + u-boot image, and tells the SPL how
+many flash blocks it needs to load.  It will be rounded up to the next 64k
+boundary (the spl flash block capacity), so it does not have to be exact, but
+you must ensure that it is not less than the actual image size.  If it is larger
+than the image, blocks may be needlessly loaded, but if too small, u-boot may
+only be partially loaded, resulting in a boot failure (bricked phone), so better
+to be too large.  The flash_u-boot utility will work with any size image and
+write the required number of blocks, provided that the partition is large
+enough.
+
+As the first writable block on the device, block 6 seems to make the most sense
+as the flash offset for writing u-boot (and this is where PalmOS places its
+SPL).  But you can place it elsewhere if you like.  If you do, you need to
+adjust CONFIG_SYS_NAND_U_BOOT_OFFS accordingly, and you must ensure that blocks
+preceeding the ones containing u-boot do *not* have the magic number in oob (the
+IPL looks for this).  In other words, make sure that any blocks that previously
+contained the u-boot image or PalmOS SPL are erased (and optionally written with
+something else) so that the IPL does not load it.  Also make sure that the new
+u-boot starting offset is at the start of a flash partition (check the kernel
+log after loading the docg4 driver), and pass the corresponding mtd device file
+to the flash_u-boot utility.
+
+The u-boot built-in default environment is used because a writable environment
+in flash did not seem worth the cost of a 256k flash block.  But adding this
+should be straightforward.
+
+
+
+Restoring PalmOS
+================
+
+If you backed up the contents of bootloader_part flash partition earlier, you
+should be able to restore it with the shell script shown below.  The first two
+blocks of data contain the PalmOS SPL and were written in reliable mode, whereas
+the next two blocks were written in normal mode, so the script has to load and
+unload the docg4 driver.  Make sure that the mtd-utils nandwrite and flash_erase
+are in your path (and are not those from busybox).  Also double-check that the
+backup image file bootloader_part.orig is exactly 1081344 bytes in length.  If
+not, it was not backed up correctly.  Run the script as:
+
+  ./restore_bootpart bootloader_part.orig /dev/mtd1
+
+The script will take a minute or so to run.  When it finishes, you may want to
+verify with nanddump that the data looks correct before you cycle power, because
+if the backup or restore failed, your phone will be bricked.  Note that as a
+consequence of reliable mode, the odd-numbered 2k regions in the first two
+blocks will not exactly match the contents of the backup file, (so unfortunately
+we can't simply dump the flash contents to a file and do a binary diff with the
+original back-up image to verify that it was restored correctly).  Also,
+nanddump will report uncorrectable ecc errors when it reads those regions.
+
+#!/bin/sh
+
+if [ $# -ne 2 ]; then
+    echo "usage: $0: <image file> <mtd device node>"
+    exit 1
+fi
+
+# reliable mode used for the first two blocks
+modprobe -r docg4
+modprobe docg4 ignore_badblocks=1 reliable_mode=1 || exit 1
+
+# erase all four blocks
+flash_erase $2 0 4
+
+# Program the first two blocks in reliable mode.
+# 2k (4 pages) is written at a time, skipping alternate 2k regions
+# Note that "2k" is 2112 bytes, including 64 oob bytes
+file_ofs=0
+flash_ofs=0
+page=0
+while [ $page -ne 1024 ]; do
+    dd if=$1 bs=2112 skip=$file_ofs count=1 | nandwrite -o -n -s $flash_ofs $2 - || exit 1
+    file_ofs=$((file_ofs+2))
+    flash_ofs=$((flash_ofs+0x1000))
+    page=$((page+8))
+done;
+
+# normal mode used for the next two blocks
+modprobe -r docg4
+modprobe docg4 ignore_badblocks=1 || exit 1
+dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1
+modprobe -r docg4
+
+
+TODO
+====
+
+  - Keypad support.
+  - Interactive boot menu using keypad and lcd.
+  - Add reliable mode support to the u-boot docg4 driver.
+  - U-boot command that will write a new image to the bootloader partition in
+    flash.
+  - Linux FTD support.
+
diff --git a/board/palmtreo680/palmtreo680.c b/board/palmtreo680/palmtreo680.c
new file mode 100644
index 0000000..f4f6e1f
--- /dev/null
+++ b/board/palmtreo680/palmtreo680.c
@@ -0,0 +1,148 @@
+/*
+ * Palm Treo 680 Support
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <nand.h>
+#include <malloc.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch-pxa/pxa.h>
+#include <asm/arch-pxa/regs-mmc.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <u-boot/crc.h>
+#include <linux/mtd/docg4.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct nand_chip docg4_nand_chip;
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+	gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* IPL initializes SDRAM (we're already running from it) */
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_LCD
+void lcd_enable(void)
+{
+	/*
+	 * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
+	 * driver code.  We need it as an output gpio.
+	 */
+	writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
+
+	/* power-up and enable the lcd */
+	writel(0x00400000, GPSR(86)); /* enable; drive high */
+	writel(0x00002000, GPSR(77)); /* power; drive high */
+	writel(0x02000000, GPCR(25)); /* enable_n; drive low */
+
+	/* turn on LCD backlight and configure PWM for reasonable brightness */
+	writel(0x00, PWM_CTRL0);
+	writel(0x1b1, PWM_PERVAL0);
+	writel(0xfd, PWM_PWDUTY0);
+	writel(0x00000040, GPSR(38)); /*  backlight power on */
+}
+#endif
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+	writel(1 << 10, GPSR(42)); /* power on */
+	return pxa_mmc_register(0);
+}
+#endif
+
+void board_nand_init(void)
+{
+	/* we have one 128M diskonchip G4  */
+
+	struct mtd_info *mtd = &nand_info[0];
+	struct nand_chip *nand = &docg4_nand_chip;
+	if (docg4_nand_init(mtd, nand, 0))
+		hang();
+}
+
+#ifdef CONFIG_SPL_BUILD
+void nand_boot(void)
+{
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	extern const void *_start, *_end;   /* boundaries of spl in memory */
+
+	/* size of spl; ipl loads this, and then a portion of u-boot */
+	const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
+
+	/* the flash offset of the blocks that are loaded by the spl */
+	const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
+		DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
+
+	/* total number of bytes loaded by IPL */
+	const size_t ipl_load_size =
+		DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
+
+	/* number of bytes of u-boot proper that was loaded by the IPL */
+	const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
+
+	/* number of remaining bytes of u-boot that the SPL must load */
+	const size_t spl_load_size =
+		CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
+
+	/* memory address where we resume loading u-boot */
+	void *const load_addr =
+		(void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
+
+	/*
+	 * Copy the portion of u-boot already read from flash by the IPL to its
+	 * correct load address.
+	 */
+	memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
+
+	/*
+	 * Resume loading u-boot where the IPL left off.
+	 */
+	nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
+
+#ifdef CONFIG_NAND_ENV_DST
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+			    (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	(*uboot)();
+}
+
+void board_init_f(ulong bootflag)
+{
+	nand_boot();
+}
+
+#endif  /* CONFIG_SPL_BUILD */
diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
index c0a7602..c0a7602 100644
--- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds
+++ b/board/samsung/common/exynos-uboot-spl.lds
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
index 93375a6..80ffe30 100644
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ b/board/samsung/dts/exynos5250-smdk5250.dts
@@ -34,6 +34,8 @@
 		mmc1 = "/mmc@12210000";
 		mmc2 = "/mmc@12220000";
 		mmc3 = "/mmc@12230000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
 	};
 
 	sromc@12250000 {
diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts
index d2ccc66..dca3386 100644
--- a/board/samsung/dts/exynos5250-snow.dts
+++ b/board/samsung/dts/exynos5250-snow.dts
@@ -30,6 +30,12 @@
 		spi2 = "/spi@12d40000";
 		spi3 = "/spi@131a0000";
 		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		mmc3 = "/mmc@12230000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
 	};
 
 	i2c4: i2c@12ca0000 {
@@ -83,6 +89,26 @@
 		};
 	};
 
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
 	tmu@10060000 {
 		samsung,min-temp	= <25>;
 		samsung,max-temp	= <125>;
diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
index 3a885a5..63c8b46 100644
--- a/board/samsung/origen/Makefile
+++ b/board/samsung/origen/Makefile
@@ -24,19 +24,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-SOBJS	:= mem_setup.o
-SOBJS	+= lowlevel_init.o
-
 ifndef CONFIG_SPL_BUILD
 COBJS	+= origen.o
 endif
 
-ifdef CONFIG_SPL_BUILD
-COBJS	+= mmc_boot.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 ALL	+=$(obj).depend $(LIB)
 
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
deleted file mode 100644
index be9d418..0000000
--- a/board/samsung/origen/lowlevel_init.S
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Lowlevel setup for ORIGEN board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include "origen_setup.h"
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-	.globl lowlevel_init
-lowlevel_init:
-	push	{lr}
-
-	/* r5 has always zero */
-	mov	r5, #0
-	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
-	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
-
-	/* check reset status */
-	ldr	r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
-	ldr	r1, [r0]
-
-	/* AFTR wakeup reset */
-	ldr	r2, =S5P_CHECK_DIDLE
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* LPA wakeup reset */
-	ldr	r2, =S5P_CHECK_LPA
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* Sleep wakeup reset */
-	ldr	r2, =S5P_CHECK_SLEEP
-	cmp	r1, r2
-	beq	wakeup_reset
-
-	/*
-	 * If U-boot is already running in ram, no need to relocate U-Boot.
-	 * Memory controller must be configured before relocating U-Boot
-	 * in ram.
-	 */
-	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
-	bic	r1, pc, r0		/* pc <- current addr of code */
-					/* r1 <- unmasked bits of pc */
-	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
-	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
-	cmp	r1, r2			/* compare r1, r2 */
-	beq	1f			/* r0 == r1 then skip sdram init */
-
-	/* init system clock */
-	bl system_clock_init
-
-	/* Memory initialize */
-	bl mem_ctrl_asm_init
-
-1:
-	/* for UART */
-	bl uart_asm_init
-	bl arch_cpu_init
-	bl tzpc_init
-	pop	{pc}
-
-wakeup_reset:
-	bl system_clock_init
-	bl mem_ctrl_asm_init
-	bl arch_cpu_init
-	bl tzpc_init
-
-exit_wakeup:
-	/* Load return address and jump to kernel */
-	ldr	r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
-
-	/* r1 = physical address of exynos4210_cpu_resume function */
-	ldr	r1, [r0]
-
-	/* Jump to kernel*/
-	mov	pc, r1
-	nop
-	nop
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
-	push	{lr}
-	ldr	r0, =EXYNOS4_CLOCK_BASE
-
-	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
-	ldr	r1, =CLK_SRC_CPU_VAL
-	ldr	r2, =CLK_SRC_CPU_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-2:	subs	r1, r1, #1
-	bne	2b
-
-	ldr	r1, =CLK_SRC_TOP0_VAL
-	ldr	r2, =CLK_SRC_TOP0_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =CLK_SRC_TOP1_VAL
-	ldr	r2, =CLK_SRC_TOP1_OFFSET
-	str	r1, [r0, r2]
-
-	/* DMC */
-	ldr	r1, =CLK_SRC_DMC_VAL
-	ldr	r2, =CLK_SRC_DMC_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_SRC_LEFTBUS */
-	ldr	r1, =CLK_SRC_LEFTBUS_VAL
-	ldr	r2, =CLK_SRC_LEFTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_SRC_RIGHTBUS */
-	ldr	r1, =CLK_SRC_RIGHTBUS_VAL
-	ldr	r2, =CLK_SRC_RIGHTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
-	ldr	r1, =CLK_SRC_FSYS_VAL
-	ldr	r2, =CLK_SRC_FSYS_OFFSET
-	str	r1, [r0, r2]
-
-	/* UART[0:4] */
-	ldr	r1, =CLK_SRC_PERIL0_VAL
-	ldr	r2, =CLK_SRC_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CAM , FIMC 0-3 */
-	ldr	r1, =CLK_SRC_CAM_VAL
-	ldr	r2, =CLK_SRC_CAM_OFFSET
-	str	r1, [r0, r2]
-
-	/* MFC */
-	ldr	r1, =CLK_SRC_MFC_VAL
-	ldr	r2, =CLK_SRC_MFC_OFFSET
-	str	r1, [r0, r2]
-
-	/* G3D */
-	ldr	r1, =CLK_SRC_G3D_VAL
-	ldr	r2, =CLK_SRC_G3D_OFFSET
-	str	r1, [r0, r2]
-
-	/* LCD0 */
-	ldr	r1, =CLK_SRC_LCD0_VAL
-	ldr	r2, =CLK_SRC_LCD0_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-3:	subs	r1, r1, #1
-	bne	3b
-
-	/* CLK_DIV_CPU0 */
-	ldr	r1, =CLK_DIV_CPU0_VAL
-	ldr	r2, =CLK_DIV_CPU0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_CPU1 */
-	ldr	r1, =CLK_DIV_CPU1_VAL
-	ldr	r2, =CLK_DIV_CPU1_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_DMC0 */
-	ldr	r1, =CLK_DIV_DMC0_VAL
-	ldr	r2, =CLK_DIV_DMC0_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_DIV_DMC1 */
-	ldr	r1, =CLK_DIV_DMC1_VAL
-	ldr	r2, =CLK_DIV_DMC1_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_LEFTBUS */
-	ldr	r1, =CLK_DIV_LEFTBUS_VAL
-	ldr	r2, =CLK_DIV_LEFTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_RIGHTBUS */
-	ldr	r1, =CLK_DIV_RIGHTBUS_VAL
-	ldr	r2, =CLK_DIV_RIGHTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_TOP */
-	ldr	r1, =CLK_DIV_TOP_VAL
-	ldr	r2, =CLK_DIV_TOP_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC[0:1] */
-	ldr	r1, =CLK_DIV_FSYS1_VAL		/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =CLK_DIV_FSYS1_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC[2:3] */
-	ldr	r1, =CLK_DIV_FSYS2_VAL		/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =CLK_DIV_FSYS2_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC4 */
-	ldr	r1, =CLK_DIV_FSYS3_VAL		/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =CLK_DIV_FSYS3_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_PERIL0: UART Clock Divisors */
-	ldr	r1, =CLK_DIV_PERIL0_VAL
-	ldr	r2, =CLK_DIV_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CAM, FIMC 0-3: CAM Clock Divisors */
-	ldr	r1, =CLK_DIV_CAM_VAL
-	ldr	r2, =CLK_DIV_CAM_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_MFC: MFC Clock Divisors */
-	ldr	r1, =CLK_DIV_MFC_VAL
-	ldr	r2, =CLK_DIV_MFC_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_G3D: G3D Clock Divisors */
-	ldr	r1, =CLK_DIV_G3D_VAL
-	ldr	r2, =CLK_DIV_G3D_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_LCD0: LCD0 Clock Divisors */
-	ldr	r1, =CLK_DIV_LCD0_VAL
-	ldr	r2, =CLK_DIV_LCD0_OFFSET
-	str	r1, [r0, r2]
-
-	/* Set PLL locktime */
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =APLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =MPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =EPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =VPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	/* APLL_CON1 */
-	ldr	r1, =APLL_CON1_VAL
-	ldr	r2, =APLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* APLL_CON0 */
-	ldr	r1, =APLL_CON0_VAL
-	ldr	r2, =APLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* MPLL_CON1 */
-	ldr	r1, =MPLL_CON1_VAL
-	ldr	r2, =MPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* MPLL_CON0 */
-	ldr	r1, =MPLL_CON0_VAL
-	ldr	r2, =MPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* EPLL */
-	ldr	r1, =EPLL_CON1_VAL
-	ldr	r2, =EPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* EPLL_CON0 */
-	ldr	r1, =EPLL_CON0_VAL
-	ldr	r2, =EPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* VPLL_CON1 */
-	ldr	r1, =VPLL_CON1_VAL
-	ldr	r2, =VPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* VPLL_CON0 */
-	ldr	r1, =VPLL_CON0_VAL
-	ldr	r2, =VPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x30000
-4:	subs	r1, r1, #1
-	bne	4b
-
-	pop	{pc}
-/*
- * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
- * void uart_asm_init(void)
- */
-	.globl uart_asm_init
-uart_asm_init:
-
-	/* setup UART0-UART3 GPIOs (part1) */
-	mov	r0, r7
-	ldr	r1, =EXYNOS4_GPIO_A0_CON_VAL
-	str	r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
-	ldr	r1, =EXYNOS4_GPIO_A1_CON_VAL
-	str	r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
-
-	ldr r0, =EXYNOS4_UART_BASE
-	add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
-
-	ldr	r1, =ULCON_VAL
-	str	r1, [r0, #ULCON_OFFSET]
-	ldr	r1, =UCON_VAL
-	str	r1, [r0, #UCON_OFFSET]
-	ldr	r1, =UFCON_VAL
-	str	r1, [r0, #UFCON_OFFSET]
-	ldr	r1, =UBRDIV_VAL
-	str	r1, [r0, #UBRDIV_OFFSET]
-	ldr	r1, =UFRACVAL_VAL
-	str	r1, [r0, #UFRACVAL_OFFSET]
-	mov	pc, lr
-	nop
-	nop
-	nop
-
diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S
deleted file mode 100644
index b49b193..0000000
--- a/board/samsung/origen/mem_setup.S
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Memory setup for ORIGEN board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include "origen_setup.h"
-#define SET_MIU
-
-	.globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-	/*
-	 * Async bridge configuration at CPU_core:
-	 * 1: half_sync
-	 * 0: full_sync
-	 */
-	ldr r0, =ASYNC_CONFIG
-	mov r1, #1
-	str r1, [r0]
-
-#ifdef SET_MIU
-	ldr	r0, =EXYNOS4_MIU_BASE
-	/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
-	ldr	r1, =0x20001507
-	str	r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
-
-	/* Update MIU Configuration */
-	ldr	r1, =0x00000001
-	str	r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
-#endif
-	/* DREX0 */
-	ldr	r0, =EXYNOS4_DMC0_BASE
-
-	/*
-	 * DLL Parameter Setting:
-	 * Termination: Enable R/W
-	 * Phase Delay for DQS Cleaning: 180' Shift
-	 */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/*
-	 * ZQ Calibration
-	 * Termination: Disable
-	 * Auto Calibration Start: Enable
-	 */
-	ldr	r1, =0xE3855703
-	str	r1, [r0, #DMC_PHYZQCONTROL]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	/*
-	 * Update DLL Information:
-	 * Force DLL Resyncronization
-	 */
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Reset Force DLL Resyncronization */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Enable Differential DQS, DLL Off*/
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Activate PHY DLL: DLL On */
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Set DLL Parameters */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* DLL Start */
-	ldr	r1, =0x7110100B
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #DMC_PHYCONTROL2]
-
-	/* Set Clock Ratio of Bus clock to Memory Clock */
-	ldr	r1, =0x0FFF301a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	/*
-	 * Memor Burst length: 8
-	 * Number of chips: 2
-	 * Memory Bus width: 32 bit
-	 * Memory Type: DDR3
-	 * Additional Latancy for PLL: 1 Cycle
-	 */
-	ldr	r1, =0x00312640
-	str	r1, [r0, #DMC_MEMCONTROL]
-
-	/*
-	 * Memory Configuration Chip 0
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x20e01323
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	/*
-	 * Memory Configuration Chip 1
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #DMC_MEMCONFIG1]
-
-	/* Config Precharge Policy */
-	ldr	r1, =0xff000000
-	str	r1, [r0, #DMC_PRECHCONFIG]
-
-	/*
-	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
-	 * Values as per Memory AC Parameters
-	 */
-	ldr	r1, =0x000000BB
-	str	r1, [r0, #DMC_TIMINGAREF]
-	ldr	r1, =0x4046654f
-	str	r1, [r0, #DMC_TIMINGROW]
-	ldr	r1, =0x46400506
-	str	r1, [r0, #DMC_TIMINGDATA]
-	ldr	r1, =0x52000A3C
-	str	r1, [r0, #DMC_TIMINGPOWER]
-
-	/* Chip0: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-2:	subs	r2, r2, #1
-	bne	2b
-
-	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00020000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00030000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00010002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00000328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-3:	subs	r2, r2, #1
-	bne	3b
-
-	/* Chip0: ZQINIT */
-	ldr	r1, =0x0a000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-4:	subs	r2, r2, #1
-	bne	4b
-
-	/* Chip1: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-5:	subs	r2, r2, #1
-	bne	5b
-
-	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00120000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00130000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00110002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00100328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-6:	subs	r2, r2, #1
-	bne	6b
-
-	/* Chip1: ZQINIT */
-	ldr	r1, =0x0a100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-7:	subs	r2, r2, #1
-	bne	7b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-8:	subs	r2, r2, #1
-	bne	8b
-
-	/* DREX1 */
-	ldr	r0, =EXYNOS4_DMC1_BASE	@0x10410000
-
-	/*
-	 * DLL Parameter Setting:
-	 * Termination: Enable R/W
-	 * Phase Delay for DQS Cleaning: 180' Shift
-	 */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/*
-	 * ZQ Calibration:
-	 * Termination: Disable
-	 * Auto Calibration Start: Enable
-	 */
-	ldr	r1, =0xE3855703
-	str	r1, [r0, #DMC_PHYZQCONTROL]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	/*
-	 * Update DLL Information:
-	 * Force DLL Resyncronization
-	 */
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Reset Force DLL Resyncronization */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Enable Differential DQS, DLL Off*/
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Activate PHY DLL: DLL On */
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Set DLL Parameters */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* DLL Start */
-	ldr	r1, =0x7110100B
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #DMC_PHYCONTROL2]
-
-	/* Set Clock Ratio of Bus clock to Memory Clock */
-	ldr	r1, =0x0FFF301a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	/*
-	 * Memor Burst length: 8
-	 * Number of chips: 2
-	 * Memory Bus width: 32 bit
-	 * Memory Type: DDR3
-	 * Additional Latancy for PLL: 1 Cycle
-	 */
-	ldr	r1, =0x00312640
-	str	r1, [r0, #DMC_MEMCONTROL]
-
-	/*
-	 * Memory Configuration Chip 0
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x20e01323
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	/*
-	 * Memory Configuration Chip 1
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #DMC_MEMCONFIG1]
-
-	/* Config Precharge Policy */
-	ldr	r1, =0xff000000
-	str	r1, [r0, #DMC_PRECHCONFIG]
-
-	/*
-	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
-	 * Values as per Memory AC Parameters
-	 */
-	ldr	r1, =0x000000BB
-	str	r1, [r0, #DMC_TIMINGAREF]
-	ldr	r1, =0x4046654f
-	str	r1, [r0, #DMC_TIMINGROW]
-	ldr	r1, =0x46400506
-	str	r1, [r0, #DMC_TIMINGDATA]
-	ldr	r1, =0x52000A3C
-	str	r1, [r0, #DMC_TIMINGPOWER]
-
-	/* Chip0: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-2:	subs	r2, r2, #1
-	bne	2b
-
-	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00020000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00030000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00010002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00000328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-3:	subs	r2, r2, #1
-	bne	3b
-
-	/* Chip 0: ZQINIT */
-	ldr	r1, =0x0a000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-4:	subs	r2, r2, #1
-	bne	4b
-
-	/* Chip1: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-5:	subs	r2, r2, #1
-	bne	5b
-
-	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00120000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00130000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00110002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00100328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-6:	subs	r2, r2, #1
-	bne	6b
-
-	/* Chip1: ZQINIT */
-	ldr	r1, =0x0a100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-7:	subs	r2, r2, #1
-	bne	7b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-8:	subs	r2, r2, #1
-	bne	8b
-
-	/* turn on DREX0, DREX1 */
-	ldr	r0, =EXYNOS4_DMC0_BASE
-	ldr	r1, =0x0FFF303a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	ldr	r0, =EXYNOS4_DMC1_BASE
-	ldr	r1, =0x0FFF303a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	mov	pc, lr
diff --git a/board/samsung/origen/mmc_boot.c b/board/samsung/origen/mmc_boot.c
deleted file mode 100644
index 072f161..0000000
--- a/board/samsung/origen/mmc_boot.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
-	u32 (*copy_bl2)(u32, u32, u32)  = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
-
-	copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
-}
-
-void board_init_f(unsigned long bootflag)
-{
-	__attribute__((noreturn)) void (*uboot)(void);
-	copy_uboot_to_ram();
-
-	/* Jump to U-Boot image */
-	uboot = (void *)CONFIG_SYS_TEXT_BASE;
-	(*uboot)();
-	/* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-	/* Function attribute is no-return */
-	/* This Function never executes */
-	while (1)
-		;
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
index 638e7b1..b7dbb91 100644
--- a/board/samsung/origen/origen.c
+++ b/board/samsung/origen/origen.c
@@ -25,6 +25,8 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 struct exynos4_gpio_part1 *gpio1;
@@ -39,6 +41,50 @@ int board_init(void)
 	return 0;
 }
 
+static int board_uart_init(void)
+{
+	int err;
+
+	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART0 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART1 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART2 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART3 not configured\n");
+		return err;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+	return err;
+}
+#endif
+
 int dram_init(void)
 {
 	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index f2c32ee..9412e37 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-SOBJS	:= lowlevel_init.o
-
-COBJS	:= clock_init.o
-COBJS	+= dmc_common.o dmc_init_ddr3.o
 COBJS	+= smdk5250_spl.o
 
 ifndef CONFIG_SPL_BUILD
@@ -38,14 +34,10 @@ COBJS	+= smdk5250.o
 endif
 endif
 
-ifdef CONFIG_SPL_BUILD
-COBJS	+= spl_boot.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
-ALL	:=	 $(obj).depend $(LIB)
+ALL	:= $(obj).depend $(LIB)
 
 all:	$(ALL)
 
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 276fd41..f1d3d97 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -144,7 +144,7 @@ int power_init_board(void)
 
 	/* VDD_MIF */
 	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
-						MAX77686_BUCK1OUT_1V)) {
+						MAX77686_BUCK1OUT_1_05V)) {
 		debug("%s: PMIC %d register write failed\n", __func__,
 						MAX77686_REG_PMIC_BUCK1OUT);
 		return -1;
@@ -332,6 +332,16 @@ static int board_uart_init(void)
 	return ret;
 }
 
+void board_i2c_init(const void *blob)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
+		exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+				     PINMUX_FLAG_NONE);
+	}
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile
index 56e0c16..c4cd0a3 100644
--- a/board/samsung/smdkv310/Makefile
+++ b/board/samsung/smdkv310/Makefile
@@ -24,18 +24,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-SOBJS	:= mem_setup.o
-SOBJS	+= lowlevel_init.o
 ifndef CONFIG_SPL_BUILD
 COBJS	+= smdkv310.o
 endif
 
-ifdef CONFIG_SPL_BUILD
-COBJS	+= mmc_boot.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 ALL	:=	 $(obj).depend $(LIB)
 
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
deleted file mode 100644
index 31e0e2e..0000000
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
- * Lowlevel setup for SMDKV310 board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-#define MEM_DLLl_ON
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-	.globl lowlevel_init
-lowlevel_init:
-	push	{lr}
-
-	/* r5 has always zero */
-	mov	r5, #0
-	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
-	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
-
-	/* check reset status  */
-	ldr     r0, =(EXYNOS4_POWER_BASE + 0x81C)	@ INFORM7
-	ldr     r1, [r0]
-
-	/* AFTR wakeup reset */
-	ldr	r2, =S5P_CHECK_DIDLE
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* Sleep wakeup reset */
-	ldr	r2, =S5P_CHECK_SLEEP
-	cmp	r1, r2
-	beq	wakeup_reset
-
-	/*
-	 * If U-boot is already running in ram, no need to relocate U-Boot.
-	 * Memory controller must be configured before relocating U-Boot
-	 * in ram.
-	 */
-	ldr	r0, =0x00ffffff		/* r0 <- Mask Bits*/
-	bic	r1, pc, r0		/* pc <- current addr of code */
-					/* r1 <- unmasked bits of pc */
-
-	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
-	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
-	cmp     r1, r2                  /* compare r1, r2 */
-	beq     1f			/* r0 == r1 then skip sdram init */
-
-	/* init system clock */
-	bl system_clock_init
-
-	/* Memory initialize */
-	bl mem_ctrl_asm_init
-
-1:
-	/* for UART */
-	bl uart_asm_init
-	bl arch_cpu_init
-	bl tzpc_init
-	pop	{pc}
-
-wakeup_reset:
-	bl system_clock_init
-	bl mem_ctrl_asm_init
-	bl arch_cpu_init
-	bl tzpc_init
-
-exit_wakeup:
-	/* Load return address and jump to kernel */
-	ldr     r0, =(EXYNOS4_POWER_BASE + 0x800)	@ INFORM0
-
-	/* r1 = physical address of exynos4210_cpu_resume function */
-	ldr	r1, [r0]
-
-	/* Jump to kernel*/
-	mov	pc, r1
-	nop
-	nop
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
-	push	{lr}
-	ldr	r0, =EXYNOS4_CLOCK_BASE
-
-	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
-	ldr	r1, =0x0101
-	ldr	r2, =0x14200			@CLK_SRC_CPU
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-2:	subs	r1, r1, #1
-	bne	2b
-
-	ldr	r1, =0x00
-	ldr	r2, =0x0C210			@CLK_SRC_TOP0
-	str	r1, [r0, r2]
-
-	ldr	r1, =0x00
-	ldr	r2, =0x0C214			@CLK_SRC_TOP1_OFFSET
-	str	r1, [r0, r2]
-
-	/* DMC */
-	ldr	r1, =0x00
-	ldr	r2, =0x10200			@CLK_SRC_DMC_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_SRC_LEFTBUS */
-	ldr	r1, =0x00
-	ldr	r2, =0x04200			@CLK_SRC_LEFTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_SRC_RIGHTBUS */
-	ldr	r1, =0x00
-	ldr	r2, =0x08200			@CLK_SRC_RIGHTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
-	ldr	r1, =0x066666
-	ldr	r2, =0x0C240			@ CLK_SRC_FSYS
-	str	r1, [r0, r2]
-
-	/* UART[0:4], PWM: SCLKMPLL(6) */
-	ldr	r1, =0x06666666
-	ldr	r2, =0x0C250			@CLK_SRC_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-3:	subs	r1, r1, #1
-	bne	3b
-
-	/*
-	 * CLK_DIV_CPU0:
-	 *
-	 * PCLK_DBG_RATIO[20]	0x1
-	 * ATB_RATIO[16]	0x3
-	 * PERIPH_RATIO[12]	0x3
-	 * COREM1_RATIO[8]	0x7
-	 * COREM0_RATIO[4]	0x3
-	 */
-	ldr	r1, =0x0133730
-	ldr	r2, =0x14500			@CLK_DIV_CPU0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_CPU1: COPY_RATIO [0]	0x3 */
-	ldr	r1, =0x03
-	ldr	r2, =0x14504			@CLK_DIV_CPU1_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * CLK_DIV_DMC0:
-	 *
-	 * CORE_TIMERS_RATIO[28]	0x1
-	 * COPY2_RATIO[24]	0x3
-	 * DMCP_RATIO[20]	0x1
-	 * DMCD_RATIO[16]	0x1
-	 * DMC_RATIO[12]	0x1
-	 * DPHY_RATIO[8]	0x1
-	 * ACP_PCLK_RATIO[4]	0x1
-	 * ACP_RATIO[0]		0x3
-	 */
-	ldr	r1, =0x13111113
-	ldr	r2, =0x010500			@CLK_DIV_DMC0_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * CLK_DIV_DMC1:
-	 *
-	 * DPM_RATIO[24]	0x1
-	 * DVSEM_RATIO[16]	0x1
-	 * PWI_RATIO[8]		0x1
-	 */
-	ldr	r1, =0x01010100
-	ldr	r2, =0x010504			@CLK_DIV_DMC1_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * CLK_DIV_LEFRBUS:
-	 *
-	 * GPL_RATIO[4]		0x1
-	 * GDL_RATIO[0]		0x3
-	 */
-	ldr	r1, =0x013
-	ldr	r2, =0x04500			@CLK_DIV_LEFTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * CLK_DIV_RIGHTBUS:
-	 *
-	 * GPR_RATIO[4]		0x1
-	 * GDR_RATIO[0]		0x3
-	 */
-	ldr	r1, =0x013
-	ldr	r2, =0x08500			@CLK_DIV_RIGHTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * CLK_DIV_TOP:
-	 *
-	 * ONENAND_RATIO[16]	0x0
-	 * ACLK_133_RATIO[12]	0x5
-	 * ACLK_160_RATIO[8]	0x4
-	 * ACLK_100_RATIO[4]	0x7
-	 * ACLK_200_RATIO[0]	0x3
-	 */
-	ldr	r1, =0x05473
-	ldr	r2, =0x0C510			@CLK_DIV_TOP_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC[0:1] */
-	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =0x0C544			@ CLK_DIV_FSYS1
-	str	r1, [r0, r2]
-
-	/* MMC[2:3] */
-	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
-	str	r1, [r0, r2]
-
-	/* MMC4 */
-	ldr	r1, =0x000f			/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =0x0C54C			@ CLK_DIV_FSYS3
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-4:	subs	r1, r1, #1
-	bne	4b
-
-	/*
-	 * CLK_DIV_PERIL0:
-	 *
-	 * UART5_RATIO[20]	8
-	 * UART4_RATIO[16]	8
-	 * UART3_RATIO[12]	8
-	 * UART2_RATIO[8]	8
-	 * UART1_RATIO[4]	8
-	 * UART0_RATIO[0]	8
-	 */
-	ldr	r1, =0x774777
-	ldr	r2, =0x0C550			@CLK_DIV_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* SLIMBUS: ???, PWM */
-	ldr	r1, =0x8
-	ldr	r2, =0x0C55C			@ CLK_DIV_PERIL3
-	str	r1, [r0, r2]
-
-	/* Set PLL locktime */
-	ldr	r1, =0x01C20
-	ldr	r2, =0x014000			@APLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-	ldr	r1, =0x01C20
-	ldr	r2, =0x014008			@MPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-	ldr	r1, =0x01C20
-	ldr	r2, =0x0C010			@EPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-	ldr	r1, =0x01C20
-	ldr	r2, =0x0C020			@VPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * APLL_CON1:
-	 *
-	 * APLL_AFC_ENB[31]	0x1
-	 * APLL_AFC[0]		0xC
-	 */
-	ldr	r1, =0x8000000C
-	ldr	r2, =0x014104			@APLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * APLL_CON0:
-	 *
-	 * APLL_MDIV[16]	0xFA
-	 * APLL_PDIV[8]		0x6
-	 * APLL_SDIV[0]		0x1
-	 */
-	ldr	r1, =0x80FA0601
-	ldr	r2, =0x014100			@APLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * MPLL_CON1:
-	 *
-	 * MPLL_AFC_ENB[31]	0x1
-	 * MPLL_AFC[0]		0x1C
-	 */
-	ldr	r1, =0x0000001C
-	ldr	r2, =0x01410C			@MPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * MPLL_CON0:
-	 *
-	 * MPLL_MDIV[16]	0xC8
-	 * MPLL_PDIV[8]		0x6
-	 * MPLL_SDIV[0]		0x1
-	 */
-	ldr	r1, =0x80C80601
-	ldr	r2, =0x014108			@MPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* EPLL */
-	ldr	r1, =0x0
-	ldr	r2, =0x0C114			@EPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * EPLL_CON0:
-	 *
-	 * EPLL_MDIV[16]	0x30
-	 * EPLL_PDIV[8]		0x3
-	 * EPLL_SDIV[0]		0x2
-	 */
-	ldr	r1, =0x80300302
-	ldr	r2, =0x0C110			@EPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * VPLL_CON1:
-	 *
-	 * VPLL_MRR[24]		0x11
-	 * VPLL_MFR[16]		0x0
-	 * VPLL_K[0]		0x400
-	 */
-	ldr	r1, =0x11000400
-	ldr	r2, =0x0C124			@VPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/*
-	 * VPLL_CON0:
-	 *
-	 * VPLL_MDIV[16]	0x35
-	 * VPLL_PDIV[8]		0x3
-	 * VPLL_SDIV[0]		0x2
-	 */
-	ldr	r1, =0x80350302
-	ldr	r2, =0x0C120			@VPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x30000
-3:	subs	r1, r1, #1
-	bne	3b
-
-	pop	{pc}
-/*
- * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
- * void uart_asm_init(void)
- */
-	.globl uart_asm_init
-uart_asm_init:
-
-	/* setup UART0-UART3 GPIOs (part1) */
-	mov	r0, r7
-	ldr	r1, =0x22222222
-	str	r1, [r0, #0x00]			@ EXYNOS4_GPIO_A0_OFFSET
-	ldr	r1, =0x00222222
-	str	r1, [r0, #0x20]			@ EXYNOS4_GPIO_A1_OFFSET
-
-	ldr r0, =EXYNOS4_UART_BASE
-	add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
-
-	ldr r1, =0x3C5
-	str	r1, [r0, #0x4]
-	ldr r1, =0x111
-	str	r1, [r0, #0x8]
-	ldr r1, =0x3
-	str	r1, [r0, #0x0]
-	ldr r1, =0x35
-	str	r1, [r0, #0x28]
-	ldr r1, =0x4
-	str	r1, [r0, #0x2c]
-
-	mov	pc, lr
-	nop
-	nop
-	nop
diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
deleted file mode 100644
index d3b6265..0000000
--- a/board/samsung/smdkv310/mem_setup.S
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * Memory setup for SMDKV310 board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#define SET_MIU
-
-#define MEM_DLL
-
-#ifdef CONFIG_CLK_800_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_200_200
-#define DRAM_CLK_200
-#endif
-#ifdef CONFIG_CLK_1000_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_400_200
-#define DRAM_CLK_400
-#endif
-
-	.globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-
-	/*
-	* Async bridge configuration at CPU_core:
-	* 1: half_sync
-	* 0: full_sync
-	*/
-	ldr r0, =0x10010350
-	mov r1, #1
-	str r1, [r0]
-
-#ifdef SET_MIU
-	ldr	r0, =EXYNOS4_MIU_BASE	@0x10600000
-#ifdef CONFIG_MIU_1BIT_INTERLEAVED
-	ldr	r1, =0x0000000c
-	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
-	ldr	r1, =0x40000000
-	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
-	ldr	r1, =0xbfffffff
-	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
-	ldr	r1, =0x00000001
-	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
-#endif
-#ifdef CONFIG_MIU_2BIT_INTERLEAVED
-	ldr	r1, =0x2000150c
-	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
-	ldr	r1, =0x40000000
-	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
-	ldr	r1, =0xbfffffff
-	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
-	ldr	r1, =0x00000001
-	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
-#endif
-#ifdef CONFIG_MIU_LINEAR
-	ldr	r1, =0x40000000
-	str	r1, [r0, #0x818]	@MIU_SINGLE_MAPPING0_START_ADDR
-	ldr	r1, =0x7fffffff
-	str	r1, [r0, #0x820]	@MIU_SINGLE_MAPPING0_END_ADDR
-	ldr	r1, =0x80000000
-	str	r1, [r0, #0x828]	@MIU_SINGLE_MAPPING1_START_ADDR
-	ldr	r1, =0xbfffffff
-	str	r1, [r0, #0x830]	@MIU_SINGLE_MAPPING1_END_ADDR]
-	ldr	r1, =0x00000006
-	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
-#endif
-#endif
-	/* DREX0 */
-	ldr	r0, =EXYNOS4_DMC0_BASE	@0x10400000
-
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-
-	ldr	r1, =0xE3855703
-	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
-
-	mov	r2, #0x100000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-
-	ldr	r1, =0x71101008
-	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-	ldr	r1, =0x7110100B
-	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
-
-	ldr	r1, =0x0FFF301a
-	str	r1, [r0, #0x00]		@DMC_CONCONTROL
-	ldr	r1, =0x00312640
-	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
-
-#ifdef CONFIG_MIU_LINEAR
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
-	ldr	r1, =0x60e01323
-	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
-#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
-	ldr	r1, =0x20e01323
-	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
-#endif
-
-	ldr	r1, =0xff000000
-	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
-
-	ldr	r1, =0x000000BC
-	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
-
-#ifdef DRAM_CLK_330
-	ldr	r1, =0x3545548d
-	str	r1, [r0, #0x34]		@DMC_TIMINGROW
-	ldr	r1, =0x45430506
-	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
-	ldr	r1, =0x4439033c
-	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
-#endif
-#ifdef DRAM_CLK_400
-	ldr	r1, =0x4046654f
-	str	r1, [r0, #0x34]		@DMC_TIMINGROW
-	ldr	r1, =0x56500506
-	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
-	ldr	r1, =0x5444033d
-	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
-#endif
-	ldr	r1, =0x07000000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-2:	subs	r2, r2, #1
-	bne	2b
-
-	ldr	r1, =0x00020000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00030000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00010002
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00000328
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-3:	subs	r2, r2, #1
-	bne	3b
-
-	ldr	r1, =0x0a000000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-4:	subs	r2, r2, #1
-	bne	4b
-
-	ldr	r1, =0x07100000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-5:	subs	r2, r2, #1
-	bne	5b
-
-	ldr	r1, =0x00120000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00130000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00110002
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00100328
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-6:	subs	r2, r2, #1
-	bne	6b
-
-	ldr	r1, =0x0a100000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-7:	subs	r2, r2, #1
-	bne	7b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-
-	mov	r2, #0x100000
-8:	subs	r2, r2, #1
-	bne	8b
-
-	/* DREX1 */
-	ldr	r0, =EXYNOS4_DMC1_BASE	@0x10410000
-
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-
-	ldr	r1, =0xE3855703
-	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
-
-	mov	r2, #0x100000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-
-	ldr	r1, =0x71101008
-	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-	ldr	r1, =0x7110100B
-	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
-
-	ldr	r1, =0x0FFF301a
-	str	r1, [r0, #0x00]		@DMC_CONCONTROL
-	ldr	r1, =0x00312640
-	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
-
-#ifdef CONFIG_MIU_LINEAR
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
-	ldr	r1, =0x60e01323
-	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
-#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
-	ldr	r1, =0x20e01323
-	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
-#endif
-
-	ldr	r1, =0xff000000
-	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
-
-	ldr	r1, =0x000000BC
-	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
-
-#ifdef DRAM_CLK_330
-	ldr	r1, =0x3545548d
-	str	r1, [r0, #0x34]		@DMC_TIMINGROW
-	ldr	r1, =0x45430506
-	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
-	ldr	r1, =0x4439033c
-	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
-#endif
-#ifdef DRAM_CLK_400
-	ldr	r1, =0x4046654f
-	str	r1, [r0, #0x34]		@DMC_TIMINGROW
-	ldr	r1, =0x56500506
-	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
-	ldr	r1, =0x5444033d
-	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
-#endif
-
-	ldr	r1, =0x07000000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-2:	subs	r2, r2, #1
-	bne	2b
-
-	ldr	r1, =0x00020000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00030000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00010002
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00000328
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-3:	subs	r2, r2, #1
-	bne	3b
-
-	ldr	r1, =0x0a000000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-4:	subs	r2, r2, #1
-	bne	4b
-
-	ldr	r1, =0x07100000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-5:	subs	r2, r2, #1
-	bne	5b
-
-	ldr	r1, =0x00120000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00130000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00110002
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-	ldr	r1, =0x00100328
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-6:	subs	r2, r2, #1
-	bne	6b
-
-	ldr	r1, =0x0a100000
-	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
-
-	mov	r2, #0x100000
-7:	subs	r2, r2, #1
-	bne	7b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
-
-	mov	r2, #0x100000
-8:	subs	r2, r2, #1
-	bne	8b
-
-	/* turn on DREX0, DREX1 */
-	ldr	r0, =0x10400000		@APB_DMC_0_BASE
-	ldr	r1, =0x0FFF303a
-	str	r1, [r0, #0x00]		@DMC_CONCONTROL
-
-	ldr	r0, =0x10410000		@APB_DMC_1_BASE
-	ldr	r1, =0x0FFF303a
-	str	r1, [r0, #0x00]		@DMC_CONCONTROL
-
-	mov	pc, lr
diff --git a/board/samsung/smdkv310/mmc_boot.c b/board/samsung/smdkv310/mmc_boot.c
deleted file mode 100644
index d3fc18d..0000000
--- a/board/samsung/smdkv310/mmc_boot.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
-	u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR;
-
-	copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
-}
-
-void board_init_f(unsigned long bootflag)
-{
-	__attribute__((noreturn)) void (*uboot)(void);
-	copy_uboot_to_ram();
-
-	/* Jump to U-Boot image */
-	uboot = (void *)CONFIG_SYS_TEXT_BASE;
-	(*uboot)();
-	/* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-	/*Function attribute is no-return*/
-	/*This Function never executes*/
-	while (1)
-		;
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
-{
-}
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index 81ac8f6..015b920 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -26,6 +26,8 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -137,3 +139,47 @@ int board_mmc_init(bd_t *bis)
 	return err;
 }
 #endif
+
+static int board_uart_init(void)
+{
+	int err;
+
+	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART0 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART1 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART2 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART3 not configured\n");
+		return err;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+	return err;
+}
+#endif
diff --git a/board/wandboard/README b/board/wandboard/README
index ce83bbe..498db2f 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -22,6 +22,11 @@ To build U-Boot for the Wandboard Solo version:
 $ make wandboard_solo_config
 $ make
 
+To build U-Boot for the Wandboard Quad version:
+
+$ make wandboard_quad_config
+$ make
+
 Flashing U-boot into the SD card
 --------------------------------
 
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 5666cbf..43c02ac 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -48,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_DDR_MB * SZ_1M;
+	gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
 
 	return 0;
 }
diff --git a/boards.cfg b/boards.cfg
index c0c4282..dd2cd98 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -267,9 +267,10 @@ ima3-mx53                    arm         armv7       ima3-mx53           esg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 cgtqmx6qeval				 arm		 armv7		 cgtqmx6eval		 congatec		mx6		cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
-mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
+mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
-mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6		mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6dlsabresd                 arm         armv7       mx6sabresd          freescale      mx6		mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
+mx6qsabresd                  arm         armv7       mx6sabresd          freescale      mx6		mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6slevk                     arm         armv7       mx6slevk            freescale      mx6		mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 titanium                     arm         armv7       titanium            freescale      mx6		titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
 vf610twr                     arm         armv7       vf610twr            freescale      vf610		vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
@@ -281,6 +282,7 @@ nitrogen6q2g                 arm         armv7       nitrogen6x          boundar
 nitrogen6s                   arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
 nitrogen6s1g                 arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
 wandboard_dl		     arm	 armv7	     wandboard		 -		mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
+wandboard_quad		     arm	 armv7	     wandboard		 -		mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
 wandboard_solo		     arm	 armv7	     wandboard		 -		mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
@@ -352,6 +354,7 @@ lp8x4x                       arm         pxa         lp8x4x              icpdas
 lubbock                      arm         pxa
 palmld                       arm         pxa
 palmtc                       arm         pxa
+palmtreo680                  arm         pxa
 polaris                      arm         pxa         trizepsiv           -              -           trizepsiv:POLARIS
 pxa255_idp                   arm         pxa
 trizepsiv                    arm         pxa
diff --git a/doc/README.mx28_common b/doc/README.mx28_common
index 8bacaf8..5d9e72f 100644
--- a/doc/README.mx28_common
+++ b/doc/README.mx28_common
@@ -1,12 +1,15 @@
-Booting U-boot on a MX28 processor
-==================================
+Booting U-boot on a MXS processor
+=================================
 
-This document describes the MX28 U-Boot port. This document mostly
-covers topics related to making the module/board bootable.
+This document describes the MXS U-Boot port. This document mostly covers topics
+related to making the module/board bootable.
 
 Terminology
 -----------
 
+The term "MXS" refers to a family of Freescale SoCs that is composed by MX23
+and MX28.
+
 The dollar symbol ($) introduces a snipped of shell code. This shall be typed
 into the unix command prompt in U-Boot source code root directory.
 
@@ -17,16 +20,16 @@ Contents
 --------
 
 1) Prerequisites
-2) Compiling U-Boot for a MX28 based board
-3) Installation of U-Boot for a MX28 based board to SD card
-4) Installation of U-Boot into NAND flash
+2) Compiling U-Boot for a MXS based board
+3) Installation of U-Boot for a MXS based board to SD card
+4) Installation of U-Boot into NAND flash on a MX28 based board
 
 1) Prerequisites
 ----------------
 
-To make a MX28 based board bootable, some tools are necessary. The first one
-is the "elftosb" tool distributed by Freescale Semiconductor. The other one
-is the "mxsboot" tool found in U-Boot source tree.
+To make a MXS based board bootable, some tools are necessary. The first one is
+the "elftosb" tool distributed by Freescale Semiconductor. The other one is the
+"mxsboot" tool found in U-Boot source tree.
 
 Firstly, obtain the elftosb archive from the following location:
 
@@ -60,18 +63,18 @@ copy the binary by hand:
 Make sure the "elftosb" binary can be found in your $PATH, in this case this
 means "/usr/local/bin/" has to be in your $PATH.
 
-2) Compiling U-Boot for a MX28 based board
+2) Compiling U-Boot for a MXS based board
 -------------------------------------------
 
-Compiling the U-Boot for a MX28 board is straightforward and done as compiling U-Boot
-for any other ARM device. For cross-compiler setup, please refer to ELDK5.0
-documentation. First, clean up the source code:
+Compiling the U-Boot for a MXS board is straightforward and done as compiling
+U-Boot for any other ARM device. For cross-compiler setup, please refer to
+ELDK5.0 documentation. First, clean up the source code:
 
 	$ make mrproper
 
-Next, configure U-Boot for a MX28 based board
+Next, configure U-Boot for a MXS based board
 
-	$ make <mx28_based_board_name>_config
+	$ make <mxs_based_board_name>_config
 
 Examples:
 
@@ -83,8 +86,16 @@ Examples:
 
 	$ make mx28evk_config
 
+3. For building U-boot for Freescale MX23EVK board:
+
+	$ make mx23evk_config
+
+4. For building U-boot for Olimex MX23 Olinuxino board:
+
+	$ make mx23_olinuxino_config
+
 Lastly, compile U-Boot and prepare a "BootStream". The "BootStream" is a special
-type of file, which the i.MX28 CPU can boot. This is handled by the following
+type of file, which MXS CPUs can boot. This is handled by the following
 command:
 
 	$ make u-boot.sb
@@ -96,18 +107,16 @@ The code produces "u-boot.sb" file. This file needs to be augmented with a
 proper header to allow successful boot from SD or NAND. Adding the header is
 discussed in the following chapters.
 
-3) Installation of U-Boot for a MX28 based board to SD card
------------------------------------------------------------
-
-To boot a MX28 based board from SD, set the boot mode DIP switches according
-to i.MX28 manual chapter 12.2.1 (Table 12-2), PORT=SSP0, SD/MMC master on
-SSP0, 3.3V.
+3) Installation of U-Boot for a MXS based board to SD card
+----------------------------------------------------------
 
+To boot a MXS based board from SD, set the boot mode DIP switches according to
+to MX28 manual, section 12.2.1 (Table 12-2) or MX23 manual, section 35.1.2
+(Table 35-3).
 
-An SD card the i.MX28 CPU can use to boot U-Boot must contain a DOS partition
-table, which in turn carries a partition of special type and which contains a
-special header. The rest of partitions in the DOS partition table can be used
-by the user.
+The SD card used to boot U-Boot must contain a DOS partition table, which in
+turn carries a partition of special type and which contains a special header.
+The rest of partitions in the DOS partition table can be used by the user.
 
 To prepare such partition, use your favourite partitioning tool. The partition
 must have the following parameters:
@@ -141,17 +150,17 @@ case, we assume the first partition of the SD card is /dev/mmcblk0p1:
 
 	$ dd if=u-boot.sd of=/dev/mmcblk0p1
 
-Last step is to insert the card into MX28 based board and boot.
+Last step is to insert the card into the MXS based board and boot.
 
 NOTE: If the user needs to adjust the start sector, the "mxsboot" tool contains
       a "-p" switch for that purpose. The "-p" switch takes the sector number as
       an argument.
 
-4) Installation of U-Boot into NAND flash
------------------------------------------
+4) Installation of U-Boot into NAND flash on a MX28 based board
+---------------------------------------------------------------
 
-To boot a MX28 based board from NAND, set the boot mode DIP switches according to i.MX28
-manual chapter 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V.
+To boot a MX28 based board from NAND, set the boot mode DIP switches according
+to MX28 manual section 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V.
 
 There are two possibilities when preparing an image writable to NAND flash.
 
@@ -214,7 +223,7 @@ There are two possibilities when preparing an image writable to NAND flash.
 	--------------------------------------------
 	   There is a slight possibility of the user wanting to adjust the
 	   STRIDE and COUNT options of the NAND boot. For description of these,
-	   see i.MX28 manual section 12.12.1.2 and 12.12.1.3.
+	   see MX28 manual section 12.12.1.2 and 12.12.1.3.
 
 	   The update scripts take this possibility into account. In case the
 	   user changes STRIDE by blowing fuses, the user also has to change
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index c9b71f7..98f2c52 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -447,10 +447,13 @@ static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
 	if (buf && buf_len)
 		sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
 	opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
-	if (is_write)
+	if (is_write) {
 		opts |= 0x40;
+		flush_cache((ulong)buf, buf_len);
+	}
 	ahci_fill_cmd_slot(pp, cmd_slot, opts);
 
+	flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
 	writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
 
 	if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
@@ -458,8 +461,12 @@ static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
 		printf("timeout exit!\n");
 		return -1;
 	}
+	invalidate_dcache_range((int)(pp->cmd_slot),
+				(int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
 	debug("ahci_exec_ata_cmd: %d byte transferred.\n",
 	      pp->cmd_slot->status);
+	if (!is_write)
+		invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
 
 	return buf_len;
 }
@@ -468,7 +475,8 @@ static void ahci_set_feature(u8 dev, u8 port)
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
 	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
@@ -615,7 +623,8 @@ static void dwc_ahsata_identify(int dev, u16 *id)
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 	u8 port = probe_ent->hard_port_no;
 
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -645,7 +654,8 @@ static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 	u8 port = probe_ent->hard_port_no;
 	u32 block;
 
@@ -675,7 +685,8 @@ void dwc_ahsata_flush_cache(int dev)
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 	u8 port = probe_ent->hard_port_no;
 
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -692,7 +703,8 @@ static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 	u8 port = probe_ent->hard_port_no;
 	u64 block;
 
@@ -728,7 +740,8 @@ u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 	u8 port = probe_ent->hard_port_no;
 	u64 block;
 
@@ -769,7 +782,8 @@ void dwc_ahsata_flush_cache_ext(int dev)
 {
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-	struct sata_fis_h2d h2d, *cfis = &h2d;
+	struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+	struct sata_fis_h2d *cfis = &h2d;
 	u8 port = probe_ent->hard_port_no;
 
 	memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -912,7 +926,9 @@ int scan_sata(int dev)
 	u8 port = probe_ent->hard_port_no;
 	block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
 
-	id = (u16 *)malloc(ATA_ID_WORDS * 2);
+	id = (u16 *)memalign(ARCH_DMA_MINALIGN,
+				roundup(ARCH_DMA_MINALIGN,
+					(ATA_ID_WORDS * 2)));
 	if (!id) {
 		printf("id malloc failed\n\r");
 		return -1;
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index a30d7f0..f16e9ae 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -55,7 +55,7 @@ static inline int get_gpio_index(int gpio)
 
 int gpio_is_valid(int gpio)
 {
-	return (gpio >= 0) && (gpio < 192);
+	return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
 }
 
 static int check_gpio(int gpio)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
index 43bbf11..09b04eb 100644
--- a/drivers/gpio/s3c2440_gpio.c
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -61,7 +61,7 @@ int gpio_set_value(unsigned gpio, int value)
 	else
 		l &= ~bit;
 
-	return writel(port, l);
+	return writel(l, port);
 }
 
 int gpio_get_value(unsigned gpio)
@@ -85,11 +85,11 @@ int gpio_free(unsigned gpio)
 
 int gpio_direction_input(unsigned gpio)
 {
-	return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+	return writel(GPIO_INPUT << GPIO_BIT(gpio), GPIO_FULLPORT(gpio));
 }
 
 int gpio_direction_output(unsigned gpio, int value)
 {
-	writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+	writel(GPIO_OUTPUT << GPIO_BIT(gpio), GPIO_FULLPORT(gpio));
 	return gpio_set_value(gpio, value);
 }
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 656bf4a..4efb768 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -48,15 +48,8 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 
 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
 {
-	unsigned int value;
-
 	s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
-
-	value = readl(&bank->dat);
-	value &= ~DAT_MASK(gpio);
-	if (en)
-		value |= DAT_SET(gpio);
-	writel(value, &bank->dat);
+	s5p_gpio_set_value(bank, gpio, en);
 }
 
 void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 46d2506..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -518,8 +518,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 #ifdef CONFIG_OF_CONTROL
 void board_i2c_init(const void *blob)
 {
+	int i;
 	int node_list[CONFIG_MAX_I2C_NUM];
-	int count, i;
+	int count;
 
 	count = fdtdec_find_aliases_for_id(blob, "i2c",
 		COMPAT_SAMSUNG_S3C2440_I2C, node_list,
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index da95e28..ec5b9db 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -560,7 +560,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 		}
 		memset(fec->tbd_base, 0, size);
 		fec_tbd_init(fec);
-		flush_dcache_range((unsigned)fec->tbd_base, size);
 	}
 
 	/*
@@ -738,6 +737,28 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 	flush_dcache_range(addr, addr + size);
 
 	/*
+	 * Below we read the DMA descriptor's last four bytes back from the
+	 * DRAM. This is important in order to make sure that all WRITE
+	 * operations on the bus that were triggered by previous cache FLUSH
+	 * have completed.
+	 *
+	 * Otherwise, on MX28, it is possible to observe a corruption of the
+	 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
+	 * for the bus structure of MX28. The scenario is as follows:
+	 *
+	 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
+	 *    to DRAM due to flush_dcache_range()
+	 * 2) ARM core writes the FEC registers via AHB_ARB2
+	 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
+	 *
+	 * Note that 2) does sometimes finish before 1) due to reordering of
+	 * WRITE accesses on the AHB bus, therefore triggering 3) before the
+	 * DMA descriptor is fully written into DRAM. This results in occasional
+	 * corruption of the DMA descriptor.
+	 */
+	readl(addr + size - 4);
+
+	/*
 	 * Enable SmartDMA transmit task
 	 */
 	fec_tx_task_enable(fec);
diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c
index ca0d214..97a9661 100644
--- a/drivers/power/battery/bat_trats.c
+++ b/drivers/power/battery/bat_trats.c
@@ -41,18 +41,23 @@ static int power_battery_charge(struct pmic *bat)
 	for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) &&
 		     bat->chrg->chrg_type(p_bat->muic) &&
 		     battery->state_of_chrg < 100; k++) {
-		udelay(10000000);
-		puts(".");
+		udelay(2000000);
+		if (!(k % 5))
+			puts(".");
 		bat->fg->fg_battery_update(p_bat->fg, bat);
 
-		if (k == 100) {
+		if (k == 200) {
 			debug(" %d [V]", battery->voltage_uV);
 			puts("\n");
 			k = 0;
 		}
 
+		if (ctrlc()) {
+			printf("\nCharging disabled on request.\n");
+			goto exit;
+		}
 	}
-
+ exit:
 	bat->chrg->chrg_state(p_bat->chrg, CHARGER_DISABLE, 0);
 
 	return 0;
diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c
index 90df2c5..f16b9dc 100644
--- a/drivers/power/power_core.c
+++ b/drivers/power/power_core.c
@@ -205,7 +205,8 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		if (strcmp(argv[3], "charge") == 0) {
 			if (p->pbat) {
-				printf("PRINT BAT charge %s\n", p->name);
+				printf("BAT: %s charging (ctrl+c to break)\n",
+				       p->name);
 				if (p->low_power_mode)
 					p->low_power_mode();
 				if (p->pbat->battery_charge)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index e65125c..6836c7a 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/uart.h>
@@ -34,10 +35,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RX_FIFO_FULL_MASK	(1 << 8)
 #define TX_FIFO_FULL_MASK	(1 << 24)
 
+/* Information about a serial port */
+struct fdt_serial {
+	u32 base_addr;  /* address of registers in physical memory */
+	u8 port_id;     /* uart port number */
+	u8 enabled;     /* 1 if enabled, 0 if disabled */
+} config __attribute__ ((section(".data")));
+
 static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
 {
+#ifdef CONFIG_OF_CONTROL
+	return (struct s5p_uart *)(config.base_addr);
+#else
 	u32 offset = dev_index * sizeof(struct s5p_uart);
 	return (struct s5p_uart *)(samsung_get_base_uart() + offset);
+#endif
 }
 
 /*
@@ -73,6 +85,16 @@ void serial_setbrg_dev(const int dev_index)
 	u32 baudrate = gd->baudrate;
 	u32 val;
 
+#if defined(CONFIG_SILENT_CONSOLE) && \
+		defined(CONFIG_OF_CONTROL) && \
+		!defined(CONFIG_SPL_BUILD)
+	if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0))
+		gd->flags |= GD_FLG_SILENT;
+#endif
+
+	if (!config.enabled)
+		return;
+
 	val = uclk / baudrate;
 
 	writel(val / 16 - 1, &uart->ubrdiv);
@@ -133,6 +155,9 @@ int serial_getc_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
+	if (!config.enabled)
+		return 0;
+
 	/* wait for character to arrive */
 	while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
 					 RX_FIFO_FULL_MASK))) {
@@ -150,6 +175,9 @@ void serial_putc_dev(const char c, const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
+	if (!config.enabled)
+		return;
+
 	/* wait for room in the tx FIFO */
 	while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
 		if (serial_err_check(dev_index, 1))
@@ -170,6 +198,9 @@ int serial_tstc_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
+	if (!config.enabled)
+		return 0;
+
 	return (int)(readl(&uart->utrstat) & 0x1);
 }
 
@@ -212,8 +243,54 @@ DECLARE_S5P_SERIAL_FUNCTIONS(3);
 struct serial_device s5p_serial3_device =
 	INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
 
+#ifdef CONFIG_OF_CONTROL
+int fdtdec_decode_console(int *index, struct fdt_serial *uart)
+{
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	node = fdt_path_offset(blob, "console");
+	if (node < 0)
+		return node;
+
+	uart->base_addr = fdtdec_get_addr(blob, node, "reg");
+	if (uart->base_addr == FDT_ADDR_T_NONE)
+		return -FDT_ERR_NOTFOUND;
+
+	uart->port_id = fdtdec_get_int(blob, node, "id", -1);
+	uart->enabled = fdtdec_get_is_enabled(blob, node);
+
+	return 0;
+}
+#endif
+
 __weak struct serial_device *default_serial_console(void)
 {
+#ifdef CONFIG_OF_CONTROL
+	int index = 0;
+
+	if ((!config.base_addr) && (fdtdec_decode_console(&index, &config))) {
+		debug("Cannot decode default console node\n");
+		return NULL;
+	}
+
+	switch (config.port_id) {
+	case 0:
+		return &s5p_serial0_device;
+	case 1:
+		return &s5p_serial1_device;
+	case 2:
+		return &s5p_serial2_device;
+	case 3:
+		return &s5p_serial3_device;
+	default:
+		debug("Unknown config.port_id: %d", config.port_id);
+		break;
+	}
+
+	return NULL;
+#else
+	config.enabled = 1;
 #if defined(CONFIG_SERIAL0)
 	return &s5p_serial0_device;
 #elif defined(CONFIG_SERIAL1)
@@ -225,6 +302,7 @@ __weak struct serial_device *default_serial_console(void)
 #else
 #error "CONFIG_SERIAL? missing."
 #endif
+#endif
 }
 
 void s5p_serial_initialize(void)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 2ea3228..9c68d7d 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -128,8 +128,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
-	s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
-	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+	s32 reg_ctrl, reg_config;
+	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 
 	if (max_hz == 0) {
@@ -147,26 +147,20 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 	reg_ctrl |=  MXC_CSPICTRL_EN;
 	reg_write(&regs->ctrl, reg_ctrl);
 
-	/*
-	 * The following computation is taken directly from Freescale's code.
-	 */
 	if (clk_src > max_hz) {
-		pre_div = DIV_ROUND_UP(clk_src, max_hz);
-		if (pre_div > 16) {
-			post_div = pre_div / 16;
-			pre_div = 15;
-		}
-		if (post_div != 0) {
-			for (i = 0; i < 16; i++) {
-				if ((1 << i) >= post_div)
-					break;
-			}
-			if (i == 16) {
+		pre_div = (clk_src - 1) / max_hz;
+		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
+		post_div = fls(pre_div);
+		if (post_div > 4) {
+			post_div -= 4;
+			if (post_div >= 16) {
 				printf("Error: no divider for the freq: %d\n",
 					max_hz);
 				return -1;
 			}
-			post_div = i;
+			pre_div >>= post_div;
+		} else {
+			post_div = 0;
 		}
 	}
 
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 554145a..a9603bc 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2009-2012 NVIDIA Corporation
+ * Copyright (c) 2009-2013 NVIDIA Corporation
  * Copyright (c) 2013 Lucas Stach
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,8 @@
 #include <asm-generic/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/usb.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch/usb.h>
 #include <usb.h>
 #include <usb/ulpi.h>
 #include <libfdt.h>
@@ -35,6 +37,11 @@
 
 #include "ehci.h"
 
+#define USB1_ADDR_MASK	0xFFFF0000
+
+#define HOSTPC1_DEVLC	0x84
+#define HOSTPC1_PSPD(x)		(((x) >> 25) & 0x3)
+
 #ifdef CONFIG_USB_ULPI
 	#ifndef CONFIG_USB_ULPI_VIEWPORT
 	#error	"To use CONFIG_USB_ULPI on Tegra Boards you have to also \
@@ -87,6 +94,8 @@ struct fdt_usb {
 
 static struct fdt_usb port[USB_PORTS_MAX];	/* List of valid USB ports */
 static unsigned port_count;			/* Number of available ports */
+/* Port that needs to clear CSC after Port Reset */
+static u32 port_addr_clear_csc;
 
 /*
  * This table has USB timing parameters for each Oscillator frequency we
@@ -129,7 +138,7 @@ static unsigned port_count;			/* Number of available ports */
  *
  * 4. The 20 microsecond delay after bias cell operation.
  */
-static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
 	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
 	{ 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
 	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
@@ -137,6 +146,22 @@ static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
 	{ 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
 };
 
+static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   1,  0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   1,  0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   1,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+
+static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   2,  0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   2,  0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   2,  0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   2,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
+};
+
 /* UTMIP Idle Wait Delay */
 static const u8 utmip_idle_wait_delay = 17;
 
@@ -146,6 +171,33 @@ static const u8 utmip_elastic_limit = 16;
 /* UTMIP High Speed Sync Start Delay */
 static const u8 utmip_hs_sync_start_delay = 9;
 
+struct fdt_usb_controller {
+	int compat;
+	/* flag to determine whether controller supports hostpc register */
+	u32 has_hostpc:1;
+	const unsigned *pll_parameter;
+};
+
+static struct fdt_usb_controller fdt_usb_controllers[] = {
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA20_USB,
+		.has_hostpc	= 0,
+		.pll_parameter	= (const unsigned *)T20_usb_pll,
+	},
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA30_USB,
+		.has_hostpc	= 1,
+		.pll_parameter	= (const unsigned *)T30_usb_pll,
+	},
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA114_USB,
+		.has_hostpc	= 1,
+		.pll_parameter	= (const unsigned *)T114_usb_pll,
+	},
+};
+
+static struct fdt_usb_controller *controller;
+
 /*
  * A known hardware issue where Connect Status Change bit of PORTSC register
  * of USB1 controller will be set after Port Reset.
@@ -156,13 +208,52 @@ static const u8 utmip_hs_sync_start_delay = 9;
 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 {
 	mdelay(50);
-	if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE)
+	/* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
+	if (controller->has_hostpc)
+		*reg |= EHCI_PS_PE;
+
+	if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc)
 		return;
 	/* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
 	if (ehci_readl(status_reg) & EHCI_PS_CSC)
 		*reg |= EHCI_PS_CSC;
 }
 
+/*
+ * This ehci_set_usbmode overrides the weak function ehci_set_usbmode
+ * in "ehci-hcd.c".
+ */
+void ehci_set_usbmode(int index)
+{
+	struct fdt_usb *config;
+	struct usb_ctlr *usbctlr;
+	uint32_t tmp;
+
+	config = &port[index];
+	usbctlr = config->reg;
+
+	tmp = ehci_readl(&usbctlr->usb_mode);
+	tmp |= USBMODE_CM_HC;
+	ehci_writel(&usbctlr->usb_mode, tmp);
+}
+
+/*
+ * This ehci_get_port_speed overrides the weak function ehci_get_port_speed
+ * in "ehci-hcd.c".
+ */
+int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+{
+	uint32_t tmp;
+	uint32_t *reg_ptr;
+
+	if (controller->has_hostpc) {
+		reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC);
+		tmp = ehci_readl(reg_ptr);
+		return HOSTPC1_PSPD(tmp);
+	} else
+		return PORTSC_PSPD(reg);
+}
+
 /* Put the port into host mode */
 static void set_host_mode(struct fdt_usb *config)
 {
@@ -209,6 +300,16 @@ void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
 		setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
 }
 
+static const unsigned *get_pll_timing(void)
+{
+	const unsigned *timing;
+
+	timing = controller->pll_parameter +
+		clock_get_osc_freq() * PARAM_COUNT;
+
+	return timing;
+}
+
 /* set up the UTMI USB controller with the parameters provided */
 static int init_utmi_usb_controller(struct fdt_usb *config)
 {
@@ -216,6 +317,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
 	int loop_count;
 	const unsigned *timing;
 	struct usb_ctlr *usbctlr = config->reg;
+	struct clk_rst_ctlr *clkrst;
+	struct usb_ctlr *usb1ctlr;
 
 	clock_enable(config->periph_id);
 
@@ -232,35 +335,97 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
 	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
 	 * mux must be switched to actually use a_sess_vld threshold.
 	 */
-	if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+	if (config->dr_mode == DR_MODE_OTG &&
+	    fdt_gpio_isvalid(&config->vbus_gpio))
 		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
 			VBUS_SENSE_CTL_MASK,
 			VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
-	}
 
 	/*
 	 * PLL Delay CONFIGURATION settings. The following parameters control
 	 * the bring up of the plls.
 	 */
-	timing = usb_pll[clock_get_osc_freq()];
-
-	val = readl(&usbctlr->utmip_misc_cfg1);
-	clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
-		timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
-	clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
-		timing[PARAM_ACTIVE_DELAY_COUNT] <<
-			UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
-	writel(val, &usbctlr->utmip_misc_cfg1);
-
-	/* Set PLL enable delay count and crystal frequency count */
-	val = readl(&usbctlr->utmip_pll_cfg1);
-	clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
-		timing[PARAM_ENABLE_DELAY_COUNT] <<
-			UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
-	clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
-		timing[PARAM_XTAL_FREQ_COUNT] <<
-			UTMIP_XTAL_FREQ_COUNT_SHIFT);
-	writel(val, &usbctlr->utmip_pll_cfg1);
+	timing = get_pll_timing();
+
+	if (!controller->has_hostpc) {
+		val = readl(&usbctlr->utmip_misc_cfg1);
+		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+				timing[PARAM_STABLE_COUNT] <<
+				UTMIP_PLLU_STABLE_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+				timing[PARAM_ACTIVE_DELAY_COUNT] <<
+				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+		writel(val, &usbctlr->utmip_misc_cfg1);
+
+		/* Set PLL enable delay count and crystal frequency count */
+		val = readl(&usbctlr->utmip_pll_cfg1);
+		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+				timing[PARAM_ENABLE_DELAY_COUNT] <<
+				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+				timing[PARAM_XTAL_FREQ_COUNT] <<
+				UTMIP_XTAL_FREQ_COUNT_SHIFT);
+		writel(val, &usbctlr->utmip_pll_cfg1);
+	} else {
+		clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+		val = readl(&clkrst->crc_utmip_pll_cfg2);
+		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+				timing[PARAM_STABLE_COUNT] <<
+				UTMIP_PLLU_STABLE_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+				timing[PARAM_ACTIVE_DELAY_COUNT] <<
+				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+		writel(val, &clkrst->crc_utmip_pll_cfg2);
+
+		/* Set PLL enable delay count and crystal frequency count */
+		val = readl(&clkrst->crc_utmip_pll_cfg1);
+		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+				timing[PARAM_ENABLE_DELAY_COUNT] <<
+				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+				timing[PARAM_XTAL_FREQ_COUNT] <<
+				UTMIP_XTAL_FREQ_COUNT_SHIFT);
+		writel(val, &clkrst->crc_utmip_pll_cfg1);
+
+		/* Disable Power Down state for PLL */
+		clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
+			     PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
+			     PLL_ACTIVE_POWERDOWN);
+
+		/* Recommended PHY settings for EYE diagram */
+		val = readl(&usbctlr->utmip_xcvr_cfg0);
+		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
+				0x4 << UTMIP_XCVR_SETUP_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
+				0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
+				0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
+		writel(val, &usbctlr->utmip_xcvr_cfg0);
+		clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
+				UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
+				0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
+
+		/* Some registers can be controlled from USB1 only. */
+		if (config->periph_id != PERIPH_ID_USBD) {
+			clock_enable(PERIPH_ID_USBD);
+			/* Disable Reset if in Reset state */
+			reset_set_enable(PERIPH_ID_USBD, 0);
+		}
+		usb1ctlr = (struct usb_ctlr *)
+			((u32)config->reg & USB1_ADDR_MASK);
+		val = readl(&usb1ctlr->utmip_bias_cfg0);
+		setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
+		clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
+				0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
+		clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
+				0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
+		writel(val, &usb1ctlr->utmip_bias_cfg0);
+
+		/* Miscellaneous setting mentioned in Programming Guide */
+		clrbits_le32(&usbctlr->utmip_misc_cfg0,
+			     UTMIP_SUSPEND_EXIT_ON_EDGE);
+	}
 
 	/* Setting the tracking length time */
 	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
@@ -308,6 +473,14 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
 	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
 	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
 
+	if (controller->has_hostpc) {
+		if (config->periph_id == PERIPH_ID_USBD)
+			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+				     UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
+		if (config->periph_id == PERIPH_ID_USB3)
+			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+				     UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
+	}
 	/* Finished the per-controller init. */
 
 	/* De-assert UTMIP_RESET to bring out of reset. */
@@ -336,6 +509,18 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
 	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
 		UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
 
+	if (controller->has_hostpc) {
+		/*
+		 * BIAS Pad Power Down is common among all 3 USB
+		 * controllers and can be controlled from USB1 only.
+		 */
+		usb1ctlr = (struct usb_ctlr *)
+			((u32)config->reg & USB1_ADDR_MASK);
+		clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
+		udelay(25);
+		clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
+			     UTMIP_FORCE_PDTRK_POWERDOWN);
+	}
 	return 0;
 }
 
@@ -438,7 +623,7 @@ static void config_clock(const u32 timing[])
 		timing[PARAM_CPCON], timing[PARAM_LFCON]);
 }
 
-int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
+static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
 {
 	const char *phy, *mode;
 
@@ -466,6 +651,8 @@ int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
 	config->enabled = fdtdec_get_is_enabled(blob, node);
 	config->has_legacy_mode = fdtdec_get_bool(blob, node,
 						  "nvidia,has-legacy-mode");
+	if (config->has_legacy_mode)
+		port_addr_clear_csc = (u32) config->reg;
 	config->periph_id = clock_decode_periph_id(blob, node);
 	if (config->periph_id == PERIPH_ID_NONE) {
 		debug("%s: Missing/invalid peripheral ID\n", __func__);
@@ -483,20 +670,22 @@ int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
 	return 0;
 }
 
-int board_usb_init(const void *blob)
+/*
+ * process_usb_nodes() - Process a list of USB nodes, adding them to our list
+ *			of USB ports.
+ * @blob:	fdt blob
+ * @node_list:	list of nodes to process (any <=0 are ignored)
+ * @count:	number of nodes to process
+ *
+ * Return:	0 - ok, -1 - error
+ */
+static int process_usb_nodes(const void *blob, int node_list[], int count)
 {
 	struct fdt_usb config;
-	enum clock_osc_freq freq;
-	int node_list[USB_PORTS_MAX];
-	int node, count, i;
-
-	/* Set up the USB clocks correctly based on our oscillator frequency */
-	freq = clock_get_osc_freq();
-	config_clock(usb_pll[freq]);
+	int node, i;
+	int clk_done = 0;
 
-	/* count may return <0 on error */
-	count = fdtdec_find_aliases_for_id(blob, "usb",
-			COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+	port_count = 0;
 	for (i = 0; i < count; i++) {
 		if (port_count == USB_PORTS_MAX) {
 			printf("tegrausb: Cannot register more than %d ports\n",
@@ -513,6 +702,10 @@ int board_usb_init(const void *blob)
 			      fdt_get_name(blob, node, NULL));
 			return -1;
 		}
+		if (!clk_done) {
+			config_clock(get_pll_timing());
+			clk_done = 1;
+		}
 		config.initialized = 0;
 
 		/* add new USB port to the list of available ports */
@@ -522,6 +715,31 @@ int board_usb_init(const void *blob)
 	return 0;
 }
 
+int board_usb_init(const void *blob)
+{
+	int node_list[USB_PORTS_MAX];
+	int count, err = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
+		controller = &fdt_usb_controllers[i];
+
+		count = fdtdec_find_aliases_for_id(blob, "usb",
+			controller->compat, node_list, USB_PORTS_MAX);
+		if (count) {
+			err = process_usb_nodes(blob, node_list, count);
+			if (err)
+				printf("%s: Error processing USB node!\n",
+				       __func__);
+			return err;
+		}
+	}
+	if (i == ARRAY_SIZE(fdt_usb_controllers))
+		controller = NULL;
+
+	return err;
+}
+
 /**
  * Start up the given port number (ports are numbered from 0 on each board).
  * This returns values for the appropriate hccr and hcor addresses to use for
@@ -564,6 +782,20 @@ success:
 	usbctlr = config->reg;
 	*hccr = (struct ehci_hccr *)&usbctlr->cap_length;
 	*hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
+
+	if (controller->has_hostpc) {
+		/* Set to Host mode after Controller Reset was done */
+		clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
+				USBMODE_CM_HC);
+		/* Select UTMI parallel interface after setting host mode */
+		if (config->utmi) {
+			clrsetbits_le32((char *)&usbctlr->usb_cmd +
+					HOSTPC1_DEVLC, PTS_MASK,
+					PTS_UTMI << PTS_SHIFT);
+			clrbits_le32((char *)&usbctlr->usb_cmd +
+				     HOSTPC1_DEVLC, STS);
+		}
+	}
 	return 0;
 }
 
diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 3c1ea1a..4db7fa4 100644
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -22,18 +22,19 @@
 #include <asm/io.h>
 #include <usb/ulpi.h>
 
-#define OMAP_ULPI_WR_OPSEL	(3 << 21)
-#define OMAP_ULPI_ACCESS	(1 << 31)
+#define OMAP_ULPI_WR_OPSEL	(2 << 22)
+#define OMAP_ULPI_RD_OPSEL	(3 << 22)
+#define OMAP_ULPI_START		(1 << 31)
 
 /*
- * Wait for the ULPI Access to complete
+ * Wait for having ulpi in done state
  */
 static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
 {
 	int timeout = CONFIG_USB_ULPI_TIMEOUT;
 
 	while (--timeout) {
-		if ((readl(ulpi_vp->viewport_addr) & mask))
+		if (!(readl(ulpi_vp->viewport_addr) & mask))
 			return 0;
 
 		udelay(1);
@@ -43,40 +44,15 @@ static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
 }
 
 /*
- * Wake the ULPI PHY up for communication
- *
- * returns 0 on success.
- */
-static int ulpi_wakeup(struct ulpi_viewport *ulpi_vp)
-{
-	int err;
-
-	if (readl(ulpi_vp->viewport_addr) & OMAP_ULPI_ACCESS)
-		return 0; /* already awake */
-
-	writel(OMAP_ULPI_ACCESS, ulpi_vp->viewport_addr);
-
-	err = ulpi_wait(ulpi_vp, OMAP_ULPI_ACCESS);
-	if (err)
-		debug("ULPI wakeup timed out\n");
-
-	return err;
-}
-
-/*
  * Issue a ULPI read/write request
  */
 static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)
 {
 	int err;
 
-	err = ulpi_wakeup(ulpi_vp);
-	if (err)
-		return err;
-
 	writel(value, ulpi_vp->viewport_addr);
 
-	err = ulpi_wait(ulpi_vp, OMAP_ULPI_ACCESS);
+	err = ulpi_wait(ulpi_vp, OMAP_ULPI_START);
 	if (err)
 		debug("ULPI request timed out\n");
 
@@ -85,7 +61,7 @@ static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)
 
 int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 {
-	u32 val = ((ulpi_vp->port_num & 0xf) << 24) |
+	u32 val = OMAP_ULPI_START | (((ulpi_vp->port_num + 1) & 0xf) << 24) |
 			OMAP_ULPI_WR_OPSEL | ((u32)reg << 16) | (value & 0xff);
 
 	return ulpi_request(ulpi_vp, val);
@@ -94,8 +70,8 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg)
 {
 	int err;
-	u32 val = ((ulpi_vp->port_num & 0xf) << 24) |
-			 OMAP_ULPI_WR_OPSEL | ((u32)reg << 16);
+	u32 val = OMAP_ULPI_START | (((ulpi_vp->port_num + 1) & 0xf) << 24) |
+			 OMAP_ULPI_RD_OPSEL | ((u32)reg << 16);
 
 	err = ulpi_request(ulpi_vp, val);
 	if (err)
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index 3359949..7243ea3 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -280,8 +280,9 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
 								node, "reg");
 	if (fimd_ctrl == NULL)
 		debug("Can't get the FIMD base address\n");
-#endif
+#else
 	fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
+#endif
 
 	offset = exynos_fimd_get_base_offset();
 
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index b189419..b0f7ef8 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -137,7 +137,7 @@ void *video_hw_init(void)
 	/* Suck display configuration from "videomode" variable */
 	penv = getenv("videomode");
 	if (!penv) {
-		printf("MXSFB: 'videomode' variable not set!");
+		puts("MXSFB: 'videomode' variable not set!\n");
 		return NULL;
 	}
 
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index d51f5f8..628d5d3 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -71,6 +71,20 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index f3916de..142d20b 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -70,6 +70,20 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 6d7a187..b6e0161 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -75,6 +75,20 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index e2a096b..582c584 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -86,9 +86,9 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL3			/* use SERIAL 3 */
 #define CONFIG_BAUDRATE			115200
 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+#define CONFIG_SILENT_CONSOLE
 
 /* Enable keyboard */
 #define CONFIG_CROS_EC		/* CROS_EC protocol */
@@ -120,6 +120,7 @@
 
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
 
 /* PWM */
 #define CONFIG_PWM
@@ -153,6 +154,7 @@
 #define CONFIG_USB_STORAGE
 
 /* USB boot mode */
+#define CONFIG_USB_BOOTING
 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
@@ -168,8 +170,10 @@
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
 /* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT	"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_TEXT_BASE	0x02023400
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
 
@@ -245,7 +249,7 @@
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
 
-#define OM_STAT				(0x1f << 1)
+#define CONFIG_SPI_BOOTING
 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
 #define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
 
@@ -257,7 +261,7 @@
 
 #define CONFIG_IRAM_STACK	0x02050000
 
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
 
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 0c73f86..27aaf16 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -49,6 +49,7 @@
 #define CONFIG_MACH_TYPE		MACH_TYPE_HARMONY
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT		/* Make sure LCD init is complete */
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -83,6 +84,14 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 5b3fa43..10ccc3b 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -70,6 +70,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 13d1839..4383375d 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -162,8 +162,8 @@
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index b0a965f..fa160e4 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -118,8 +118,8 @@
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"update_sd_firmware_filename=u-boot.imx\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index a4b610f..cc31e9b 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -124,8 +124,8 @@
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
 	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 76f7812..a396acf 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -30,7 +30,7 @@
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
-#include "mx6qsabre_common.h"
+#include "mx6sabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #if defined(CONFIG_ENV_IS_IN_MMC)
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index b814418..c7db81d 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -170,8 +170,8 @@
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6sabre_common.h
index bfaa420..53cc559 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -18,7 +18,6 @@
 #define __MX6QSABRE_COMMON_CONFIG_H
 
 #define CONFIG_MX6
-#define CONFIG_MX6Q
 
 #include "mx6_common.h"
 
diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6sabresd.h
index 44f07cb..76675f4 100644
--- a/include/configs/mx6qsabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -24,7 +24,7 @@
 #define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabresd.dtb"
 #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
 
-#include "mx6qsabre_common.h"
+#include "mx6sabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 #if defined(CONFIG_ENV_IS_IN_MMC)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 19dcdd6..55e3ad9 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -73,8 +73,8 @@
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index aea91bc..74df66c 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -276,8 +276,6 @@
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
-#define CONFIG_SYS_DCACHE_OFF
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 #define CONFIG_CMD_CACHE
 #endif
@@ -287,4 +285,8 @@
 #define CONFIG_CMD_TIME
 #define CONFIG_SYS_ALT_MEMTEST
 
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_CMD_FS_GENERIC
+
 #endif	       /* __CONFIG_H */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index e179911..5013aee 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -36,6 +36,7 @@
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /* Keep L2 Cache Disabled */
 #define CONFIG_L2_OFF			1
@@ -67,6 +68,8 @@
 #define CONFIG_BAUDRATE			115200
 #define EXYNOS4_DEFAULT_UART_OFFSET	0x020000
 
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
@@ -147,7 +150,10 @@
 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
 #define CONFIG_DOS_PARTITION		1
 
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x02040000
 
 /* U-boot copy size from boot Media to DRAM.*/
 #define COPY_BL2_SIZE		0x80000
@@ -156,4 +162,5 @@
 
 /* Enable devicetree support */
 #define CONFIG_OF_LIBFDT
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h
new file mode 100644
index 0000000..2ab6fd2
--- /dev/null
+++ b/include/configs/palmtreo680.h
@@ -0,0 +1,286 @@
+/*
+ * Palm Treo 680 configuration file
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_CPU_PXA27X
+#define CONFIG_PALMTREO680
+#define CONFIG_MACH_TYPE                MACH_TYPE_TREO680
+
+#define CONFIG_SYS_MALLOC_LEN           (4096*1024)
+
+#define CONFIG_LZMA
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART                   1
+#define CONFIG_BAUDRATE                 9600
+#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX               3
+
+/* we have nand (although technically nand *is* flash...) */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_LCD
+/* #define CONFIG_KEYBOARD */  /* TODO */
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+#undef  CONFIG_CMD_FPGA
+#undef  CONFIG_CMD_LOADS
+#undef  CONFIG_CMD_NET
+#undef  CONFIG_CMD_NFS
+#undef  CONFIG_CMD_IMLS
+#undef  CONFIG_CMD_FLASH
+#undef  CONFIG_CMD_SETGETDCR
+#undef  CONFIG_CMD_SOURCE
+#undef  CONFIG_CMD_XIMG
+
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_PXA_LCD
+#define CONFIG_ACX544AKN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_FB_ADDR 0x5c000000    /* internal SRAM */
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN         /* requires "splashimage" env var */
+#define CONFIG_SPLASH_SCREEN_ALIGN   /* requires "splashpos" env var */
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
+
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER          1
+#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT               "$ "
+#else
+#define CONFIG_SYS_PROMPT               "=> "
+#endif
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_PBSIZE               \
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV       1
+
+/*
+ * Clock Configuration
+ */
+#undef  CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ                   1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
+#define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE            0xa0000000
+#define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL  0x0E000000
+#define CONFIG_SYS_GAFR0_U_VAL  0xA500001A
+#define CONFIG_SYS_GAFR1_L_VAL  0x60000002
+#define CONFIG_SYS_GAFR1_U_VAL  0xAAA07959
+#define CONFIG_SYS_GAFR2_L_VAL  0x02AAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL  0x41440F08
+#define CONFIG_SYS_GAFR3_L_VAL  0x56AA95FF
+#define CONFIG_SYS_GAFR3_U_VAL  0x00001401
+#define CONFIG_SYS_GPCR0_VAL    0x1FF80400
+#define CONFIG_SYS_GPCR1_VAL    0x03003FC1
+#define CONFIG_SYS_GPCR2_VAL    0x01C1E000
+#define CONFIG_SYS_GPCR3_VAL    0x01C1E000
+#define CONFIG_SYS_GPDR0_VAL    0xCFF90400
+#define CONFIG_SYS_GPDR1_VAL    0xFB22BFC1
+#define CONFIG_SYS_GPDR2_VAL    0x93CDFFDF
+#define CONFIG_SYS_GPDR3_VAL    0x0069FF81
+#define CONFIG_SYS_GPSR0_VAL    0x02000018
+#define CONFIG_SYS_GPSR1_VAL    0x00000000
+#define CONFIG_SYS_GPSR2_VAL    0x000C0000
+#define CONFIG_SYS_GPSR3_VAL    0x00080000
+
+#define CONFIG_SYS_PSSR_VAL     0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN         0x01ffffff
+#define CONFIG_SYS_CCCR         0x02000210
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL     0x7ff844c8
+#define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
+#define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
+#define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
+#define CONFIG_SYS_MDREFR_VAL   0x201fa031
+#define CONFIG_SYS_MDMRS_VAL    0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL  0x00000000
+#define CONFIG_SYS_SXCNFG_VAL   0x40044004
+#define CONFIG_SYS_MECR_VAL     0x00000003
+#define CONFIG_SYS_MCMEM0_VAL   0x0001c391
+#define CONFIG_SYS_MCMEM1_VAL   0x0001c391
+#define CONFIG_SYS_MCATT0_VAL   0x0001c391
+#define CONFIG_SYS_MCATT1_VAL   0x0001c391
+#define CONFIG_SYS_MCIO0_VAL    0x00014611
+#define CONFIG_SYS_MCIO1_VAL    0x0001c391
+
+/*
+ * USB
+ */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_USB_DEV_PULLUP_GPIO 114
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE    0xa1700000 /* IPL loads SPL here */
+#define CONFIG_SPL_STACK        0x5c040000 /* end of internal SRAM */
+#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
+#define CONFIG_SPL_NAND_DOCG4   /* use lean docg4 nand spl driver */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT  /* spl uses memcpy */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_DOCG4
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
+#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
+#define CONFIG_BITREVERSE       /* needed by docg4 driver */
+#define CONFIG_BCH              /* needed by docg4 driver */
+
+/*
+ * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image.  It
+ * will be rounded up to the next 64k boundary (the spl flash block size), so it
+ * does not have to be exact, but you must ensure that it is not less than the
+ * actual image size, or it may fail to boot (bricked phone)!
+ * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
+*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
+
+/*
+ * This is the byte offset into the flash at which the concatenated spl + u-boot
+ * image is placed.  It must be at the start of a block (256k boundary).  Blocks
+ * 0 - 5 are write-protected, so we start at block 6.
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000  /* block 6 */
+
+/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
+#define CONFIG_SYS_NAND_U_BOOT_DST  0xa0000000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+/* passed to linker by Makefile as arg to -Ttext option */
+#define CONFIG_SYS_TEXT_BASE 0xa0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x5c040000 /* end of internal SRAM */
+
+/*
+ * environment
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_BUILD_ENVCRC
+#define CONFIG_ENV_SIZE 0x200
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+	"stdin=usbtty\0"           \
+	"stdout=usbtty\0"          \
+	"stderr=usbtty"
+#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
+ip=192.168.11.102:::255.255.255.0:treo:usb0"
+#define CONFIG_BOOTDELAY   3
+
+#if 0 /* example: try 2nd mmc partition, then nand */
+#define CONFIG_BOOTCOMMAND                                              \
+	"mmc rescan; "                                                  \
+	"if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then "       \
+	    "bootm 0xa1000000; "					\
+	"elif nand read 0xa1000000 0x280000 0x240000; then "            \
+	    "bootm 0xa1000000; "					\
+	"fi; "
+#endif
+
+/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
+#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 5e43066..0f04597 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -36,6 +36,7 @@
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /* Mach Type */
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310
@@ -57,6 +58,7 @@
 /* Handling Sleep Mode*/
 #define S5P_CHECK_SLEEP			0x00000BAD
 #define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
@@ -93,6 +95,7 @@
 
 /* MMC SPL */
 #define CONFIG_SPL
+#define CONFIG_SKIP_LOWLEVEL_INIT
 #define COPY_BL2_FNPTR_ADDR	0x00002488
 
 #define CONFIG_SPL_TEXT_BASE	0x02021410
@@ -146,7 +149,10 @@
 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
 #define CONFIG_DOS_PARTITION		1
 
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x02040000
 
 /* U-boot copy size from boot Media to DRAM.*/
 #define	COPY_BL2_SIZE		0x80000
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 721b29c..44e98e5 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -77,4 +77,7 @@
 /* Total I2C ports on Tegra114 */
 #define TEGRA_I2C_NUM_CONTROLLERS	5
 
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+
 #endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index ed36e11..7ea36be 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -90,4 +90,7 @@
 /* Total I2C ports on Tegra30 */
 #define TEGRA_I2C_NUM_CONTROLLERS	5
 
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+
 #endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index c70838b..103295e 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -66,7 +66,7 @@
 #define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (16 << 20))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL2			/* use SERIAL 2 */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 41a7176..05e682c 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -43,6 +43,7 @@
 #define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT		/* Make sure LCD init is complete */
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -73,6 +74,14 @@
 /* USB keyboard */
 #define CONFIG_USB_KEYBOARD
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 77fe893..5012fc8 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -83,13 +83,101 @@
 
 #define CONFIG_BOOTDELAY		3
 
+#define CONFIG_LOADADDR			0x82000000
 #define CONFIG_SYS_TEXT_BASE		0x3f008000
 
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttyLP1\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=vf610-twr.dtb\0" \
+	"fdt_addr=0x81000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_PROMPT		"Vybrid U-Boot > "
+#define CONFIG_SYS_PROMPT		"=> "
 #undef CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
@@ -101,8 +189,7 @@
 #define CONFIG_SYS_MEMTEST_START	0x80010000
 #define CONFIG_SYS_MEMTEST_END		0x87C00000
 
-#define CONFIG_SYS_LOAD_ADDR		0x80010000
-
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 
 /*
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 5593f1c..ee6bf21 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -103,6 +103,8 @@
 
 #if defined(CONFIG_MX6DL)
 #define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"
+#elif defined(CONFIG_MX6Q)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6q-wandboard.dtb"
 #elif defined(CONFIG_MX6S)
 #define CONFIG_DEFAULT_FDT_FILE		"imx6s-wandboard.dtb"
 #endif
@@ -118,8 +120,8 @@
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"update_sd_firmware_filename=u-boot.imx\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
diff --git a/include/fdtdec.h b/include/fdtdec.h
index d93e102..bdefda4 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -64,6 +64,8 @@ struct fdt_memory {
 enum fdt_compat_id {
 	COMPAT_UNKNOWN,
 	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra20 USB port */
+	COMPAT_NVIDIA_TEGRA30_USB,	/* Tegra30 USB port */
+	COMPAT_NVIDIA_TEGRA114_USB,	/* Tegra114 USB port */
 	COMPAT_NVIDIA_TEGRA114_I2C,	/* Tegra114 I2C w/single clock source */
 	COMPAT_NVIDIA_TEGRA20_I2C,	/* Tegra20 i2c */
 	COMPAT_NVIDIA_TEGRA20_DVC,	/* Tegra20 dvc (really just i2c) */
@@ -92,6 +94,7 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS_FIMD,	/* Exynos Display controller */
 	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
 	COMPAT_SAMSUNG_EXYNOS5_DWMMC,	/* Exynos5 DWMMC controller */
+	COMPAT_SAMSUNG_EXYNOS_SERIAL,	/* Exynos UART */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
 	COMPAT_MAXIM_98095_CODEC,	/* MAX98095 Codec */
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index fdc7ca9..1c374a9 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -157,6 +157,8 @@ enum {
 
 /* Buck1 1 volt value */
 #define MAX77686_BUCK1OUT_1V	0x5
+/* Buck1 1.05 volt value */
+#define MAX77686_BUCK1OUT_1_05V    0x6
 #define MAX77686_BUCK1CTRL_EN	(3 << 0)
 /* Buck2 1.3 volt value */
 #define MAX77686_BUCK2DVS1_1_3V	0x38
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b314268..1b3c810 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -37,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(UNKNOWN, "<none>"),
 	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
+	COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"),
+	COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"),
 	COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"),
 	COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
 	COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
@@ -65,6 +67,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
 	COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
 	COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+	COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
 	COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
 	COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c
new file mode 100644
index 0000000..3d8296f
--- /dev/null
+++ b/tools/palmtreo680/flash_u-boot.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ *
+ * This is a userspace Linux utility that, when run on the Treo 680, will
+ * program u-boot to flash.  The docg4 driver *must* be loaded with the
+ * reliable_mode and ignore_badblocks parameters enabled:
+ *
+ *        modprobe docg4 ignore_badblocks=1 reliable_mode=1
+ *
+ * This utility writes the concatenated spl + u-boot image to the start of the
+ * mtd device in the format expected by the IPL/SPL.  The image file and mtd
+ * device node are passed to the utility as arguments.  The blocks must have
+ * been erased beforehand.
+ *
+ * When you compile this, note that it links to libmtd from mtd-utils, so ensure
+ * that your include and lib paths include this.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <errno.h>
+#include <mtd/mtd-user.h>
+#include "libmtd.h"
+
+#define RELIABLE_BLOCKSIZE  0x10000 /* block capacity in reliable mode */
+#define STANDARD_BLOCKSIZE  0x40000 /* block capacity in normal mode */
+#define PAGESIZE 512
+#define PAGES_PER_BLOCK 512
+#define OOBSIZE 7		/* available to user (16 total) */
+
+uint8_t ff_oob[OOBSIZE] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+/* this is the magic number the IPL looks for (ASCII "BIPO") */
+uint8_t page0_oob[OOBSIZE] = {'B', 'I', 'P', 'O', 0xff, 0xff, 0xff};
+
+int main(int argc, char * const argv[])
+{
+	int devfd, datafd, num_blocks, block;
+	off_t file_size;
+	libmtd_t mtd_desc;
+	struct mtd_dev_info devinfo;
+	uint8_t *blockbuf;
+	char response[8];
+
+	if (argc != 3) {
+		printf("usage: %s <image file> <mtd dev node>\n", argv[0]);
+		return -EINVAL;
+	}
+
+	mtd_desc = libmtd_open();
+	if (mtd_desc == NULL) {
+		int errsv = errno;
+		fprintf(stderr, "can't initialize libmtd\n");
+		return -errsv;
+	}
+
+	/* open the spl image file and mtd device */
+	datafd = open(argv[1], O_RDONLY);
+	if (datafd == -1) {
+		int errsv = errno;
+		perror(argv[1]);
+		return -errsv;
+	}
+	devfd = open(argv[2], O_WRONLY);
+	if (devfd == -1) {
+		int errsv = errno;
+		perror(argv[2]);
+		return -errsv;
+	}
+	if (mtd_get_dev_info(mtd_desc, argv[2], &devinfo) < 0) {
+		int errsv = errno;
+		perror(argv[2]);
+		return -errsv;
+	}
+
+	/* determine the number of blocks needed by the image */
+	file_size = lseek(datafd, 0, SEEK_END);
+	if (file_size == (off_t)-1) {
+		int errsv = errno;
+		perror("lseek");
+		return -errsv;
+	}
+	num_blocks = (file_size + RELIABLE_BLOCKSIZE - 1) / RELIABLE_BLOCKSIZE;
+	file_size = lseek(datafd, 0, SEEK_SET);
+	if (file_size == (off_t)-1) {
+		int errsv = errno;
+		perror("lseek");
+		return -errsv;
+	}
+	printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt);
+	printf("U-boot will occupy %d blocks\n", num_blocks);
+	if (num_blocks > devinfo.eb_cnt) {
+		fprintf(stderr, "Insufficient blocks on partition\n");
+		return -EINVAL;
+	}
+
+	printf("IMPORTANT: These blocks must be in an erased state!\n");
+	printf("Do you want to proceed?\n");
+	scanf("%s", response);
+	if ((response[0] != 'y') && (response[0] != 'Y')) {
+		printf("Exiting\n");
+		close(devfd);
+		close(datafd);
+		return 0;
+	}
+
+	blockbuf = calloc(RELIABLE_BLOCKSIZE, 1);
+	if (blockbuf == NULL) {
+		int errsv = errno;
+		perror("calloc");
+		return -errsv;
+	}
+
+	for (block = 0; block < num_blocks; block++) {
+		int ofs, page;
+		uint8_t *pagebuf = blockbuf, *buf = blockbuf;
+		uint8_t *oobbuf = page0_oob; /* magic num in oob of 1st page */
+		size_t len = RELIABLE_BLOCKSIZE;
+		int ret;
+
+		/* read data for one block from file */
+		while (len) {
+			ssize_t read_ret = read(datafd, buf, len);
+			if (read_ret == -1) {
+				int errsv = errno;
+				if (errno == EINTR)
+					continue;
+				perror("read");
+				return -errsv;
+			} else if (read_ret == 0) {
+				break; /* EOF */
+			}
+			len -= read_ret;
+			buf += read_ret;
+		}
+
+		printf("Block %d: writing\r", block + 1);
+		fflush(stdout);
+
+		for (page = 0, ofs = 0;
+		     page < PAGES_PER_BLOCK;
+		     page++, ofs += PAGESIZE) {
+			if (page & 0x04)  /* Odd-numbered 2k page */
+				continue; /* skipped in reliable mode */
+
+			ret = mtd_write(mtd_desc, &devinfo, devfd, block, ofs,
+					pagebuf, PAGESIZE, oobbuf, OOBSIZE,
+					MTD_OPS_PLACE_OOB);
+			if (ret) {
+				fprintf(stderr,
+					"\nmtd_write returned %d on block %d, ofs %x\n",
+					ret, block + 1, ofs);
+				return -EIO;
+			}
+			oobbuf = ff_oob;  /* oob for subsequent pages */
+
+			if (page & 0x01)  /* odd-numbered subpage */
+				pagebuf += PAGESIZE;
+		}
+	}
+
+	printf("\nDone\n");
+
+	close(devfd);
+	close(datafd);
+	free(blockbuf);
+	return 0;
+}
author	Tom Rini <trini@ti.com>	2013-07-12 10:36:48 -0400
committer	Tom Rini <trini@ti.com>	2013-07-12 10:36:48 -0400
commit	fbbbc86e8ebac4f42f4ca39ceba80cea27c983bc (patch)
tree	9c91526cefd027d9bd964572d4f92bd2d1376c5d
parent	d72da1582895ca226b995758426ec3769b54a9b8 (diff)
parent	efc284e32503b240dbd35c6e8b8d098d702b4be7 (diff)
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