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authorHans de Goede <hdegoede@redhat.com>2015-02-19 14:46:44 +0100
committerHans de Goede <hdegoede@redhat.com>2015-02-21 16:53:37 +0100
commitf388a26d1132dae7ffe123cd7bd9adf78d4f7b57 (patch)
tree127de1c00345fab1969b5291b6e19fbaf6f98e89
parent52defe8f65700ad625c3ca63f723564210b2dc82 (diff)
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sunxi: Fix sun5i mbus speed when booting old kernels
Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, halving the mbus frequency, so set it to 300 MHz ourselves and base the mbus divider on that. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index d297ed0..c28ee05 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -144,7 +144,16 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0xa1005000
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT 0xa1009900
+#else
#define PLL6_CFG_DEFAULT 0xa1009911
+#endif
/* nand clock */
#define NAND_CLK_SRC_OSC24 0