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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-11-22 10:19:35 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-11-22 10:19:35 +0100
commitd44a5f51288aec60c6bdb4ac939d75c24e5bf9c2 (patch)
treeecdb7323aea876f50e96995b05b6e320021aaaca
parent56eb3da43fab5990a4b7bc118b76c7cae2ceb140 (diff)
parentb5f05b063413245e3d29186739fb5db98d137dfd (diff)
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Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
-rw-r--r--arch/arm/cpu/armv7/zynq/cpu.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 2bb3843..9af340e 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -16,23 +16,24 @@ void lowlevel_init(void)
int arch_cpu_init(void)
{
zynq_slcr_unlock();
- /* remap DDR to zero, FILTERSTART */
- writel(0, &scu_base->filter_start);
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, &scu_base->filter_start);
+
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel(0x1F, &slcr_base->ocm_cfg);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel(0x0, &slcr_base->fpga_rst_ctrl);
- /* TZ_DDR_RAM, Set DDR trust zone non-secure */
- writel(0xFFFFFFFF, &slcr_base->trust_zone);
/* Set urgent bits with register */
writel(0x0, &slcr_base->ddr_urgent_sel);
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
+#endif
zynq_slcr_lock();