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authorWolfgang Denk <wd@denx.de>2008-08-26 23:14:58 +0200
committerWolfgang Denk <wd@denx.de>2008-08-26 23:14:58 +0200
commitc5d11e79a260415448c152ed557c9bfb93759067 (patch)
tree1fa825b4aaa09eae4b69f4a378948f0d5c871524
parentb4e07520bbb5467ad72eb92a5c9177d2797b9e30 (diff)
parent1a9eeb78b825bfade31d7606a2fe3b9eca9e35be (diff)
downloadu-boot-imx-c5d11e79a260415448c152ed557c9bfb93759067.zip
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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
-rw-r--r--Makefile4
-rw-r--r--board/freescale/mpc8315erdb/mpc8315erdb.c39
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c9
-rw-r--r--board/freescale/mpc8349emds/pci.c414
-rw-r--r--board/matrix_vision/mvblm7/Makefile (renamed from board/mvblm7/Makefile)0
-rw-r--r--board/matrix_vision/mvblm7/config.mk (renamed from board/mvblm7/config.mk)0
-rw-r--r--board/matrix_vision/mvblm7/fpga.c (renamed from board/mvblm7/fpga.c)0
-rw-r--r--board/matrix_vision/mvblm7/fpga.h (renamed from board/mvblm7/fpga.h)0
-rw-r--r--board/matrix_vision/mvblm7/mvblm7.c (renamed from board/mvblm7/mvblm7.c)0
-rw-r--r--board/matrix_vision/mvblm7/mvblm7.h (renamed from board/mvblm7/mvblm7.h)0
-rw-r--r--board/matrix_vision/mvblm7/mvblm7_autoscript (renamed from board/mvblm7/mvblm7_autoscript)10
-rw-r--r--board/matrix_vision/mvblm7/pci.c (renamed from board/mvblm7/pci.c)0
-rw-r--r--common/fdt_support.c30
-rw-r--r--cpu/mpc83xx/pci.c26
-rw-r--r--include/asm-ppc/immap_83xx.h4
-rw-r--r--include/configs/MPC8315ERDB.h2
-rw-r--r--include/configs/MPC8349EMDS.h26
-rw-r--r--include/configs/MVBLM7.h56
-rw-r--r--include/mpc83xx.h7
19 files changed, 273 insertions, 354 deletions
diff --git a/Makefile b/Makefile
index 8c90dab..66d9104 100644
--- a/Makefile
+++ b/Makefile
@@ -2065,7 +2065,7 @@ MPC8313ERDB_NAND_66_config: unconfig
fi ; \
if [ "$(findstring _NAND_,$@)" ] ; then \
$(XECHO) -n "...NAND..." ; \
- echo "TEXT_BASE = 0x00100000" > $(obj)/board/freescale/mpc8313erdb/config.tmp ; \
+ echo "TEXT_BASE = 0x00100000" > $(obj)board/freescale/mpc8313erdb/config.tmp ; \
echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
@@ -2180,7 +2180,7 @@ MPC837XERDB_config: unconfig
@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
MVBLM7_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index 7af36dd..3eecee2 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -25,9 +25,8 @@
#include <common.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#endif
+#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
@@ -122,11 +121,47 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_tsec1_fixup(void *fdt, bd_t *bd)
+{
+ char *mpc8315erdb = getenv("mpc8315erdb");
+ const char disabled[] = "disabled";
+ const char *path;
+ int ret;
+
+ if (!mpc8315erdb)
+ return;
+
+ if (!strcmp(mpc8315erdb, "tsec1")) {
+ return;
+ } else if (strcmp(mpc8315erdb, "ulpi")) {
+ printf("WARNING: wrong `mpc8315erdb' environment "
+ "variable specified: `%s'. Should be `ulpi' "
+ "or `tsec1'.\n", mpc8315erdb);
+ return;
+ }
+
+ ret = fdt_path_offset(fdt, "/aliases");
+ if (ret < 0) {
+ printf("WARNING: can't find /aliases node\n");
+ return;
+ }
+
+ path = fdt_getprop(fdt, ret, "ethernet0", NULL);
+ if (!path) {
+ printf("WARNING: can't find ethernet0 alias\n");
+ return;
+ }
+
+ do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
+}
+
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_tsec1_fixup(blob, bd);
}
#endif
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 9a312c3..4c04f2c 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -165,6 +165,15 @@ int fixed_sdram(void)
int checkboard (void)
{
+ /*
+ * Warning: do not read the BCSR registers here
+ *
+ * There is a timing bug in the 8349E and 8349EA BCSR code
+ * version 1.2 (read from BCSR 11) that will cause the CFI
+ * flash initialization code to overwrite BCSR 0, disabling
+ * the serial ports and gigabit ethernet
+ */
+
puts("Board: Freescale MPC8349EMDS\n");
return 0;
}
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index ecc67b6..9c19e30 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -20,58 +20,63 @@
*/
#include <asm/mmu.h>
+#include <asm/io.h>
#include <common.h>
-#include <asm/global_data.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_PCI
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349emds_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- }
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CFG_PCI1_MEM_BASE,
+ phys_start: CFG_PCI1_MEM_PHYS,
+ size: CFG_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CFG_PCI1_IO_BASE,
+ phys_start: CFG_PCI1_IO_PHYS,
+ size: CFG_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CFG_PCI1_MMIO_BASE,
+ phys_start: CFG_PCI1_MMIO_PHYS,
+ size: CFG_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
- {}
};
-#endif
-static struct pci_controller pci_hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- }
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+ {
+ bus_start: CFG_PCI2_MEM_BASE,
+ phys_start: CFG_PCI2_MEM_PHYS,
+ size: CFG_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CFG_PCI2_IO_BASE,
+ phys_start: CFG_PCI2_IO_PHYS,
+ size: CFG_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CFG_PCI2_MMIO_BASE,
+ phys_start: CFG_PCI2_MMIO_PHYS,
+ size: CFG_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
+#endif
-/**************************************************************************
- *
- * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
- *
- */
-void
-pib_init(void)
+#ifndef CONFIG_PCISLAVE
+void pib_init(void)
{
u8 val8, orig_i2c_bus;
/*
@@ -128,299 +133,86 @@ pib_init(void)
i2c_set_bus_num(orig_i2c_bus);
}
-/**************************************************************************
- * pci_init_board()
- *
- * NOTICE: PCI2 is not currently supported
- *
- */
-void
-pci_init_board(void)
+void pci_init_board(void)
{
- volatile immap_t * immr;
- volatile clk83xx_t * clk;
- volatile law83xx_t * pci_law;
- volatile pot83xx_t * pci_pot;
- volatile pcictrl83xx_t * pci_ctrl;
- volatile pciconf83xx_t * pci_conf;
- u16 reg16;
- u32 reg32;
- u32 dev;
- struct pci_controller * hose;
-
- immr = (immap_t *)CFG_IMMR;
- clk = (clk83xx_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci_hose[0];
+ volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+ /* initialize the PCA9555PW IO expander on the PIB board */
pib_init();
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
-
- reg32 = clk->occr;
- udelay(2000);
+ /* Enable all 8 PCI_CLK_OUTPUTS */
clk->occr = 0xff000000;
udelay(2000);
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-
-#ifdef CONFIG_MPC83XX_PCI2
- pci_ctrl[1].gcr = 0;
- udelay(2000);
- pci_ctrl[1].gcr = 1;
-#endif
-
- /* We need to wait at least a 1sec based on PCI specs */
- {
- int i;
-
- for (i = 0; i < 1000; ++i)
- udelay (1000);
- }
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space - prefetch */
- pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /* PCI1 mmio - non-prefetch mem space */
- pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CFG_PCI1_MMIO_BASE,
- CFG_PCI1_MMIO_PHYS,
- CFG_PCI1_MMIO_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CFG_IMMR+0x8300),
- (CFG_IMMR+0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ udelay(2000);
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC83XX_PCI2
- hose = &pci_hose[1];
-
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI2 mem space - prefetch */
- pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI2 IO space */
- pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /* PCI2 mmio - non-prefetch mem space */
- pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CFG_PCI2_MEM_BASE,
- CFG_PCI2_MEM_PHYS,
- CFG_PCI2_MEM_SIZE,
- PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CFG_PCI2_MMIO_BASE,
- CFG_PCI2_MMIO_PHYS,
- CFG_PCI2_MMIO_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CFG_PCI2_IO_BASE,
- CFG_PCI2_IO_PHYS,
- CFG_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- hose->region_count = 4;
+}
- pci_setup_indirect(hose,
- (CFG_IMMR+0x8380),
- (CFG_IMMR+0x8384));
+#else
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
- pci_register_hose(hose);
+ /* Enable all 8 PCI_CLK_OUTPUTS */
+ clk->occr = 0xff000000;
+ udelay(2000);
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
+ udelay(2000);
+ mpc83xx_pci_init(1, reg, 0);
+
+ /* Configure PCI Inbound Translation Windows (3 1MB windows) */
+ pci_ctrl->pitar0 = 0x0;
+ pci_ctrl->pibar0 = 0x0;
+ pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+ pci_ctrl->pitar1 = 0x0;
+ pci_ctrl->pibar1 = 0x0;
+ pci_ctrl->piebar1 = 0x0;
+ pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+ pci_ctrl->pitar2 = 0x0;
+ pci_ctrl->pibar2 = 0x0;
+ pci_ctrl->piebar2 = 0x0;
+ pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
}
+#endif /* CONFIG_PCISLAVE */
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#endif
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */
diff --git a/board/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile
index cfbecfb..cfbecfb 100644
--- a/board/mvblm7/Makefile
+++ b/board/matrix_vision/mvblm7/Makefile
diff --git a/board/mvblm7/config.mk b/board/matrix_vision/mvblm7/config.mk
index 1d85f4f..1d85f4f 100644
--- a/board/mvblm7/config.mk
+++ b/board/matrix_vision/mvblm7/config.mk
diff --git a/board/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c
index a60af01..a60af01 100644
--- a/board/mvblm7/fpga.c
+++ b/board/matrix_vision/mvblm7/fpga.c
diff --git a/board/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h
index 19277eb..19277eb 100644
--- a/board/mvblm7/fpga.h
+++ b/board/matrix_vision/mvblm7/fpga.h
diff --git a/board/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c
index b07f913..b07f913 100644
--- a/board/mvblm7/mvblm7.c
+++ b/board/matrix_vision/mvblm7/mvblm7.c
diff --git a/board/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h
index 03e9f41..03e9f41 100644
--- a/board/mvblm7/mvblm7.h
+++ b/board/matrix_vision/mvblm7/mvblm7.h
diff --git a/board/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/mvblm7_autoscript
index ec6e34e..6f9357f 100644
--- a/board/mvblm7/mvblm7_autoscript
+++ b/board/matrix_vision/mvblm7/mvblm7_autoscript
@@ -5,11 +5,17 @@ setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
setenv ramkernel setenv kernel_boot \${loadaddr}
setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam bootdtb
+setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
setenv set_static_ip setenv ipaddr \${static_ipaddr}
setenv set_static_nm setenv netmask \${static_netmask}
setenv set_static_gw setenv gatewayip \${static_gateway}
@@ -24,7 +30,7 @@ then
then
echo "=== bootp succeeded -> netboot ==="
run set_ip
- run getdtb rundtb bootfromnet ramparam bootdtb
+ run getdtb rundtb bootfromnet ramparam addcons bootdtb
else
echo "=== netboot failed ==="
fi
diff --git a/board/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c
index ef34a6b..ef34a6b 100644
--- a/board/mvblm7/pci.c
+++ b/board/matrix_vision/mvblm7/pci.c
diff --git a/common/fdt_support.c b/common/fdt_support.c
index e57ac0a..405b9db 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -408,24 +408,40 @@ void fdt_fixup_ethernet(void *fdt)
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
char *mode;
+ char *type;
const char *compat = "fsl-usb2-dr";
- const char *prop = "dr_mode";
+ const char *prop_mode = "dr_mode";
+ const char *prop_type = "phy_type";
int node_offset;
int err;
mode = getenv("usb_dr_mode");
- if (!mode)
+ type = getenv("usb_phy_type");
+ if (!mode && !type)
return;
node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
- if (node_offset < 0)
+ if (node_offset < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
compat, fdt_strerror(node_offset));
+ return;
+ }
- err = fdt_setprop(blob, node_offset, prop, mode, strlen(mode) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop, compat, fdt_strerror(err));
+ if (mode) {
+ err = fdt_setprop(blob, node_offset, prop_mode, mode,
+ strlen(mode) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_mode, compat, fdt_strerror(err));
+ }
+
+ if (type) {
+ err = fdt_setprop(blob, node_offset, prop_type, type,
+ strlen(type) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_type, compat, fdt_strerror(err));
+ }
}
#endif /* CONFIG_HAS_FSL_DR_USB */
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index adabf7a..c3ec5f8 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -167,6 +167,32 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
pci_init_bus(i, reg[i]);
}
+#ifdef CONFIG_PCISLAVE
+
+#define PCI_FUNCTION_CONFIG 0x44
+#define PCI_FUNCTION_CFG_LOCK 0x20
+
+/*
+ * Unlock the configuration bit so that the host system can begin booting
+ *
+ * This should be used after you have:
+ * 1) Called mpc83xx_pci_init()
+ * 2) Set up your inbound translation windows to the appropriate size
+ */
+void mpc83xx_pcislave_unlock(int bus)
+{
+ struct pci_controller *hose = &pci_hose[bus];
+ u32 dev;
+ u16 reg16;
+
+ /* Unlock configuration lock in PCI function configuration register */
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
+ reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
+ pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 5b21539..ff18303 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -61,7 +61,9 @@ typedef struct sysconf83xx {
u32 spcr; /* System Priority Configuration Register */
u32 sicrl; /* System I/O Configuration Register Low */
u32 sicrh; /* System I/O Configuration Register High */
- u8 res6[0x0C];
+ u8 res6[0x04];
+ u32 sidcr0; /* System I/O Delay Configuration Register 0 */
+ u32 sidcr1; /* System I/O Delay Configuration Register 1 */
u32 ddrcdr; /* DDR Control Driver Register */
u32 ddrdsr; /* DDR Debug Status Register */
u32 obir; /* Output Buffer Impedance Register */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index b0cc36d..006b93a 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -321,6 +321,8 @@
#define CONFIG_NET_MULTI 1
#endif
+#define CONFIG_HAS_FSL_DR_USB
+
/*
* TSEC
*/
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index a53f5cd..c8870b5 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -48,6 +48,11 @@
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_PCI
+#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
+#endif /* CONFIG_PCISLAVE */
+
#ifndef CONFIG_SYS_CLK_FREQ
#ifdef PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
@@ -406,6 +411,8 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -417,7 +424,7 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
@@ -573,6 +580,20 @@
HRCWL_CORE_TO_CSB_1X1)
#endif
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_AGENT |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_DISABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
#if defined(PCI_64BIT)
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
@@ -599,7 +620,8 @@
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
-#endif
+#endif /* PCI_64BIT */
+#endif /* CONFIG_PCISLAVE */
/*
* System performance
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 0dce9b4..849350f 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -406,22 +406,22 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 1000
-#define MV_CI "mvBL-M7"
-#define MV_VCI "mvBL-M7"
-#define MV_FPGA_DATA "0xfff80000"
-#define MV_FPGA_SIZE "0x76ca2"
-#define MV_KERNEL_ADDR "0xff810000"
-#define MV_INITRD_ADDR "0xffc00000"
-#define MV_AUTOSCR_ADDR "0xff804000"
-#define MV_AUTOSCR_ADDR2 "0xff806000"
-#define MV_DTB_ADDR "0xff808000"
-#define MV_INITRD_LENGTH "0x00300000"
+#define MV_CI mvBL-M7
+#define MV_VCI mvBL-M7
+#define MV_FPGA_DATA 0xfff80000
+#define MV_FPGA_SIZE 0x00076ca2
+#define MV_KERNEL_ADDR 0xff810000
+#define MV_INITRD_ADDR 0xffb00000
+#define MV_AUTOSCR_ADDR 0xff804000
+#define MV_AUTOSCR_ADDR2 0xff806000
+#define MV_DTB_ADDR 0xff808000
+#define MV_INITRD_LENGTH 0x00400000
#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define MV_KERNEL_ADDR_RAM "0x00100000"
-#define MV_DTB_ADDR_RAM "0x00600000"
-#define MV_INITRD_ADDR_RAM "0x01000000"
+#define MV_KERNEL_ADDR_RAM 0x00100000
+#define MV_DTB_ADDR_RAM 0x00600000
+#define MV_INITRD_ADDR_RAM 0x01000000
#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
then autoscr ${autoscr_addr}; \
@@ -431,25 +431,26 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
+ "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MV_FPGA_DATA "\0" \
- "fpgadatasize=" MV_FPGA_SIZE "\0" \
- "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \
- "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \
- "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \
- "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \
- "mv_initrd_addr=" MV_INITRD_ADDR "\0" \
- "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \
- "mv_initrd_length=" MV_INITRD_LENGTH "\0" \
- "mv_dtb_addr=" MV_DTB_ADDR "\0" \
- "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
- "dtb_name=" MV_DTB_NAME "\0" \
+ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
+ "autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0" \
+ "autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0" \
+ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MV_CI "\0" \
- "dhcp_vendor-class-identifier=" MV_VCI "\0" \
+ "dhcp_client_id=" MK_STR(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \
@@ -470,6 +471,7 @@
"gevss_debug=0\0" \
"watchdog=0\0" \
"usb_dr_mode=host\0" \
+ "sensor_cnt=2\0" \
""
#define CONFIG_FPGA_COUNT 1
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 70a4de7..5d82bb4 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -350,7 +350,9 @@
/* ATR - Arbiter Timers Register
*/
#define ATR_DTO 0x00FF0000 /* Data time out */
+#define ATR_DTO_SHIFT 16
#define ATR_ATO 0x000000FF /* Address time out */
+#define ATR_ATO_SHIFT 0
/* AER - Arbiter Event Register
*/
@@ -364,10 +366,15 @@
/* AEATR - Arbiter Event Address Register
*/
#define AEATR_EVENT 0x07000000 /* Event type */
+#define AEATR_EVENT_SHIFT 24
#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
+#define AEATR_MSTR_ID_SHIFT 16
#define AEATR_TBST 0x00000800 /* Transfer burst */
+#define AEATR_TBST_SHIFT 11
#define AEATR_TSIZE 0x00000700 /* Transfer Size */
+#define AEATR_TSIZE_SHIFT 8
#define AEATR_TTYPE 0x0000001F /* Transfer Type */
+#define AEATR_TTYPE_SHIFT 0
/* HRCWL - Hard Reset Configuration Word Low
*/