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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-11-17 20:21:20 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:09 -0600 |
| commit | abc76eb6a6936a99811eda256222b3927427f8e2 (patch) | |
| tree | 1594e2b321a612a47ac2114d16ccbf1a3ee53bd2 | |
| parent | effe4973f2f349e6e87d455ae718aabaf919a75d (diff) | |
| download | u-boot-imx-abc76eb6a6936a99811eda256222b3927427f8e2.zip u-boot-imx-abc76eb6a6936a99811eda256222b3927427f8e2.tar.gz u-boot-imx-abc76eb6a6936a99811eda256222b3927427f8e2.tar.bz2 | |
ppc/85xx: Map boot page guarded for MP boot
We already map the page cache-inhibited. There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | board/freescale/mpc8572ds/tlb.c | 2 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 2 | ||||
| -rw-r--r-- | board/freescale/p2020ds/tlb.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/mp.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/release.S | 4 |
5 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index d832f89..6a2a0b5 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 0009913..93d0bf7 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index b2e562a..36ad086 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 8568f5d..6530cb1 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -312,7 +312,7 @@ void setup_mp(void) disable_tlb(i); set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 55eca72..00c4c54 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -166,8 +166,8 @@ __secondary_start_page: lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - oris r11,r13,(MAS2_I)@h - ori r11,r13,(MAS2_I)@l + oris r11,r13,(MAS2_I|MAS2_G)@h + ori r11,r13,(MAS2_I|MAS2_G)@l mtspr SPRN_MAS2,r11 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l |