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| author | Wolfgang Denk <wd@denx.de> | 2010-11-30 21:15:25 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-11-30 21:15:25 +0100 |
| commit | a7bf3ecc71003f15470aeea43477be15bb15054e (patch) | |
| tree | 71ce3ea95c4f7c25b9f0011946d5b2581c9f0766 | |
| parent | bb7fc5744dd696552092cee571041d7df3128dbe (diff) | |
| parent | e45c98ad35ca600e25e9264528e7b6be17969f8c (diff) | |
| download | u-boot-imx-a7bf3ecc71003f15470aeea43477be15bb15054e.zip u-boot-imx-a7bf3ecc71003f15470aeea43477be15bb15054e.tar.gz u-boot-imx-a7bf3ecc71003f15470aeea43477be15bb15054e.tar.bz2 | |
Merge branch 'master' of /home/wd/git/u-boot/custodians
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/start.S | 8 | ||||
| -rw-r--r-- | include/configs/MPC8360EMDS.h | 4 |
2 files changed, 10 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 515be4c..460ac9a 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -1158,6 +1158,10 @@ map_flash_by_law1: bne 1b stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ + /* Wait for HW to catch up */ + lwz r4, LBLAWAR1(r3) + twi 0,r4,0 + isync blr /* Though all the LBIU Local Access Windows and LBC Banks will be @@ -1196,5 +1200,9 @@ remap_flash_by_law0: xor r4, r4, r4 stw r4, LBLAWBAR1(r3) stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ + /* Wait for HW to catch up */ + lwz r4, LBLAWAR1(r3) + twi 0,r4,0 + isync blr #endif /* CONFIG_SYS_FLASHBOOT */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 7b82c43..a959940 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -296,13 +296,13 @@ /* * CS4 on Local Bus, to PIB */ -#define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ +#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* * CS5 on Local Bus, to PIB */ -#define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ +#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* |