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| author | Nishanth Menon <nm@ti.com> | 2014-02-18 12:00:01 -0600 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 13:55:41 -0500 |
| commit | 82da4410f8fb68d2f1f8e1692baa1779cd03909e (patch) | |
| tree | f56ae3a861eb3f780c584530e3034bf57669f356 | |
| parent | 6e2192a3d80b315d071dfe0cbb70a35fe0a262e9 (diff) | |
| download | u-boot-imx-82da4410f8fb68d2f1f8e1692baa1779cd03909e.zip u-boot-imx-82da4410f8fb68d2f1f8e1692baa1779cd03909e.tar.gz u-boot-imx-82da4410f8fb68d2f1f8e1692baa1779cd03909e.tar.bz2 | |
DRA7: fix ABB efuse offset for OPP_NOM
commit 194dd74ad919e57026f385aaab7f89acf7ea79ef
(DRA7: add ABB setup for MPU voltage domain)
Made an offset typo error by using 0x4A003B24 as the efuse offset
for OPP_NOM. As per TI documentation, 0x4A003B24 is for OPP_OD, and
0x4A003B20 is for OPP_NOM. Fix the same.
Reported-by: Praveen Rao <prao@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ff32807..7292161 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -432,7 +432,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, - .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118, |