diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-04-17 08:33:26 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-04-25 21:14:19 +0200 |
| commit | 7a56f1791d84bb0fbd4e40bb6731915cc5ff6251 (patch) | |
| tree | c00a27603fa5819eee8b7f1df64b750cd404d3c2 | |
| parent | 3f215011142a7c3ed6e38f2712b8e875b8dcfd0f (diff) | |
| download | u-boot-imx-7a56f1791d84bb0fbd4e40bb6731915cc5ff6251.zip u-boot-imx-7a56f1791d84bb0fbd4e40bb6731915cc5ff6251.tar.gz u-boot-imx-7a56f1791d84bb0fbd4e40bb6731915cc5ff6251.tar.bz2 | |
imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR register
Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz.
CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the
bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c
from the mainline kernel.
mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for
this board as well.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| -rw-r--r-- | board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index f4cae5e..996d788 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -172,3 +172,14 @@ DATA 4 0x020e0010 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb |