powerpc: zpc1900: remove orphan board

This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>

5 files changed, 1 insertions, 558 deletions

diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile
deleted file mode 100644
index e636365..0000000
--- a/board/zpc1900/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= zpc1900.o
diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c
deleted file mode 100644
index fed4934..0000000
--- a/board/zpc1900/zpc1900.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <miiphy.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB  */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB  */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC  */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* SMC2 TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   0,   0,   0,   0,   0   }, /* PA6 */
-	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
-	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
-	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER  */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV  */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN  */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER  */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL    */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS    */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN  */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN CLSN */
-	/* PC28 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC21 */
-	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC20 */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RENA */
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT972 MDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT972 MDIO */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* PC0 */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD  */
-	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD  */
-	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   0,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-void *nvram_read(void *dest, long src, size_t count)
-{
-	return memcpy(dest, (const void *)src, count);
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	vu_char     *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555);
-	vu_char     *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA);
-	vu_char     *d = (vu_char *)dest;
-	const uchar *s = (const uchar *)src;
-
-	/* Unprotect the EEPROM */
-	*p1 = 0xAA;
-	*p2 = 0x55;
-	*p1 = 0x80;
-	*p1 = 0xAA;
-	*p2 = 0x55;
-	*p1 = 0x20;
-	udelay(10000);
-
-	/* Write the data to the EEPROM */
-	while (count--) {
-		*d++ = *s++;
-		while (*(d - 1) != *(s - 1))
-			/* wait */;
-	}
-
-	/* Protect the EEPROM */
-	*p1 = 0xAA;
-	*p2 = 0x55;
-	*p1 = 0xA0;
-	udelay(10000);
-}
-#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */
-
-phys_size_t initdram(int board_type)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr;
-	uchar c = 0xFF;
-	long int msize = CONFIG_SYS_SDRAM_SIZE;
-	int i;
-
-	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
-		immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
-		immap->im_siu_conf.sc_siumcr =
-			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
-			| SIUMCR_LBPC01;
-	}
-
-#ifndef CONFIG_SYS_RAMBOOT
-	immap->im_siu_conf.sc_ppc_acr  = 0x03;
-	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifdef CONFIG_SYS_LSDRAM_BASE
-	/*
-	  Initialise local bus SDRAM only if the pins
-	  are configured as local bus pins and not as PCI.
-	*/
-	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
-		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
-		memctl->memc_or4   = CONFIG_SYS_LSDRAM_OR;
-		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BR;
-		ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
-		for (i = 0; i < 8; i++)
-			*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN;
-	}
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
-	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_or2  = CONFIG_SYS_PSDRAM_OR;
-	memctl->memc_br2  = CONFIG_SYS_PSDRAM_BR;
-	/*
-	 * The mode data for Mode Register Write command must appear on
-	 * the address lines during a mode-set cycle. It is driven by
-	 * the memory controller, in single PowerQUICC II mode,
-	 * according to PSDMR[CL] and PSDMR[BL] fields. In
-	 * 60x-compatible mode, software must drive the correct value on
-	 * the address lines. BL=0 because for 64-bit port size burst
-	 * length must be 4.
-	 */
-	ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE |
-			      ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN;    /* Refresh enable */
-	*ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* Return total 60x bus SDRAM size */
-	return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
-	return 0;
-}
diff --git a/boards.cfg b/boards.cfg
index d286de7..2125fa6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1247,7 +1247,6 @@ Orphan  powerpc     mpc8260        -           -               ispan
 Orphan  powerpc     mpc8260        -           -               ispan               ISPAN_REVB                            ISPAN:SYS_REV_B                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
 Orphan  powerpc     mpc8260        -           -               rattler             Rattler                               -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
 Orphan  powerpc     mpc8260        -           -               rattler             Rattler8248                           Rattler:MPC8248                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
-Orphan  powerpc     mpc8260        -           -               zpc1900             ZPC1900                               -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK                           -                                                                                                                                 Anton Vorontsov <avorontsov@ru.mvista.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_33                        MPC8360ERDK:CLKIN_33MHZ                                                                                                           Anton Vorontsov <avorontsov@ru.mvista.com>
 Orphan  powerpc     mpc83xx        -           matrix_vision   mergerbox           MERGERBOX                             -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0a2d8fc..a042eea 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+zpc1900          powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 mpc8260ads       powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 adder            powerpc     mpc8xx         -           -           Yuli Barcohen <yuli@arabellasw.com>
 quad100hd	 powerpc     ppc405ep	    -		-	    Gary Jennejohn <gljennjohn@googlemail.com>
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
deleted file mode 100644
index d76a140..0000000
--- a/include/configs/ZPC1900.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (C) 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
- * This port was developed and tested on Revision C board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CPU_ID_STR		"MPC8265"
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
-#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
-#undef	CONFIG_CONS_NONE		/* It's not on external UART */
-#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
-#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX	2	/* FCC2 is used for Ethernet */
-
-#if (CONFIG_ETHER_INDEX == 2)
-/*
- * - Rx clock is CLK13
- * - Tx clock is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Full duplex
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII			/* MII PHY management        */
-#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT		2	/* Port C */
-#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE		MDIO_DECLARE
-
-#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
-#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
-#define MDIO_READ		((iop->pdat &  0x00400000) != 0)
-
-#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
-				else	iop->pdat &= ~0x00400000
-
-#define MDC(bit)		if(bit) iop->pdat |=  0x00200000; \
-				else	iop->pdat &= ~0x00200000
-
-#define MIIDELAY		udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE		38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND	"dhcp;bootm"	/* autoboot command */
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=:::::eth0:dhcp"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03800000	/* 1 ... 56 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		64
-
-#define CONFIG_SYS_IMMR		0xF0000000
-#define CONFIG_SYS_LSDRAM_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_BCSR		0xFEA00000
-#define CONFIG_SYS_EEPROM		0xFEB00000
-#define CONFIG_SYS_FLSIMM_BASE		0xFF000000
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
-
-#define BCSR_PCI_MODE		0x01
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
-				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
-				 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
-				 HRCW_MODCK_H0111                          \
-				) /* 0x16848207 */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
-#define CONFIG_ENV_IS_IN_NVRAM	1
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#  define CONFIG_ENV_SECT_SIZE	0x10000
-#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#else
-#  define CONFIG_ENV_ADDR		(CONFIG_SYS_EEPROM + 0x400)
-#  define CONFIG_ENV_SIZE		0x1000
-#  define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-#endif
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2		0
-
-#define CONFIG_SYS_SIUMCR		0x42200000
-#define CONFIG_SYS_SYPCR		0xFFFFFFC3
-#define CONFIG_SYS_BCR			0x90000000
-#define CONFIG_SYS_SCCR		SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR			RMR_CSRE
-#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR		0
-
-#define CONFIG_SYS_PSDMR		/* 0x834DA43B */0x014DA43A
-#define CONFIG_SYS_PSRT		0x0F/* 0x0C */
-#define CONFIG_SYS_LSDMR		0x0085A562
-#define CONFIG_SYS_LSRT		0x0F
-#define CONFIG_SYS_MPTPR		0x4000
-
-#define CONFIG_SYS_PSDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
-#define CONFIG_SYS_PSDRAM_OR		0xFC0028C0
-#define CONFIG_SYS_LSDRAM_BR		(CONFIG_SYS_LSDRAM_BASE | 0x00001861)
-#define CONFIG_SYS_LSDRAM_OR		0xFF803480
-
-#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00000801)
-#define CONFIG_SYS_OR0_PRELIM		0xFFE00856
-#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_EEPROM | 0x00000801)
-#define CONFIG_SYS_OR5_PRELIM		0xFFFF03F6
-#define CONFIG_SYS_BR6_PRELIM		(CONFIG_SYS_FLSIMM_BASE | 0x00001801)
-#define CONFIG_SYS_OR6_PRELIM		0xFF000856
-#define CONFIG_SYS_BR7_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR7_PRELIM		0xFFFF83F6
-
-#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
-
-#endif /* __CONFIG_H */