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| author | Dinh Nguyen <gills702@gmail.com> | 2012-06-08 05:26:52 +0000 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2012-07-11 13:15:31 -0500 |
| commit | 66f119e50cc854695a3709c67bf6a6c8ef60f6bc (patch) | |
| tree | 791c774f4a8c2152f6df5d95e5f81f69341fa76c | |
| parent | c59ab0921fcc99db87efa02022f4ca39dad975b2 (diff) | |
| download | u-boot-imx-66f119e50cc854695a3709c67bf6a6c8ef60f6bc.zip u-boot-imx-66f119e50cc854695a3709c67bf6a6c8ef60f6bc.tar.gz u-boot-imx-66f119e50cc854695a3709c67bf6a6c8ef60f6bc.tar.bz2 | |
net/designware: Consecutive writes to the same register to be avoided
This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
| -rw-r--r-- | drivers/net/designware.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 326d550..bf21a08 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -171,8 +171,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); - writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, &dma_p->opmode); conf = FRAMEBURSTENABLE | DISABLERXOWN; |