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author | Michal Simek <michal.simek@xilinx.com> | 2014-01-16 09:18:21 +0100 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-19 09:41:21 +0100 |
commit | 627981213ad1693591a03614d35ccdc060aa5935 (patch) | |
tree | d4a4463a525eedef2f935fde2834fd11119718c1 | |
parent | e66da8bbf45762a340371bf8aff730cb17454801 (diff) | |
download | u-boot-imx-627981213ad1693591a03614d35ccdc060aa5935.zip u-boot-imx-627981213ad1693591a03614d35ccdc060aa5935.tar.gz u-boot-imx-627981213ad1693591a03614d35ccdc060aa5935.tar.bz2 |
zynq: Move bootmode to headers
These numbers will be reused by SPL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 6 | ||||
-rw-r--r-- | board/xilinx/zynq/board.c | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index cd69677..1fe0448 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -21,6 +21,12 @@ #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 +/* Bootmode setting values */ +#define ZYNQ_BM_MASK 0xF +#define ZYNQ_BM_NOR 0x2 +#define ZYNQ_BM_SD 0x5 +#define ZYNQ_BM_JTAG 0x0 + /* Reflect slcr offsets */ struct slcr_regs { u32 scl; /* 0x0 */ diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 16d2d99..82f2345 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -12,12 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Bootmode setting values */ -#define ZYNQ_BM_MASK 0x0F -#define ZYNQ_BM_NOR 0x02 -#define ZYNQ_BM_SD 0x05 -#define ZYNQ_BM_JTAG 0x0 - #ifdef CONFIG_FPGA Xilinx_desc fpga; |