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authorHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-06-20 10:41:05 +0200
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-06-20 12:46:48 +0200
commit5f723a3b98c630bde33de74351f2121691fdef14 (patch)
tree3fac4e5d3fe16b8c6696822d0ab1744ab4263e24
parent5605ef6b5802921cbefe6a933a9dea3497396b5c (diff)
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avr32: Enable SPI flash support on ATNGW100
The ATNGW100 has 8MB DataFlash on board. Give users access to it through the new SPI flash framework. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-rw-r--r--board/atmel/atngw100/atngw100.c25
-rw-r--r--include/configs/atngw100.h6
2 files changed, 31 insertions, 0 deletions
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index 375f0e7..f2c3e79 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -60,6 +60,9 @@ int board_early_init_f(void)
#if defined(CONFIG_MMC)
gpio_enable_mmci();
#endif
+#if defined(CONFIG_ATMEL_SPI)
+ gpio_enable_spi0(1 << 0);
+#endif
return 0;
}
@@ -89,3 +92,25 @@ void board_init_info(void)
gd->bd->bi_phy_id[0] = 0x01;
gd->bd->bi_phy_id[1] = 0x03;
}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA3
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 3fc9975..7ac51b5 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -114,6 +114,8 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
@@ -126,6 +128,10 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_SPI 1
+
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_ATMEL 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32