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| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2008-01-08 15:39:01 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-09 06:32:54 +0100 |
| commit | 580d1d3186a2bc6dbdb626941b716dae1788e51e (patch) | |
| tree | 4a1d32f3db2f6ab83c61bc9bd1ff0ad0b7d7162a | |
| parent | ff5fb8a6ccba56e3482d0e297d8cfb7faa040811 (diff) | |
| download | u-boot-imx-580d1d3186a2bc6dbdb626941b716dae1788e51e.zip u-boot-imx-580d1d3186a2bc6dbdb626941b716dae1788e51e.tar.gz u-boot-imx-580d1d3186a2bc6dbdb626941b716dae1788e51e.tar.bz2 | |
ppc4xx: Fix UIC2 vector number base
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| -rw-r--r-- | cpu/ppc4xx/vecnum.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 93e51b9..8d04b69 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -106,16 +106,16 @@ #define VECNUM_RXDE VECNUM_MRDE /* UIC 2 */ -#define VECNUM_EIR5 (62 + 0) /* External interrupt 5 */ -#define VECNUM_EIR6 (62 + 1) /* External interrupt 6 */ -#define VECNUM_OPB (62 + 2) /* OPB to PLB bridge int stat */ -#define VECNUM_EIR2 (62 + 3) /* External interrupt 2 */ -#define VECNUM_EIR3 (62 + 4) /* External interrupt 3 */ -#define VECNUM_DDR2 (62 + 5) /* DDR2 sdram */ -#define VECNUM_MCTX0 (62 + 6) /* MAl intp coalescence TX0 */ -#define VECNUM_MCTX1 (62 + 7) /* MAl intp coalescence TX1 */ -#define VECNUM_MCTR0 (62 + 8) /* MAl intp coalescence TR0 */ -#define VECNUM_MCTR1 (62 + 9) /* MAl intp coalescence TR1 */ +#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ +#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ +#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ +#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ +#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ +#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ +#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ +#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ +#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ +#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ #elif defined(CONFIG_440SPE) @@ -152,12 +152,12 @@ #define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ /* UIC 2 */ -#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ -#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ -#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ -#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ -#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ -#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ +#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */ +#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */ +#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */ +#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */ +#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */ +#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */ #elif defined(CONFIG_440SP) |