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| author | Jason Liu <jason.hui@linaro.org> | 2011-11-25 00:18:04 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-01-08 21:28:16 -0600 |
| commit | 4692708d452b054fe5996405ee5cfff1f3b23070 (patch) | |
| tree | 47d6830d1fee67dbe73e73ea3ad5251d576bbd3e | |
| parent | 9a420986cccc9bd2c37affd931d627b3c3e72952 (diff) | |
| download | u-boot-imx-4692708d452b054fe5996405ee5cfff1f3b23070.zip u-boot-imx-4692708d452b054fe5996405ee5cfff1f3b23070.tar.gz u-boot-imx-4692708d452b054fe5996405ee5cfff1f3b23070.tar.bz2 | |
i.mx: fsl_esdhc: add the i.mx6q support
The mmc host controller on the i.mx6q is called usdhc which
is redesigned based on the freescale esdhc controller.
The usdhc controller is almost compatible with esdhc except
it adds one mix register to support debug/SD3.0 and move
the low bit 0-6 of XFERTYP register to the mix control reg
low bit 0-6. Thus on i.mx6q, we have the following compared
with the previous soc: (can refer to RM of chapter 56.3.3)
i.mx6q:
mix control:
bit 31 - bit 7: Added for debug/SD3.0 support
bit 6 - bit 0: move in the XFERTYP register bit 6-0 on previous soc
XFERTYP register:
bit 31 - bit 7: the same as before,
bit 6 - bit 0: no-use
previous soc
mix control: no
XFERTYP register:
bit 31 - bit 0: xfertype information
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index ec953f0..ddd1b4c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -58,7 +58,8 @@ struct fsl_esdhc { uint autoc12err; uint hostcapblt; uint wml; - char reserved1[8]; + uint mixctrl; + char reserved1[4]; uint fevt; char reserved2[168]; uint hostver; @@ -298,8 +299,13 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Send the command */ esdhc_write32(®s->cmdarg, cmd->cmdarg); +#if defined(CONFIG_FSL_USDHC) + esdhc_write32(®s->mixctrl, + (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); +#else esdhc_write32(®s->xfertyp, xfertyp); - +#endif /* Wait for the command to complete */ while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) ; @@ -482,7 +488,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc = malloc(sizeof(struct mmc)); - sprintf(mmc->name, "FSL_ESDHC"); + sprintf(mmc->name, "FSL_SDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; /* First reset the eSDHC controller */ |