powerpc/85xx: Add support for new P102x/P2020 RDB style boards

The following boards share a common design but with minor variations
between them:

P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC

The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.

Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>

10 files changed, 2289 insertions, 0 deletions

diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
new file mode 100644
index 0000000..8056af8
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += ddr.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
new file mode 100644
index 0000000..f0cbde7
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_DDR_RAW_TIMING
+#if	defined(CONFIG_P1020RDB_PROTO) || \
+	defined(CONFIG_P1021RDB) || \
+	defined(CONFIG_P1020UTM)
+/* Micron MT41J256M8_187E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1870,
+	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
+	.tAA_ps = 13125,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13125,
+	.tRRD_ps = 7500,
+	.tRP_ps = 13125,
+	.tRAS_ps = 37500,
+	.tRC_ps = 50625,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 37500,
+};
+#elif defined(CONFIG_P2020RDB)
+/* Micron MT41J128M16_15E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1500,
+	.caslat_X = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.tAA_ps = 13500,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13500,
+	.tRRD_ps = 6000,
+	.tRP_ps = 13500,
+	.tRAS_ps = 36000,
+	.tRC_ps = 49500,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 30000,
+};
+#elif defined(CONFIG_P1020MBG)
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 1073741824u,
+	.capacity = 2147483648u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1870,
+	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
+	.tAA_ps = 13125,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13125,
+	.tRRD_ps = 7500,
+	.tRP_ps = 13125,
+	.tRAS_ps = 37500,
+	.tRC_ps = 50625,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 37500,
+};
+#elif defined(CONFIG_P1020RDB)
+/*
+ * Samsung K4B2G0846C-HCF8
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1875,
+	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
+	.tAA_ps = 13125,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13125,
+	.tRRD_ps = 7500,
+	.tRP_ps = 13125,
+	.tRAS_ps = 37500,
+	.tRC_ps = 50625,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 37500,
+};
+#elif	defined(CONFIG_P1024RDB) || \
+	defined(CONFIG_P1025RDB)
+/*
+ * Samsung K4B2G0846C-HCH9
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1500,
+	.caslat_X = 0x3e << 4,	/* 5,6,7,8,9 */
+	.tAA_ps = 13125,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13125,
+	.tRRD_ps = 6000,
+	.tRP_ps = 13125,
+	.tRAS_ps = 36000,
+	.tRC_ps = 49125,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 30000,
+};
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DDR_RAW_TIMING */
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+			strmhz(buf, sysinfo.freqDDRBus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	int i;
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	if (pdimm->primary_sdram_width == 64)
+		popts->data_bus_width = 0;
+	else if (pdimm->primary_sdram_width == 32)
+		popts->data_bus_width = 1;
+	else
+		printf("Error in DDR bus width configuration!\n");
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
new file mode 100644
index 0000000..5ff6ea6
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_VSC7385_ENET
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
new file mode 100644
index 0000000..4671128
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -0,0 +1,449 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <ioports.h>
+#include <asm/fsl_serdes.h>
+#include <netdev.h>
+
+#ifdef CONFIG_QE
+
+#define GPIO_GETH_SW_PORT	1
+#define GPIO_GETH_SW_PIN	29
+#define GPIO_GETH_SW_DATA	(1 << (31 - GPIO_GETH_SW_PIN))
+
+#define GPIO_SLIC_PORT		1
+#define GPIO_SLIC_PIN		30
+#define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))
+
+
+#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+#define PCA_IOPORT_I2C_ADDR		0x23
+#define PCA_IOPORT_OUTPUT_CMD		0x2
+#define PCA_IOPORT_CFG_CMD		0x6
+#define PCA_IOPORT_QE_PIN_ENABLE	0xf8
+#define PCA_IOPORT_QE_TDM_ENABLE	0xf6
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GPIO */
+	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
+#if 0
+	{1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
+#endif
+	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
+	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
+	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */
+
+#ifdef CONFIG_P1025RDB
+	/* QE_MUX_MDC */
+	{1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
+
+	/* QE_MUX_MDIO */
+	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */
+
+	/* UCC_1_MII */
+	{0, 23, 2, 0, 2}, /* CLK12 */
+	{0, 24, 2, 0, 1}, /* CLK9 */
+	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
+	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
+	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
+	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
+	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
+	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
+	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
+	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
+	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
+	{0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
+	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
+	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
+	{0, 17, 2, 0, 2}, /* ENET1_CRS    */
+	{0, 16, 2, 0, 2}, /* ENET1_COL    */
+
+	/* UCC_5_RMII */
+	{1, 11, 2, 0, 1}, /* CLK13 */
+	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
+	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
+	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
+	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
+	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
+	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
+	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
+#endif
+
+	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
+struct cpld_data {
+	u8 cpld_rev_major;
+	u8 pcba_rev;
+	u8 wd_cfg;
+	u8 rst_bps_sw;
+	u8 load_default_n;
+	u8 rst_bps_wd;
+	u8 bypass_enable;
+	u8 bps_led;
+	u8 status_led;                  /* offset: 0x8 */
+	u8 fxo_led;                     /* offset: 0x9 */
+	u8 fxs_led;                     /* offset: 0xa */
+	u8 rev4[2];
+	u8 system_rst;                  /* offset: 0xd */
+	u8 bps_out;
+	u8 rev5[3];
+	u8 cpld_rev_minor;
+};
+
+#define CPLD_WD_CFG	0x03
+#define CPLD_RST_BSW	0x00
+#define CPLD_RST_BWD	0x00
+#define CPLD_BYPASS_EN	0x03
+#define CPLD_STATUS_LED	0x01
+#define CPLD_FXO_LED	0x01
+#define CPLD_FXS_LED	0x0F
+#define CPLD_SYS_RST	0x00
+
+void board_cpld_init(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
+	out_8(&cpld_data->status_led, CPLD_STATUS_LED);
+	out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
+	out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
+	out_8(&cpld_data->system_rst, CPLD_SYS_RST);
+}
+
+void board_gpio_init(void)
+{
+#ifdef CONFIG_QE
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+
+	/* Enable VSC7385 switch */
+	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
+
+	/* Enable SLIC */
+	setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
+#else
+
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+	/*
+	 * GPIO10 DDR Reset, open drain
+	 * GPIO7  LOAD_DEFAULT_N          Input
+	 * GPIO11  WDI (watchdog input)
+	 * GPIO12  Ethernet Switch Reset
+	 * GPIO13  SLIC Reset
+	 */
+
+	setbits_be32(&pgpio->gpdir, 0x02130000);
+#ifndef CONFIG_SYS_RAMBOOT
+	/* init DDR3 reset signal */
+	setbits_be32(&pgpio->gpdir, 0x00200000);
+	setbits_be32(&pgpio->gpodr, 0x00200000);
+	clrbits_be32(&pgpio->gpdat, 0x00200000);
+	udelay(1000);
+	setbits_be32(&pgpio->gpdat, 0x00200000);
+	udelay(1000);
+	clrbits_be32(&pgpio->gpdir, 0x00200000);
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* reset VSC7385 Switch */
+	setbits_be32(&pgpio->gpdir, 0x00080000);
+	setbits_be32(&pgpio->gpdat, 0x00080000);
+#endif
+
+#ifdef CONFIG_SLIC
+	/* reset SLIC */
+	setbits_be32(&pgpio->gpdir, 0x00040000);
+	setbits_be32(&pgpio->gpdat, 0x00040000);
+#endif
+#endif
+}
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+	clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
+
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
+
+	board_gpio_init();
+	board_cpld_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 in, out, io_config, val;
+
+	printf("Board: %s ", CONFIG_BOARDNAME);
+
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+
+	printf("CPLD: V%d.%d PCBA: V%d.0\n",
+		in_8(&cpld_data->cpld_rev_major) & 0x0F,
+		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
+		in_8(&cpld_data->pcba_rev) & 0x0F);
+
+	/* Initialize i2c early for rom_loc and flash bank information */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
+	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+
+	val = (in & io_config) | (out & (~io_config));
+
+	puts("rom_loc: ");
+	if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
+		puts("sd");
+#ifdef __SW_BOOT_SPI
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
+		puts("spi");
+#endif
+#ifdef __SW_BOOT_NAND
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
+		puts("nand");
+#endif
+#ifdef __SW_BOOT_PCIE
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
+		puts("pcie");
+#endif
+	} else {
+		if (val & 0x2)
+			puts("nor lower bank");
+		else
+			puts("nor upper bank");
+	}
+	puts("\n");
+
+	if (val & 0x1) {
+		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+		puts("SD/MMC : 8-bit Mode\n");
+		puts("eSPI : Disabled\n");
+	} else {
+		puts("SD/MMC : 4-bit Mode\n");
+		puts("eSPI : Enabled\n");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	ccsr_gur_t *gur __attribute__((unused)) =
+		(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+#ifdef CONFIG_VSC7385_ENET
+	char *tmp;
+	unsigned int vscfw_addr;
+#endif
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		printf("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+#ifdef CONFIG_VSC7385_ENET
+	/* If a VSC7385 microcode image is present, then upload it. */
+	if ((tmp = getenv("vscfw_addr")) != NULL) {
+		vscfw_addr = simple_strtoul(tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *) vscfw_addr,
+					CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else
+		puts("No address specified for VSC7385 microcode.\n");
+#endif
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+#if defined(CONFIG_UEC_ETH)
+	/*  QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
+
+	uec_standard_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_QE) && \
+	(defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
+static void fdt_board_fixup_qe_pins(void *blob)
+{
+	unsigned int oldbus;
+	u8 val8;
+	int node;
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	if (hwconfig("qe")) {
+		/* For QE and eLBC pins multiplexing,
+		 * there is a PCA9555 device on P1025RDB.
+		 * It control the multiplex pins' functions,
+		 * and setting the PCA9555 can switch the
+		 * function between QE and eLBC.
+		 */
+		oldbus = i2c_get_bus_num();
+		i2c_set_bus_num(0);
+		if (hwconfig("tdm"))
+			val8 = PCA_IOPORT_QE_TDM_ENABLE;
+		else
+			val8 = PCA_IOPORT_QE_PIN_ENABLE;
+		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
+				1, &val8, 1);
+		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
+				1, &val8, 1);
+		i2c_set_bus_num(oldbus);
+		/* if run QE TDM, Set ABSWP to implement
+		 * conversion of addresses in the eLBC.
+		 */
+		if (hwconfig("tdm")) {
+			set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
+			set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
+			setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+		}
+	} else {
+		node = fdt_path_offset(blob, "/qe");
+		if (node >= 0)
+			fdt_del_node(blob, node);
+	}
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_QE
+	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+			sizeof("okay"), 0);
+#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+	fdt_board_fixup_qe_pins(blob);
+#endif
+#endif
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
new file mode 100644
index 0000000..6d22463
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_NAND_SPL
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI memory 1.5G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O effective: 192K  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+
+#ifdef CONFIG_SYS_NAND_BASE
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+	/* *I*G - eSDHC/eSPI/NAND boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 8, BOOKE_PAGESZ_1G, 1),
+
+#ifdef CONFIG_P1020MBG
+	/* 2G DDR on P1020MBG, map the second 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 9, BOOKE_PAGESZ_1G, 1),
+#endif
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index d32ff7e..b224a9c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -574,6 +574,10 @@ P1011RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freesca
 P1011RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,NAND
 P1011RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,SDCARD
 P1011RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,SPIFLASH
+P1020MBG-PC                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020MBG
+P1020MBG-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020MBG,36BIT
+P1020MBG-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020MBG,SDCARD
+P1020MBG-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT
 P1020RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB
 P1020RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,36BIT
 P1020RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,36BIT,SDCARD
@@ -581,10 +585,40 @@ P1020RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freesca
 P1020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,NAND
 P1020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SDCARD
 P1020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SPIFLASH
+P1020RDB-PC                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB
+P1020RDB-PC_NAND             powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,NAND
+P1020RDB-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,SDCARD
+P1020RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,SPIFLASH
+P1020RDB-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,36BIT
+P1020RDB-PC_36BIT_NAND       powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,36BIT,NAND
+P1020RDB-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,36BIT,SDCARD
+P1020RDB-PC_36BIT_SPIFLASH   powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,36BIT,SPIFLASH
+P1020UTM-PC                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM
+P1020UTM-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM,SDCARD
+P1020UTM-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM,36BIT
+P1020UTM-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD
+P1021RDB-PC                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB
+P1021RDB-PC_NAND             powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,NAND
+P1021RDB-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,SDCARD
+P1021RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,SPIFLASH
+P1021RDB-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,36BIT
+P1021RDB-PC_36BIT_NAND       powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,36BIT,NAND
+P1021RDB-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD
+P1021RDB-PC_36BIT_SPIFLASH   powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH
 P1022DS                      powerpc     mpc85xx     p1022ds             freescale
 P1022DS_36BIT                powerpc     mpc85xx     p1022ds             freescale      -           P1022DS:36BIT
 P1023RDS                     powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS
 P1023RDS_NAND                powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS:NAND
+P1024RDB                     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB
+P1024RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB,36BIT
+P1024RDB_NAND                powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB,NAND
+P1024RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB,SDCARD
+P1024RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB,SPIFLASH
+P1025RDB                     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1025RDB
+P1025RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1025RDB,36BIT
+P1025RDB_NAND                powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1025RDB,NAND
+P1025RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1025RDB,SDCARD
+P1025RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1025RDB,SPIFLASH
 P2010RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB
 P2010RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,36BIT
 P2010RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,36BIT,SDCARD
@@ -604,6 +638,14 @@ P2020RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,NAND
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
+P2020RDB-PC                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB
+P2020RDB-PC_NAND             powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,NAND
+P2020RDB-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,SDCARD
+P2020RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,SPIFLASH
+P2020RDB-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT
+P2020RDB-PC_36BIT_NAND       powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT,NAND
+P2020RDB-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD
+P2020RDB-PC_36BIT_SPIFLASH   powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH
 P2041RDB                     powerpc     mpc85xx     p2041rdb            freescale
 P2041RDB_SDCARD              powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SPIFLASH            powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
diff --git a/doc/README.p1_p2_rdb_pc b/doc/README.p1_p2_rdb_pc
new file mode 100644
index 0000000..4437731
--- /dev/null
+++ b/doc/README.p1_p2_rdb_pc
@@ -0,0 +1,46 @@
+Overview
+--------
+P1_P2_RDB_PC represents a set of boards including
+    P1020MSBG-PC
+    P1020RDB-PC
+    P1020UTM-PC
+    P1021RDB-PC
+    P1024RDB
+    P1025RDB
+    P2020RDB-PC
+
+They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
+has 64-bit DDR. All others have 32-bit DDR.
+
+Key features on these boards include:
+    * DDR3
+    * NOR flash
+    * NAND flash (on RDB's only)
+    * SPI flash (on RDB's only)
+    * SDHC/MMC card slot
+    * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
+    * PCIE slot and mini-PCIE slots
+
+As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
+is used to store SPD data. In case of absent or corrupted SPD, falling back
+to timing data embedded in the source code will be used. Raw timing data is
+extracted from DDR chip datasheet. Different speeds of DDR are supported with
+this approach. ODT option is forced to fit this set of boards, again because
+they don't have regular DIMMs.
+
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
+for writing timing.
+
+VSC firmware Address is defined by default in config file for eTSEC1.
+
+SD width is based off DIP switch. DIP switch is detected on the
+board by reading i2c bus and setting the appropriate mux values.
+
+Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
+pins multiplexing. QE function needs to be disabled to access Nor Flash and
+CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
+in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
+enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
+
+'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
+'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
new file mode 100644
index 0000000..b9b89cf
--- /dev/null
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -0,0 +1,984 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * QorIQ RDB boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#if defined(CONFIG_P1020MBG)
+#define CONFIG_BOARDNAME "P1020MBG"
+#define CONFIG_P1020
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xe4
+#define __SW_BOOT_SD		0x54
+#endif
+
+#if defined(CONFIG_P1020UTM)
+#define CONFIG_BOARDNAME "P1020UTM"
+#define CONFIG_P1020
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xe0
+#define __SW_BOOT_SD		0x50
+#endif
+
+#if defined(CONFIG_P1020RDB)
+#define CONFIG_BOARDNAME "P1020RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x5c
+#define __SW_BOOT_SPI		0x1c
+#define __SW_BOOT_SD		0x9c
+#define __SW_BOOT_NAND		0xec
+#define __SW_BOOT_PCIE		0x6c
+#endif
+
+#if defined(CONFIG_P1021RDB)
+#define CONFIG_BOARDNAME "P1021RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1021
+#define CONFIG_QE
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x5c
+#define __SW_BOOT_SPI		0x1c
+#define __SW_BOOT_SD		0x9c
+#define __SW_BOOT_NAND		0xec
+#define __SW_BOOT_PCIE		0x6c
+#endif
+
+#if defined(CONFIG_P1024RDB)
+#define CONFIG_BOARDNAME "P1024RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1024
+#define CONFIG_SLIC
+#define CONFIG_SPI_FLASH
+#define __SW_BOOT_MASK		0xf3
+#define __SW_BOOT_NOR		0x00
+#define __SW_BOOT_SPI		0x08
+#define __SW_BOOT_SD		0x04
+#define __SW_BOOT_NAND		0x0c
+#endif
+
+#if defined(CONFIG_P1025RDB)
+#define CONFIG_BOARDNAME "P1025RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1025
+#define CONFIG_QE
+#define CONFIG_SLIC
+#define CONFIG_SPI_FLASH
+
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+#define __SW_BOOT_MASK		0xf3
+#define __SW_BOOT_NOR		0x00
+#define __SW_BOOT_SPI		0x08
+#define __SW_BOOT_SD		0x04
+#define __SW_BOOT_NAND		0x0c
+#endif
+
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P2020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xc8
+#define __SW_BOOT_SPI		0x28
+#define __SW_BOOT_SD		0x68 /* or 0x18 */
+#define __SW_BOOT_NAND		0xe8
+#define __SW_BOOT_PCIE		0xa8
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
+#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_TEXT_BASE_SPL	0xff800000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE_SPL
+#else
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500
+#define CONFIG_MPC85xx
+
+#define CONFIG_MP
+
+#define CONFIG_FSL_ELBC
+#define CONFIG_PCI
+#define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW
+#define CONFIG_TSEC_ENET	/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL3114
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#else
+#define CONFIG_SYS_CLK_FREQ	66666666
+#endif
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ENABLE_36BIT_PHYS
+#endif
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+       SPL code*/
+#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS 0x52
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#ifdef CONFIG_P1020MBG
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#else
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* Default settings for DDR3 */
+#ifdef CONFIG_P2020RDB
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8645F607
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC7000000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330104
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4644
+#define CONFIG_SYS_DDR_TIMING_2		0x0FA88CCF
+#define CONFIG_SYS_DDR_CLK_CTRL		0x02000000
+#define CONFIG_SYS_DDR_MODE_1		0x00421422
+#define CONFIG_SYS_DDR_MODE_2		0x04000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0C300100
+
+#else
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x40461520
+#define CONFIG_SYS_DDR_MODE_2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x0C300000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff	DDR	Up to 2GB cacheable
+ * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
+ * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX 0xXXXX_XXXX	SRAM	YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xec00_0000 0xefff_ffff	FLASH	Up to 64M non-cacheable
+ * 0xff80_0000 0xff8f_ffff	NAND flash	1M non-cacheable
+ * 0xff90_0000 0xff97_ffff	L2 SDRAM(REV.)  512K cacheable(optional)
+ * 0xffa0_0000 0xffaf_ffff	CPLD	1M non-cacheable
+ * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff	CCSR	1M non-cacheable
+ */
+
+
+/*
+ * Local Bus Definitions
+ */
+#if defined(CONFIG_P1020MBG)
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+#elif defined(CONFIG_P1020UTM)
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
+#define CONFIG_SYS_FLASH_BASE		0xee000000
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
+#define CONFIG_SYS_FLASH_BASE		0xef000000
+#endif
+
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
+	| BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \
+	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+	| BR_PS_8	/* Port Size = 8 bit */ \
+	| BR_MS_FCM	/* MSEL = FCM */ \
+	| BR_V)	/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
+	| OR_FCM_CSCT \
+	| OR_FCM_CST \
+	| OR_FCM_CHT \
+	| OR_FCM_SCY_1 \
+	| OR_FCM_TRLX \
+	| OR_FCM_EHTR)
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_CPLD_BASE	0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#endif
+/* CPLD config size: 1Mb */
+#define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
+
+#define CONFIG_SYS_PMC_BASE	0xff980000
+#define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
+#define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+				 OR_GPCM_EAD)
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#endif
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
+
+
+/* Vsc7385 switch */
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_SYS_VSC7385_BASE		0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
+#else
+#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+#endif
+
+#define CONFIG_SYS_VSC7385_BR_PRELIM	\
+	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
+			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
+			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
+
+/* The size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C spd and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}} /* Don't probe this addr */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
+
+/*
+ * I2C2 EEPROM
+ */
+#undef CONFIG_ID_EEPROM
+
+#define CONFIG_RTC_PT7C4338
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_SPI_FLASH)
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	10000000
+#define CONFIG_SF_DEFAULT_MODE	0
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
+
+/* video */
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	/* do pci plug-and-play */
+#define CONFIG_E1000	/* Defind e1000 pci Ethernet card*/
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR	2
+#define TSEC2_PHY_ADDR	0
+#define TSEC3_PHY_ADDR	1
+
+#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX	0
+#define TSEC2_PHYIDX	0
+#define TSEC3_PHYIDX	0
+
+#define CONFIG_ETHPRIME	"eTSEC1"
+
+#define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_ADDR		0xefec0000
+#define CONFIG_SYS_QE_FW_LENGTH		0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_P1025RDB
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1	/* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5	/* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_P1025RDB */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#else
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR	0xfff80000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+		 || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#undef CONFIG_WATCHDOG	/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#define CONFIG_BOOTARGS	/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#ifdef __SW_BOOT_NOR
+#define __NOR_RST_CMD	\
+norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_SPI
+#define __SPI_RST_CMD	\
+spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_SD
+#define __SD_RST_CMD	\
+sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_NAND
+#define __NAND_RST_CMD	\
+nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_PCIE
+#define __PCIE_RST_CMD	\
+pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"netdev=eth0\0"	\
+"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"	\
+"loadaddr=1000000\0"	\
+"bootfile=uImage\0"	\
+"tftpflash=tftpboot $loadaddr $uboot; "	\
+	"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
+"consoledev=ttyS0\0"	\
+"ramdiskaddr=2000000\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"fdtaddr=c00000\0"	\
+"bdev=sda1\0" \
+"jffs2nor=mtdblock3\0"	\
+"norbootaddr=ef080000\0"	\
+"norfdtaddr=ef040000\0"	\
+"jffs2nand=mtdblock9\0"	\
+"nandbootaddr=100000\0"	\
+"nandfdtaddr=80000\0"		\
+"ramdisk_size=120000\0"	\
+"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
+"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
+MK_STR(__NOR_RST_CMD)"\0" \
+MK_STR(__SPI_RST_CMD)"\0" \
+MK_STR(__SD_RST_CMD)"\0" \
+MK_STR(__NAND_RST_CMD)"\0" \
+MK_STR(__PCIE_RST_CMD)"\0"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+"setenv bootargs root=/dev/nfs rw "	\
+"nfsroot=$serverip:$rootpath "	\
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;"	\
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"fatload usb 0:2 $loadaddr $bootfile;"	\
+"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"ext2load usb 0:4 $loadaddr $bootfile;"	\
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT	\
+"setenv bootargs root=/dev/$jffs2nor rw "	\
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"tftp $ramdiskaddr $ramdiskfile;"	\
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
new file mode 100644
index 0000000..475cc49
--- /dev/null
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
@@ -0,0 +1,137 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
+PAD_TO := 0xff801000
+
+include $(TOPDIR)/config.mk
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
+		$(LDFLAGS) $(LDFLAGS_FINAL)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o resetvec.o
+COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(nandobj)board/$(BOARDDIR)
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+	@rm -f $(obj)cache.c
+	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+	@rm -f $(obj)cpu_init_early.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+	@rm -f $(obj)cpu_init_nand.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+	@rm -f $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+	@rm -f $(obj)law.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+	@rm -f $(obj)nand_boot_fsl_elbc.c
+	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+	       $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+	@rm -f $(obj)ns16550.c
+	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+	@rm -f $(obj)fixed_ivor.S
+	ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+	@rm -f $(obj)start.S
+	ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+
+$(obj)tlb.c:
+	@rm -f $(obj)tlb.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+	@rm -f $(obj)tlb_table.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+	@rm -f $(obj)nand_boot.c
+	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
new file mode 100644
index 0000000..b9796ea
--- /dev/null
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#define udelay(x) {int i, j; \
+			for (i = 0; i < x; i++) \
+				for (j = 0; j < 10000; j++) \
+					; }
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+void sdram_init(void)
+{
+	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+	out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
+	out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
+#endif
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
+	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+
+	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+
+	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL);
+
+	/* Set, but do not enable the memory */
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
+
+	asm volatile("sync;isync");
+	udelay(500);
+
+	/* Let the controller go */
+	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifndef CONFIG_QE
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+#ifndef CONFIG_QE
+	/* init DDR3 reset signal */
+	out_be32(&pgpio->gpdir, 0x02000000);
+	out_be32(&pgpio->gpodr, 0x00200000);
+	out_be32(&pgpio->gpdat, 0x00000000);
+	udelay(1000);
+	out_be32(&pgpio->gpdat, 0x00200000);
+	udelay(1000);
+	out_be32(&pgpio->gpdir, 0x00000000);
+#endif
+
+	/* Initialize the DDR3 */
+	sdram_init();
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+			CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}