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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-01-29 18:03:39 +0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-30 09:19:17 -0500 |
| commit | 0f274f5376f02ccf30327bf3e5c88d26d3ea8827 (patch) | |
| tree | c4782c013f59c7a86490048edfdf32d580ca54ce | |
| parent | 2d73f0d6cd42a0ed9a791d665ddbd3d3bf287801 (diff) | |
| download | u-boot-imx-0f274f5376f02ccf30327bf3e5c88d26d3ea8827.zip u-boot-imx-0f274f5376f02ccf30327bf3e5c88d26d3ea8827.tar.gz u-boot-imx-0f274f5376f02ccf30327bf3e5c88d26d3ea8827.tar.bz2 | |
ARM: armv7 fix spelling of SCTRL
SCTLR is the abbreviation of System Control Register, so we should
use SCTLR but not SCTRL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/cpu.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 01cdb7e..c56417d 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -53,7 +53,7 @@ int cleanup_before_linux(void) * After D-cache is flushed and before it is disabled there may * be some new valid entries brought into the cache. We are sure * that these lines are not dirty and will not affect our execution. - * (because unwinding the call-stack and setting a bit in CP15 SCTRL + * (because unwinding the call-stack and setting a bit in CP15 SCTLR * is all we did during this. We have not pushed anything on to the * stack. Neither have we affected any static data) * So just invalidate the entire d-cache again to avoid coherency diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index fdc05b9..70048c1 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -52,10 +52,10 @@ reset: * Continue to use ROM code vector only in OMAP4 spl) */ #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) - /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ - mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register + /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register bic r0, #CR_V @ V = 0 - mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register + mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register /* Set vector address in CP15 VBAR register */ ldr r0, =_start |