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authorVolodymyr Riazantsev <volodymyr.riazantsev@globallogic.com>2015-01-20 10:16:44 -0500
committerYork Sun <yorksun@freescale.com>2015-02-24 13:11:10 -0800
commit0e1bf614d5045b060db8e1bf9e7f69afdf1c592f (patch)
tree159ede2b603a11e20cfd667f9712137839a6bb7a
parent8133574ea4769806145a8fd49fc0567db86583a8 (diff)
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mmc: fsl_esdhc: Add support for DDR mode
Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--drivers/mmc/fsl_esdhc.c8
-rw-r--r--include/configs/mx6_common.h2
-rw-r--r--include/fsl_esdhc.h1
3 files changed, 9 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c55eb28..f5d2ccb 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
esdhc_write32(&regs->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
esdhc_write32(&regs->mixctrl,
- (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+ (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
#else
esdhc_write32(&regs->xfertyp, xfertyp);
@@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
if ((sdhc_clk / (div * pre_div)) <= clock)
break;
- pre_div >>= 1;
+ pre_div >>= mmc->ddr_mode ? 2 : 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
@@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
}
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+ cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+#endif
if (cfg->max_bus_width > 0) {
if (cfg->max_bus_width < 8)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index e0528ce..29b72b2 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -28,6 +28,8 @@
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
#define CONFIG_MP
#define CONFIG_MXC_GPT_HCLK
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index c1b6648..313fa1e 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -108,6 +108,7 @@
#define XFERTYP_RSPTYP_48_BUSY 0x00030000
#define XFERTYP_MSBSEL 0x00000020
#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDREN 0x00000008
#define XFERTYP_AC12EN 0x00000004
#define XFERTYP_BCEN 0x00000002
#define XFERTYP_DMAEN 0x00000001