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| author | Mike Frysinger <vapier@gentoo.org> | 2010-12-24 18:21:53 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-04-08 00:44:26 -0400 |
| commit | 0807fe0a4986aa594d29ccea6a821d9c73b6f57a (patch) | |
| tree | ed4a80d6669f50f3950dbed678ab2f5211c50833 | |
| parent | cca07417d594fcae589463d1678d639810f986cd (diff) | |
| download | u-boot-imx-0807fe0a4986aa594d29ccea6a821d9c73b6f57a.zip u-boot-imx-0807fe0a4986aa594d29ccea6a821d9c73b6f57a.tar.gz u-boot-imx-0807fe0a4986aa594d29ccea6a821d9c73b6f57a.tar.bz2 | |
Blackfin: drop duplicate system mmr and L1 scratch defines
Common code already takes care of setting up these defines when a port
hasn't specified them, so punt the duplicate values.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
7 files changed, 1 insertions, 42 deletions
diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_def.h b/arch/blackfin/include/asm/mach-bf518/BF512_def.h index abc88ca..bbaf22f 100644 --- a/arch/blackfin/include/asm/mach-bf518/BF512_def.h +++ b/arch/blackfin/include/asm/mach-bf518/BF512_def.h @@ -513,11 +513,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF512_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h index 5d61972..3b61aaf 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_def.h @@ -438,12 +438,6 @@ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif #endif /* __BFIN_DEF_ADSP_BF531_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h index f7378b7..64f55f5 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF532_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF532_def.h @@ -12,12 +12,6 @@ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif #endif /* __BFIN_DEF_ADSP_BF532_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h index b77efe0..3c0595f 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF533_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF533_def.h @@ -17,11 +17,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF533_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h index e854eed..c388eef 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF534_def.h +++ b/arch/blackfin/include/asm/mach-bf537/BF534_def.h @@ -21,11 +21,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF534_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_def.h b/arch/blackfin/include/asm/mach-bf538/BF538_def.h index eae8e81..1736dab 100644 --- a/arch/blackfin/include/asm/mach-bf538/BF538_def.h +++ b/arch/blackfin/include/asm/mach-bf538/BF538_def.h @@ -1021,11 +1021,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF538_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index 1aae565..46925f8 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -708,14 +708,9 @@ #define EBIU_SDBCTL 0xFFC00A14 #define EBIU_SDRRC 0xFFC00A18 #define EBIU_SDSTAT 0xFFC00A1C + #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF561_proc__ */ |