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| author | Ed Swarthout <Ed.Swarthout@freescale.com> | 2007-10-19 17:51:40 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-10-24 00:29:23 +0200 |
| commit | cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2 (patch) | |
| tree | 1454ce86f409fc6095722529cae112f45380b428 | |
| parent | e9d0d527992566ebef9826962ff1745b2f082b92 (diff) | |
| download | u-boot-imx-cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2.zip u-boot-imx-cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2.tar.gz u-boot-imx-cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2.tar.bz2 | |
fsl_pci_init enable COMMAND_MEMORY if inbound window
Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows
to pciauto_setup_device has the side effect of not getting
COMMAND_MEMORY set.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| -rw-r--r-- | drivers/fsl_pci_init.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 3a13eea..1e77884 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; + int inbound = 0; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -74,6 +75,7 @@ fsl_pci_init(struct pci_controller *hose) PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | (__ilog2(hose->regions[r].size) - 1); pi++; + inbound = hose->regions[r].size > 0; } else { /* Outbound */ po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; @@ -138,6 +140,12 @@ fsl_pci_init(struct pci_controller *hose) pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + if (inbound) { + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); + pci_hose_write_config_word(hose, dev, PCI_COMMAND, + temp16 | PCI_COMMAND_MEMORY); + } + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); |