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authorTerry Lv <r65388@freescale.com>2010-12-01 17:54:35 +0800
committerTerry Lv <r65388@freescale.com>2010-12-01 18:29:40 +0800
commitd47b8248f35f034ce2491ccc9c96ffd7e45460c9 (patch)
treeaa88c20feb29fb9f4c1f811df24a4ba445fd1c29
parenta3654e9f36d5b9615d9d4953f4e1f50422d04248 (diff)
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ENGR00133744: Merge mx50_arm2 to mx50_rdp
Merge mx50_arm2 to mx50_rdp. Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat
-rw-r--r--Makefile8
-rw-r--r--board/freescale/mx50_arm2/Makefile49
-rw-r--r--board/freescale/mx50_arm2/config.mk7
-rw-r--r--board/freescale/mx50_arm2/flash_header.S1438
-rw-r--r--board/freescale/mx50_arm2/lowlevel_init.S207
-rw-r--r--board/freescale/mx50_arm2/mx50_arm2.c1163
-rw-r--r--board/freescale/mx50_arm2/u-boot.lds73
-rw-r--r--board/freescale/mx50_rdp/flash_header.S1094
-rw-r--r--board/freescale/mx50_rdp/mx50_rdp.c302
-rw-r--r--include/configs/mx50_arm2_ddr2.h2
-rw-r--r--include/configs/mx50_rdp.h1
11 files changed, 1368 insertions, 2976 deletions
diff --git a/Makefile b/Makefile
index c281cdf..228d5e9 100644
--- a/Makefile
+++ b/Makefile
@@ -3252,13 +3252,7 @@ mx50_arm2_lpddr2_config \
mx50_arm2_ddr2_config \
mx50_arm2_iram_config \
mx50_arm2_config \
-mx50_arm2_mfg_config : unconfig
- @[ -z "$(findstring iram_,$@)" ] || \
- { echo "TEXT_BASE = 0xF8008400" >$(obj)board/freescale/mx50_arm2/config.tmp ; \
- echo "... with iram configuration" ; \
- }
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx50_arm2 freescale mx50
-
+mx50_arm2_mfg_config \
mx50_rdp_iram_config \
mx50_rdp_mfg_config \
mx50_rdp_config : unconfig
diff --git a/board/freescale/mx50_arm2/Makefile b/board/freescale/mx50_arm2/Makefile
deleted file mode 100644
index 2bbcde3..0000000
--- a/board/freescale/mx50_arm2/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2010 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx50_arm2.o
-SOBJS := lowlevel_init.o flash_header.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/mx50_arm2/config.mk b/board/freescale/mx50_arm2/config.mk
deleted file mode 100644
index fcb4c00..0000000
--- a/board/freescale/mx50_arm2/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
-
-ifndef TEXT_BASE
- TEXT_BASE = 0x77800000
-endif
diff --git a/board/freescale/mx50_arm2/flash_header.S b/board/freescale/mx50_arm2/flash_header.S
deleted file mode 100644
index 30545a7..0000000
--- a/board/freescale/mx50_arm2/flash_header.S
+++ /dev/null
@@ -1,1438 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx50.h>
-
-#ifdef CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-
-#if defined(CONFIG_ZQ_CALIB)
-.macro do_zq_calib
-/*=============================================================================
- * ZQ calibration
- *===========================================================================*/
- ldr r0, =DATABAHN_BASE_ADDR
-
-/*=============================================================================
- * Pu calibration start
- *===========================================================================*/
- ldr r1, =0x0
-pu_loop:
- cmp r1, #0x20
- beq pu_out
-
- // pu<<16,pd=0
- mov r2, r1, lsl #16
- // Set SW_CFG1
- str r2, [r0, #0x128]
-
- // ((pd+1)<<8) | (pu+1)
- add r1, r1, #0x1
- ldr r2, =0x1
- orr r3, r1, r2, lsl #8
- // Set SW_CFG2
- str r3, [r0, #0x12c]
-
- sub r1, r1, #0x1
-
- // Start ZQ comparator
- ldr r2, =0x10000
- str r2, [r0, #0x124]
-
- // Delay 300ns at least
- ldr r3, =0x0
-pu_delay:
- add r3, r3, #0x1
- cmp r3, #0x1000
- bne pu_delay
-
- // Read compare result
- ldr r3, [r0,#0x14c]
- and r3, r3, #0x1
-
- // Stop ZQ comparator
- ldr r2, =0x0
- str r2, [r0, #0x124]
-
- // Add pu value
- add r1, r1, #0x1
- cmp r3, #0x1
- bne pu_loop
-
-pu_out:
- // Pu calibration result in r1
- sub r1, r1, #0x1
-
-/*=============================================================================
- * PD calibration start
- *===========================================================================*/
- ldr r2, =0x0
-pd_loop:
- cmp r2, #0xf
- beq pd_out
-
- // pd<<24 | pu<<16 | 1<<4
- mov r3, r2, lsl #24
- orr r3, r3, r1, lsl #16
- orr r3, r3, #0x10
- // Set SW_CFG1
- str r3, [r0, #0x128]
-
- // ((pd+1) << 8) | (pu+1)
- add r2, r2, #0x1
- add r1, r1, #0x1
- mov r3, r2, LSL #8
- orr r3, r3, r1
- // Set SW_CFG2
- str r3, [r0, #0x12c]
-
- sub r2, r2, #0x1
- sub r1, r1, #0x1
-
- // Start ZQ comparator
- ldr r3, =0x10000
- str r3, [r0, #0x124]
-
- // Delay 300ns at least
- ldr r3, =0x0
-pd_delay:
- add r3, r3, #0x1
- cmp r3, #0x1000
- bne pd_delay
-
- // Read compare result
- ldr r3, [r0, #0x14c]
- and r3, r3, #0x1
-
- // Stop ZQ comparator
- ldr r8, =0x0
- str r8, [r0, #0x124]
-
- // Add pd value
- add r2, r2, #0x1
-
- cmp r3, #0x0
- bne pd_loop
-
- // Make sure r2 > 0
- cmp r2, #0x0
- beq pd_loop
-
-pd_out:
- // Pd calibration result in r2
- sub r2, r2, #0x2
-
-/*=============================================================================
- * Software load PU/PD value,PU is stored in r1, and PD is stored in r2
- *===========================================================================*/
- /* ((pd + 1) << 24) | ((pu + 1) << 16) */
- add r5, r1, #0x1
- add r6, r2, #0x1
- mov r3, r6, lsl #24
- orr r3, r3, r5, lsl #16
- /* Set SW_CFG1 */
- str r3, [r0, #0x128]
-
- /* (pd << 8) | pu */
- mov r3, r2, lsl #8
- orr r3, r3, r1
- /* Set SW_CFG2 */
- str r3, [r0, #0x12c]
-
- /* Loading PU value, set pu_pd_sel=0 */
- ldr r3, =0x310000
- str r3, [r0, #0x124]
- /* Clear for next load */
- ldr r3, =0x200000
- str r3, [r0, #0x124]
-
- /* Loading PD value, set pu_pd_sel=1 */
- ldr r3, =0x10
- orr r3, r3, r6, lsl #24
- orr r3, r3, r5, lsl #16
- str r3, [r0, #0x128]
-
- ldr r3, =0x310000
- str r3, [r0, #0x124]
- ldr r3, =0x200000
- str r3, [r0, #0x124]
-.endm
-#endif
-
-.section ".text.flasheader", "x"
- b _start
- .org CONFIG_FLASH_HEADER_OFFSET
-
-/* First IVT to copy the plugin that initializes the system into OCRAM */
-ivt_header: .long 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-app_code_jump_v: .long 0xF8006458 /* Plugin entry point */
-reserv1: .long 0x0
-dcd_ptr: .long 0x0
-boot_data_ptr: .long 0xF8006420
-self_ptr: .long 0xF8006400
-app_code_csf: .long 0x0 /* reserve 4K for csf */
-reserv2: .long 0x0
-boot_data: .long 0xF8006000
-image_len: .long 4*1024 /* Can copy upto 72K, OCRAM free space */
-plugin: .long 0x1 /* Enable plugin flag */
-
-/* Second IVT to give entry point into the bootloader copied to DDR */
-ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40
-app2_code_jump_v: .long _start // Entry point for the bootloader
-reserv3: .long 0x0
-dcd2_ptr: .long 0x0
-boot_data2_ptr: .long boot_data2
-self_ptr2: .long ivt2_header
-app_code_csf2: .long 0x0 // reserve 4K for csf
-reserv4: .long 0x0
-boot_data2: .long TEXT_BASE
-image_len2: .long _end - TEXT_BASE
-plugin2: .long 0x0
-
-/*=============================================================================
- * Here starts the plugin code
- *===========================================================================*/
-
-plugin_start:
-
-/* Save the return address and the function arguments */
- push {r0-r6, r8, lr}
-
-/* To return to ROM from plugin, we need to fill in these argument.
- * Here is what need to do:
- * Need to construct the paramters for this function before return to ROM:
- * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
- */
- /* Check r0 if valid address
- * Mfgtools or sb_loader run-plug maybe pass down invalidate data
- */
- cmp r0, #0xf8000000
- mov r4, r0
- ldr r3, DDR_DEST_ADDR
- strhi r3, [r0]
- ldr r3, COPY_SIZE
- strhi r3, [r1]
- ldr r3, IVT2_HDR_OFS
- strhi r3, [r2]
-
-/*=============================================================================
- *init script for codex LPDDR1-200MHz CPU board
- *===========================================================================*/
-
-/* Setup PLL1 to be 800 MHz */
- ldr r0, =CCM_BASE_ADDR
-
-/* Switch ARM domain to be clocked from LP-APM */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
- ldr r0, =PLL1_BASE_ADDR
- ldr r1, =0x1232
- str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
- ldr r1, =0x2
- str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- ldr r1, =DP_OP_800
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, =DP_MFD_800
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, =DP_MFN_800
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- /* Now restart PLL */
- ldr r1, =0x1232
- str r1, [r0, #PLL_DP_CTL]
-wait_pll1_lock:
- ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq wait_pll1_lock
-
-/* Switch ARM back to PLL1 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x0
- str r1, [r0,#CLKCTL_CCSR]
-
-/*=============================================================================
- * Enable all clocks (they are disabled by ROM code)
- *===========================================================================*/
-
- mov r1, #0xffffffff
- str r1, [r0, #0x68]
- str r1, [r0, #0x6c]
- str r1, [r0, #0x70]
- str r1, [r0, #0x74]
- str r1, [r0, #0x78]
- str r1, [r0, #0x7c]
- str r1, [r0, #0x80]
- str r1, [r0, #0x84]
-
-#if defined(CONFIG_LPDDR2)
-
-/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
-/* setmem /32 0x53FD4098 = 0x80000003 */
- ldr r1, =0x80000003
- str r1, [r0, #0x98]
-
-/* poll to make sure DDR dividers take effect */
-1:
- ldr r1, [r0, #0x8c]
- ands r1, r1, #0x4
- bne 1b
-
-/*=============================================================================
- * IOMUX
- *===========================================================================*/
- ldr r0, =0x53fa8000
- mov r1, #0x04000000
- str r1, [r0, #0x6ac]
- ldr r2, =0x00180000
- str r2, [r0, #0x6a4]
- str r2, [r0, #0x668]
- str r2, [r0, #0x698]
- str r2, [r0, #0x6a0]
- str r2, [r0, #0x6a8]
- str r2, [r0, #0x6b4]
- str r2, [r0, #0x498]
- str r2, [r0, #0x49c]
- str r2, [r0, #0x4f0]
- str r2, [r0, #0x500]
- str r2, [r0, #0x4c8]
- str r2, [r0, #0x528]
- str r2, [r0, #0x4f4]
- str r2, [r0, #0x4fc]
- str r2, [r0, #0x4cc]
- str r2, [r0, #0x524]
-
-//*===========================================
-// DDR controller setting
-//*===========================================
-// CTL setting
- ldr r0, =DATABAHN_BASE_ADDR
-
-#if defined(CONFIG_ZQ_CALIB)
- do_zq_calib
-#else
-// setmem /32 0x1400012C = 0x00000817 // pd=<<8, pu=<<0
- ldr r1, =0x00000817
- str r1, [r0, #0x12c]
-// setmem /32 0x14000128 = 0x09180000 // (pd+1)<<24, (pu+1)<<16
- ldr r1, =0x09180000
- str r1, [r0, #0x128]
-// load PU, pu_pd_sel=0
-// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
- ldr r1, =0x00310000
- str r1, [r0, #0x124]
-// setmem /32 0x14000124 = 0x00200000 // clear for next load
- ldr r1, =0x00200000
- str r1, [r0, #0x124]
-// load PD, pu_pd_sel=1
-// setmem /32 0x14000128 = 0x09180010 // (pd+1)<<24, (pu+1)<<16, 1<<4
- ldr r1, =0x09180010
- str r1, [r0, #0x128]
-// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
- ldr r1, =0x00310000
- str r1, [r0, #0x124]
-// setmem /32 0x14000124 = 0x00200000 // clear for next load
- ldr r1, =0x00200000
- str r1, [r0, #0x124]
-#endif
-
-/*=============================================================================
- * DDR setting
- *===========================================================================*/
-
-/* setmem /32 0x14000000 = 0x00000500 */
- ldr r1, =0x00000500
- str r1, [r0, #0x0]
-/* setmem /32 0x14000004 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x4]
-/* setmem /32 0x14000008 = 0x0000001b */
- ldr r1, =0x0000001b
- str r1, [r0, #0x8]
-/* setmem /32 0x1400000c = 0x0000d056 */
- ldr r1, =0x0000d056
- str r1, [r0, #0xc]
-/* setmem /32 0x14000010 = 0x0000010b */
- ldr r1, =0x0000010b
- str r1, [r0, #0x10]
-/* setmem /32 0x14000014 = 0x00000a6b */
- ldr r1, =0x00000a6b
- str r1, [r0, #0x14]
-/* setmem /32 0x14000018 = 0x02020d0c */
- ldr r1, =0x02020d0c
- str r1, [r0, #0x18]
-/* setmem /32 0x1400001c = 0x0c110302 */
- ldr r1, =0x0c110302
- str r1, [r0, #0x1c]
-/* setmem /32 0x14000020 = 0x05020503 */
- ldr r1, =0x05020503
- str r1, [r0, #0x20]
-/* setmem /32 0x14000024 = 0x00000105 */
- ldr r1, =0x00000105
- str r1, [r0, #0x24]
-/* setmem /32 0x14000028 = 0x01000403 */
- ldr r1, =0x01000403
- str r1, [r0, #0x28]
-/* setmem /32 0x1400002c = 0x09040501 */
- ldr r1, =0x09040501
- str r1, [r0, #0x2c]
-/* setmem /32 0x14000030 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x30]
-/* setmem /32 0x14000034 = 0x00000e02 */
- ldr r1, =0x00000e02
- str r1, [r0, #0x34]
-/* setmem /32 0x14000038 = 0x00000006 */
- ldr r1, =0x00000006
- str r1, [r0, #0x38]
-/* setmem /32 0x1400003c = 0x00002301 */
- ldr r1, =0x00002301
- str r1, [r0, #0x3c]
-/* setmem /32 0x14000040 = 0x00050300 */
- ldr r1, =0x00050300
- str r1, [r0, #0x40]
-/* setmem /32 0x14000044 = 0x00000300 */
- ldr r1, =0x00000300
- str r1, [r0, #0x44]
-/* setmem /32 0x14000048 = 0x00260026 */
- ldr r1, =0x00260026
- str r1, [r0, #0x48]
-/* setmem /32 0x1400004c = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x4c]
-/* setmem /32 0x1400005c = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x5c]
-/* setmem /32 0x14000060 = 0x00000002 */
- ldr r1, =0x00000002
- str r1, [r0, #0x60]
-/* setmem /32 0x14000064 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x64]
-/* setmem /32 0x14000068 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x68]
-/* setmem /32 0x1400006c = 0x00040042 */
- ldr r1, =0x00040042
- str r1, [r0, #0x6c]
-/* setmem /32 0x14000070 = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x70]
-/* setmem /32 0x14000074 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x74]
-/* setmem /32 0x14000078 = 0x00040042 */
- ldr r1, =0x00040042
- str r1, [r0, #0x78]
-/* setmem /32 0x1400007c = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x7c]
-/* setmem /32 0x14000080 = 0x010b0000 */
- ldr r1, =0x010b0000
- str r1, [r0, #0x80]
-/* setmem /32 0x14000084 = 0x00000060 */
- ldr r1, =0x00000060
- str r1, [r0, #0x84]
-/* setmem /32 0x14000088 = 0x02400018 */
- ldr r1, =0x02400018
- str r1, [r0, #0x88]
-/* setmem /32 0x1400008c = 0x01000e00 */
- ldr r1, =0x01000e00
- str r1, [r0, #0x8c]
-/* setmem /32 0x14000090 = 0x0a010101 */
- ldr r1, =0x0a010101
- str r1, [r0, #0x90]
-/* setmem /32 0x14000094 = 0x01011f1f */
- ldr r1, =0x01011f1f
- str r1, [r0, #0x94]
-/* setmem /32 0x14000098 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x98]
-/* setmem /32 0x1400009c = 0x00030101 */
- ldr r1, =0x00030101
- str r1, [r0, #0x9c]
-/* setmem /32 0x140000a0 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0xa0]
-/* setmem /32 0x140000a4 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0xa4]
-/* setmem /32 0x140000a8 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xa8]
-/* setmem /32 0x140000ac = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xac]
-/* setmem /32 0x140000c8 = 0x02020101 */
- ldr r1, =0x02020101
- str r1, [r0, #0xc8]
-/* setmem /32 0x140000cc = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0xcc]
-/* setmem /32 0x140000d0 = 0x06060606 */
- ldr r1, =0x06060606
- str r1, [r0, #0xd0]
-/* setmem /32 0x140000d4 = 0x06060606 */
- ldr r1, =0x06060606
- str r1, [r0, #0xd4]
-/* setmem /32 0x140000d8 = 0x00000102 */
- ldr r1, =0x00000102
- str r1, [r0, #0xd8]
-/* setmem /32 0x140000dc = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xdc]
-/* setmem /32 0x140000e0 = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xdc]
-/* setmem /32 0x140000e4 = 0x02020000 */
- ldr r1, =0x02020000
- str r1, [r0, #0xe4]
-/* setmem /32 0x140000e8 = 0x02020202 */
- ldr r1, =0x02020202
- str r1, [r0, #0xe8]
-/* setmem /32 0x140000ec = 0x00000202 */
- ldr r1, =0x00000202
- str r1, [r0, #0xec]
-/* setmem /32 0x140000f0 = 0x01010064 */
- ldr r1, =0x01010064
- str r1, [r0, #0xf0]
-/* setmem /32 0x140000f4 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0xf4]
-/* setmem /32 0x140000f8 = 0x00010101 */
- ldr r1, =0x00010101
- str r1, [r0, #0xf8]
-/* setmem /32 0x140000fc = 0x00000064 */
- ldr r1, =0x00000064
- str r1, [r0, #0xfc]
-/* setmem /32 0x14000100 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x100]
-/* setmem /32 0x14000104 = 0x02000802 */
- ldr r1, =0x02000802
- str r1, [r0, #0x104]
-/* setmem /32 0x14000108 = 0x04080000 */
- ldr r1, =0x04080000
- str r1, [r0, #0x108]
-/* setmem /32 0x1400010c = 0x04080408 */
- ldr r1, =0x04080408
- str r1, [r0, #0x10c]
-/* setmem /32 0x14000110 = 0x04080408 */
- ldr r1, =0x04080408
- str r1, [r0, #0x110]
-/* setmem /32 0x14000114 = 0x03060408 */
- ldr r1, =0x03060408
- str r1, [r0, #0x114]
-/* setmem /32 0x14000118 = 0x01010002 */
- ldr r1, =0x01010002
- str r1, [r0, #0x118]
-/* setmem /32 0x1400011c = 0x00001000 */
- ldr r1, =0x00001000
- str r1, [r0, #0x11c]
-/* setmem /32 0x14000200 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x200]
-/* setmem /32 0x14000204 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x204]
-/* setmem /32 0x14000208 = 0xf5003a27 */
- ldr r1, =0xf5003a27
- str r1, [r0, #0x208]
-/* setmem /32 0x14000210 = 0xf5003a27 */
- str r1, [r0, #0x210]
-/* setmem /32 0x14000218 = 0xf5003a27 */
- str r1, [r0, #0x218]
-/* setmem /32 0x14000220 = 0xf5003a27 */
- str r1, [r0, #0x220]
-/* setmem /32 0x14000228 = 0xf5003a27 */
- str r1, [r0, #0x228]
-/* setmem /32 0x1400020c = 0x074002e1 */
- ldr r1, =0x074002e1
- str r1, [r0, #0x20c]
-/* setmem /32 0x14000214 = 0x074002e1 */
- str r1, [r0, #0x214]
-/* setmem /32 0x1400021c = 0x074002e1 */
- str r1, [r0, #0x21c]
-/* setmem /32 0x14000224 = 0x074002e1 */
- str r1, [r0, #0x224]
-/* setmem /32 0x1400022c = 0x074002e1 */
- str r1, [r0, #0x22c]
-/* setmem /32 0x14000230 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x230]
-/* setmem /32 0x14000234 = 0x00810006 */
- ldr r1, =0x00810006
- str r1, [r0, #0x234]
-/* setmem /32 0x14000238 = 0x20099414 */
- ldr r1, =0x20099414
- str r1, [r0, #0x238]
-/* setmem /32 0x14000240 = 0x20099414 */
- str r1, [r0, #0x240]
-/* setmem /32 0x14000248 = 0x20099414 */
- str r1, [r0, #0x248]
-/* setmem /32 0x14000250 = 0x20099414 */
- str r1, [r0, #0x250]
-/* setmem /32 0x14000258 = 0x20099414 */
- str r1, [r0, #0x258]
-/* setmem /32 0x1400023c = 0x000a0b01 */
- ldr r1, =0x000a0b01
- str r1, [r0, #0x23c]
-/* setmem /32 0x14000244 = 0x000a0b01 */
- str r1, [r0, #0x244]
-/* setmem /32 0x1400024c = 0x000a0b01 */
- str r1, [r0, #0x24c]
-/* setmem /32 0x14000254 = 0x000a0b01 */
- str r1, [r0, #0x254]
-/* setmem /32 0x1400025c = 0x000a0b01 */
- str r1, [r0, #0x25c]
-
-/* Start ddr */
-/* setmem /32 0x14000000 = 0x00000501 // bit[0]: start */
- ldr r1, =0x00000501
- str r1, [r0, #0x0]
-/* poll to make sure it is done */
-1:
- ldr r1, [r0, #0xa8]
- ands r1, r1, #0x10
- beq 1b
-
-#elif defined(CONFIG_DDR2)
-
-/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0xA0000043
- str r1, [r0, #0x94]
-
-/* DDR clock from PLL1 */
- ldr r1, =0x00000803
- str r1, [r0, #0x90]
-
-/* ---------- IOMUX SETUP ---------- */
-/* 0x53fa86ac = 0x02000000 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, ddr_sel=2'b01*/
- ldr r0, =0x53fa8600
- mov r1, #0x02000000
- mov r3, #0x00200000
- mov r2, #0x0
- str r1, [r0, #0xac]
-/* These DSE values seem to make thing work */
-/* 0x53fa86a4 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_CTLDS, dse=3'b100*/
- str r3, [r0, #0xa4]
-/* 0x53fa8668 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_ADDDS, dse=3'b100*/
- str r3, [r0, #0x68]
-/* 0x53fa8698 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B0DS, dse=3'b100*/
- str r3, [r0, #0x98]
-/* 0x53fa86a0 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B1DS, dse=3'b100*/
- str r3, [r0, #0xa0]
-/* 0x53fa86a8 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B2DS, dse=3'b100*/
- str r3, [r0, #0xa8]
-/* 0x53fa86b4 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B3DS, dse=3'b100*/
- str r3, [r0, #0xb4]
-/* 0x53fa8498 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
- ldr r0, =0x53fa8400
- str r3, [r0, #0x98]
-/* 0x53fa849c = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
- str r3, [r0, #0x9c]
-/* 0x53fa84f0 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, dse=3'b100*/
- str r3, [r0, #0xf0]
-/* 0x53fa8500 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, dse=3'b100*/
- ldr r0, =0x53fa8500
- str r3, [r0, #0x00]
-/* 0x53fa84c8 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, dse=3'b100*/
- ldr r0, =0x53fa8400
- str r3, [r0, #0xc8]
-/* 0x53fa8528 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, dse=3'b100*/
- ldr r0, =0x53fa8500
- str r3, [r0, #0x28]
-
-/* 0x53fa84f4 = 0x00200080
- IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, dse=3'b100 , pke=1, pue=1
- */
- ldr r0, =0x53fa8400
- orr r3, r3,#0x00000080
- str r3, [r0, #0xf4]
-
-/* 0x53fa84fc = 0x00200080
- IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, dse=3'b100 , pke=1, pue=1
- */
- str r3, [r0, #0xfc]
-
-/* 0x53fa84cc = 0x00200080
- IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, dse=3'b100 , pke=1, pue=1
- */
- str r3, [r0, #0xcc]
- ldr r0, =0x53fa8500
-
-/* 0x53fa8524 = 0x00200080
- IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, dse=3'b100 , pke=1, pue=1
- */
- str r3, [r0, #0x24]
-
-/* ---------- DDR SETUP ---------- */
-//*===========================================
-// DDR controller setting
-//*===========================================
-// CTL setting
- ldr r0, =DATABAHN_BASE_ADDR
-
-#if defined(CONFIG_ZQ_CALIB)
- do_zq_calib
-#else
-// setmem /32 0x1400012C = 0x00000817 // pd=<<8, pu=<<0
- ldr r1, =0x00000817
- str r1, [r0, #0x12c]
-// setmem /32 0x14000128 = 0x09180000 // (pd+1)<<24, (pu+1)<<16
- ldr r1, =0x09180000
- str r1, [r0, #0x128]
-// load PU, pu_pd_sel=0
-// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
- ldr r1, =0x00310000
- str r1, [r0, #0x124]
-// setmem /32 0x14000124 = 0x00200000 // clear for next load
- ldr r1, =0x00200000
- str r1, [r0, #0x124]
-// load PD, pu_pd_sel=1
-// setmem /32 0x14000128 = 0x09180010 // (pd+1)<<24, (pu+1)<<16, 1<<4
- ldr r1, =0x09180010
- str r1, [r0, #0x128]
-// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
- ldr r1, =0x00310000
- str r1, [r0, #0x124]
-// setmem /32 0x14000124 = 0x00200000 // clear for next load
- ldr r1, =0x00200000
- str r1, [r0, #0x124]
-#endif
-
-/* CTL setting */
-/* setmem /32 0x14000000 = 0x00000400 */
- ldr r1, =0x00000400
- str r1, [r0, #0x0]
-/* setmem /32 0x14000004 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x4]
-/* setmem /32 0x14000008 = 0x0000d056 */
- ldr r1, =0x0000d056
- str r1, [r0, #0x8]
-/* setmem /32 0x1400000c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xc]
-/* setmem /32 0x14000010 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x10]
-/* setmem /32 0x14000014 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x14]
-/* setmem /32 0x14000018 = 0x02030808 */
- ldr r1, =0x02030808
- str r1, [r0, #0x18]
-/* setmem /32 0x1400001c = 0x0c100302 */
- ldr r1, =0x0c100302
- str r1, [r0, #0x1c]
-/* setmem /32 0x14000020 = 0x02020402 */
- ldr r1, =0x02020402
- str r1, [r0, #0x20]
-/* setmem /32 0x14000024 = 0x0048eb04 */
- ldr r1, =0x0048eb04
- str r1, [r0, #0x24]
-/* setmem /32 0x14000028 = 0x01000303 */
- ldr r1, =0x01000303
- str r1, [r0, #0x28]
-/* setmem /32 0x1400002c = 0x08040401 */
- ldr r1, =0x08040401
- str r1, [r0, #0x2c]
-/* setmem /32 0x14000030 = 0x000000c8 */
- ldr r1, =0x000000c8
- str r1, [r0, #0x30]
-/* setmem /32 0x14000034 = 0x006b0c02 */
- ldr r1, =0x006b0c02
- str r1, [r0, #0x34]
-/* setmem /32 0x14000038 = 0x00000005 */
- ldr r1, =0x00000005
- str r1, [r0, #0x38]
-/* setmem /32 0x1400003c = 0x00003401 */
- ldr r1, =0x00003401
- str r1, [r0, #0x3c]
-/* setmem /32 0x14000040 = 0x0005081b */
- ldr r1, =0x0005081b
- str r1, [r0, #0x40]
-/* setmem /32 0x14000044 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x44]
-/* setmem /32 0x14000048 = 0x003700c8 */
- ldr r1, =0x003700c8
- str r1, [r0, #0x48]
-/* setmem /32 0x1400004c = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x4c]
-/* setmem /32 0x14000050 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x50]
-/* setmem /32 0x14000054 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x54]
-/* setmem /32 0x14000058 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x58]
-/* setmem /32 0x1400005c = 0x03000000 */
- ldr r1, =0x03000000
- str r1, [r0, #0x5c]
-/* setmem /32 0x14000060 = 0x00000003 */
- ldr r1, =0x00000003
- str r1, [r0, #0x60]
-/* setmem /32 0x14000064 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x64]
-/* setmem /32 0x14000068 = 0x06420000 */
- ldr r1, =0x06420000
- str r1, [r0, #0x68]
-/* setmem /32 0x1400006c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x6c]
-/* setmem /32 0x14000070 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x70]
-/* setmem /32 0x14000074 = 0x06420000 */
- ldr r1, =0x06420000
- str r1, [r0, #0x74]
-/* setmem /32 0x14000078 = 0x00000004 */
- ldr r1, =0x00000004
- str r1, [r0, #0x78]
-/* setmem /32 0x1400007c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x7c]
-/* setmem /32 0x14000080 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x80]
-/* setmem /32 0x14000084 = 0x00000100 */
- ldr r1, =0x00000100
- str r1, [r0, #0x84]
-/* setmem /32 0x14000088 = 0x02400040 */
- ldr r1, =0x02400040
- str r1, [r0, #0x88]
-/* setmem /32 0x1400008c = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0x8c]
-/* setmem /32 0x14000090 = 0x0a000101 */
- ldr r1, =0x0a000101
- str r1, [r0, #0x90]
-/* setmem /32 0x14000094 = 0x01011f1f */
- ldr r1, =0x01011f1f
- str r1, [r0, #0x94]
-/* setmem /32 0x14000098 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x98]
-/* setmem /32 0x1400009c = 0x00030103 */
- ldr r1, =0x00030103
- str r1, [r0, #0x9c]
-/* setmem /32 0x140000a0 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xa0]
-/* setmem /32 0x140000a4 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0xa4]
-/* setmem /32 0x140000a8 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xa8]
-/* setmem /32 0x140000ac = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xac]
-/* setmem /32 0x140000b0 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xb0]
-/* setmem /32 0x140000b4 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xb4]
-/* setmem /32 0x140000b8 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xb8]
-/* setmem /32 0x140000bc = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xbc]
-/* setmem /32 0x140000c0 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xc0]
-/* setmem /32 0x140000c4 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xc4]
-/* setmem /32 0x140000c8 = 0x02020101 */
- ldr r1, =0x02020101
- str r1, [r0, #0xc8]
-/* setmem /32 0x140000cc = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0xcc]
-/* setmem /32 0x140000d0 = 0x01010201 */
- ldr r1, =0x01010201
- str r1, [r0, #0xd0]
-/* setmem /32 0x140000d4 = 0x00000200 */
- ldr r1, =0x00000200
- str r1, [r0, #0xd4]
-/* setmem /32 0x140000d8 = 0x00000101 */
- ldr r1, =0x00000101
- str r1, [r0, #0xd8]
-/* setmem /32 0x140000dc = 0x0003ffff */
- ldr r1, =0x0003ffff
- str r1, [r0, #0xdc]
-/* setmem /32 0x140000e0 = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xe0]
-/* setmem /32 0x140000e4 = 0x02020000 */
- ldr r1, =0x02020000
- str r1, [r0, #0xe4]
-/* setmem /32 0x140000e8 = 0x02020202 */
- ldr r1, =0x02020202
- str r1, [r0, #0xe8]
-/* setmem /32 0x140000ec = 0x00000202 */
- ldr r1, =0x00000202
- str r1, [r0, #0xec]
-/* setmem /32 0x140000f0 = 0x01010064 */
- ldr r1, =0x01010064
- str r1, [r0, #0xf0]
-/* setmem /32 0x140000f4 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0xf4]
-/* setmem /32 0x140000f8 = 0x00010101 */
- ldr r1, =0x00010101
- str r1, [r0, #0xf8]
-/* setmem /32 0x140000fc = 0x00000064 */
- ldr r1, =0x00000064
- str r1, [r0, #0xfc]
-/* setmem /32 0x14000100 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x100]
-/* setmem /32 0x14000104 = 0x02000702 */
- ldr r1, =0x02000702
- str r1, [r0, #0x104]
-/* setmem /32 0x14000108 = 0x081b0000 */
- ldr r1, =0x081b0000
- str r1, [r0, #0x108]
-/* setmem /32 0x1400010c = 0x081b081b */
- ldr r1, =0x081b081b
- str r1, [r0, #0x10c]
-/* setmem /32 0x14000110 = 0x081b081b */
- ldr r1, =0x081b081b
- str r1, [r0, #0x110]
-/* setmem /32 0x14000114 = 0x0304081b */
- ldr r1, =0x0304081b
- str r1, [r0, #0x114]
-/* setmem /32 0x14000118 = 0x01010002 */
- ldr r1, =0x01010002
- str r1, [r0, #0x118]
-/* setmem /32 0x1400011c = 0x00001000 */
- ldr r1, =0x00001000
- str r1, [r0, #0x11c]
-/* setmem /32 0x14000120 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x120]
-/* setmem /32 0x14000124 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x124]
-/* setmem /32 0x14000128 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x128]
-/* setmem /32 0x1400012c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x12c]
-/* setmem /32 0x14000130 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x130]
-/* setmem /32 0x14000134 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x134]
-/* setmem /32 0x14000138 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x138]
-/* setmem /32 0x1400013c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x13c]
-/* setmem /32 0x14000140 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x140]
-/* setmem /32 0x14000144 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x144]
-/* setmem /32 0x14000148 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x148]
-/* setmem /32 0x1400014c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x14c]
-/* setmem /32 0x14000150 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x150]
-/* setmem /32 0x14000154 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x154]
-/* setmem /32 0x14000158 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x158]
-
-/* PHY setting */
-/* setmem /32 0x14000200 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x200]
-/* setmem /32 0x14000204 = 0x000f1100 */
- ldr r1, =0x000f1100
- str r1, [r0, #0x204]
-/* setmem /32 0x14000208 = 0xf4013a27 */
- ldr r1, =0xf4013a27
- str r1, [r0, #0x208]
-/* setmem /32 0x1400020c = 0x26c002c0 */
- ldr r1, =0x26c002c0
- str r1, [r0, #0x20c]
-/* setmem /32 0x14000210 = 0xf4013a27 */
- ldr r1, =0xf4013a27
- str r1, [r0, #0x210]
-/* setmem /32 0x14000214 = 0x26c002c0 */
- ldr r1, =0x26c002c0
- str r1, [r0, #0x214]
-/* setmem /32 0x14000218 = 0xf4013a27 */
- ldr r1, =0xf4013a27
- str r1, [r0, #0x218]
-/* setmem /32 0x1400021c = 0x26c002c0 */
- ldr r1, =0x26c002c0
- str r1, [r0, #0x21c]
-/* setmem /32 0x14000220 = 0xf4013a27 */
- ldr r1, =0xf4013a27
- str r1, [r0, #0x220]
-/* setmem /32 0x14000224 = 0x26c002c0 */
- ldr r1, =0x26c002c0
- str r1, [r0, #0x224]
-/* setmem /32 0x14000228 = 0xf4013a27 */
- ldr r1, =0xf4013a27
- str r1, [r0, #0x228]
-/* setmem /32 0x1400022c = 0x26c002c0 */
- ldr r1, =0x26c002c0
- str r1, [r0, #0x22c]
-/* setmem /32 0x14000230 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x230]
-/* setmem /32 0x14000234 = 0x00000005 */
- ldr r1, =0x00000005
- str r1, [r0, #0x234]
-/* setmem /32 0x14000238 = 0x20099d14 */
- ldr r1, =0x20099d14
- str r1, [r0, #0x238]
-/* setmem /32 0x1400023c = 0x000a1f01 */
- ldr r1, =0x000a1f01
- str r1, [r0, #0x23c]
-/* setmem /32 0x14000240 = 0x20099d14 */
- ldr r1, =0x20099d14
- str r1, [r0, #0x240]
-/* setmem /32 0x14000244 = 0x000a1f01 */
- ldr r1, =0x000a1f01
- str r1, [r0, #0x244]
-/* setmem /32 0x14000248 = 0x20099d14 */
- ldr r1, =0x20099d14
- str r1, [r0, #0x248]
-/* setmem /32 0x1400024c = 0x000a1f01 */
- ldr r1, =0x000a1f01
- str r1, [r0, #0x24c]
-/* setmem /32 0x14000250 = 0x20099d14 */
- ldr r1, =0x20099d14
- str r1, [r0, #0x250]
-/* setmem /32 0x14000254 = 0x000a1f01 */
- ldr r1, =0x000a1f01
- str r1, [r0, #0x254]
-/* setmem /32 0x14000258 = 0x20099d14 */
- ldr r1, =0x20099d14
- str r1, [r0, #0x258]
-/* setmem /32 0x1400025c = 0x000a1f01 */
- ldr r1, =0x000a1f01
- str r1, [r0, #0x25c]
-
-/* Start ddr */
-/* setmem /32 0x14000000 = 0x00000401 // bit[0]: start */
- ldr r1, =0x00000401
- str r1, [r0, #0x0]
-
-/* poll to make sure it is done */
-1:
- ldr r1, [r0, #0xa8]
- ands r1, r1, #0x10
- beq 1b
-
-#else
-
-/*==================================================================
- * lpddr1-mddr
- *=================================================================*/
-
-/* DDR clock setting -- Set DDR to be div 4 to get 200MHz */
-/* setmem /32 0x53FD4098 = 0x80000004 */
- ldr r1, =0x80000004
- str r1, [r0, #0x98]
-
-/* poll to make sure DDR dividers take effect */
-1:
- ldr r1, [r0, #0x8c]
- ands r1, r1, #0x4
- bne 1b
-
-/*==================================================================
- * IOMUX
- *=================================================================*/
- ldr r0, =0x53fa8600
- mov r1, #0x00000000
- mov r3, #0x00380000
- mov r2, #0x0
- str r1, [r0, #0xac]
- str r2, [r0, #0x6c]
- str r2, [r0, #0x8c]
- str r2, [r0, #0x70]
- str r3, [r0, #0xa4]
- str r3, [r0, #0x68]
- str r3, [r0, #0x98]
- str r3, [r0, #0xa0]
- str r3, [r0, #0xa8]
- str r3, [r0, #0xb4]
-
- ldr r0, =0x53fa8400
- str r3, [r0, #0x98]
- str r3, [r0, #0x9c]
- str r3, [r0, #0xf0]
- str r3, [r0, #0x100]
- str r3, [r0, #0xc8]
- str r3, [r0, #0x128]
- str r3, [r0, #0xf4]
- str r3, [r0, #0xfc]
- str r3, [r0, #0xcc]
- str r3, [r0, #0x124]
-
-//*===========================================
-// DDR controller setting
-//*===========================================
-// CTL setting
- ldr r0, =DATABAHN_BASE_ADDR
-
-#if defined(CONFIG_ZQ_CALIB)
- do_zq_calib
-#else
-// setmem /32 0x1400012C = 0x00000817 // pd=<<8, pu=<<0
- ldr r1, =0x00000817
- str r1, [r0, #0x12c]
-// setmem /32 0x14000128 = 0x09180000 // (pd+1)<<24, (pu+1)<<16
- ldr r1, =0x09180000
- str r1, [r0, #0x128]
-// load PU, pu_pd_sel=0
-// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
- ldr r1, =0x00310000
- str r1, [r0, #0x124]
-// setmem /32 0x14000124 = 0x00200000 // clear for next load
- ldr r1, =0x00200000
- str r1, [r0, #0x124]
-// load PD, pu_pd_sel=1
-// setmem /32 0x14000128 = 0x09180010 // (pd+1)<<24, (pu+1)<<16, 1<<4
- ldr r1, =0x09180010
- str r1, [r0, #0x128]
-// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
- ldr r1, =0x00310000
- str r1, [r0, #0x124]
-// setmem /32 0x14000124 = 0x00200000 // clear for next load
- ldr r1, =0x00200000
- str r1, [r0, #0x124]
-#endif
-
-/*==============================================================
- * DDR setting
- *=============================================================*/
-/* setmem /32 0x14000000 = 0x00000100 */
- ldr r1, =0x00000100
- str r1, [r0, #0x0]
-/* setmem /32 0x14000008 = 0x00009c40 */
- ldr r1, =0x00009c40
- str r1, [r0, #0x8]
-/* setmem /32 0x14000014 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x14]
-/* setmem /32 0x14000018 = 0x01010706 */
- ldr r1, =0x01010706
- str r1, [r0, #0x018]
-/* setmem /32 0x1400001c = 0x080b0201 */
- ldr r1, =0x080b0201
- str r1, [r0, #0x01c]
-/* setmem /32 0x14000020 = 0x02000303 */
- ldr r1, =0x02000303
- str r1, [r0, #0x020]
-/* setmem /32 0x14000024 = 0x0136b002 */
- ldr r1, =0x0136b002
- str r1, [r0, #0x024]
-/* setmem /32 0x14000028 = 0x01000101 */
- ldr r1, =0x01000101
- str r1, [r0, #0x028]
-/* setmem /32 0x1400002c = 0x06030301 */
- ldr r1, =0x06030301
- str r1, [r0, #0x02c]
-/* setmem /32 0x14000030 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x030]
-/* setmem /32 0x14000034 = 0x00000a02 */
- ldr r1, =0x00000a02
- str r1, [r0, #0x034]
-/* setmem /32 0x14000038 = 0x00000003 */
- ldr r1, =0x00000003
- str r1, [r0, #0x038]
-/* setmem /32 0x1400003c = 0x00001401 */
- ldr r1, =0x00001401
- str r1, [r0, #0x03c]
-/* setmem /32 0x14000040 = 0x0005030f */
- ldr r1, =0x0005030f
- str r1, [r0, #0x040]
-/* setmem /32 0x14000044 = 0x00000200 */
- ldr r1, =0x00000200
- str r1, [r0, #0x044]
-/* setmem /32 0x14000048 = 0x00180018 */
- ldr r1, =0x00180018
- str r1, [r0, #0x048]
-/* setmem /32 0x1400004c = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x04c]
-/* setmem /32 0x1400005c = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0x05c]
-/* setmem /32 0x14000060 = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x060]
-/* setmem /32 0x14000064 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x064]
-/* setmem /32 0x14000068 = 0x00320000 */
- ldr r1, =0x00320000
- str r1, [r0, #0x068]
-/* setmem /32 0x1400006c = 0x00800000 */
- ldr r1, =0x00800000
- str r1, [r0, #0x06c]
-/* setmem /32 0x14000070 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x070]
-/* setmem /32 0x14000074 = 0x00320000 */
- ldr r1, =0x00320000
- str r1, [r0, #0x074]
-/* setmem /32 0x14000080 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x080]
-/* setmem /32 0x14000084 = 0x00000100 */
- ldr r1, =0x00000100
- str r1, [r0, #0x084]
-/* setmem /32 0x14000088 = 0x02400040 */
- ldr r1, =0x02400040
- str r1, [r0, #0x088]
-/* setmem /32 0x1400008c = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0x08c]
-/* setmem /32 0x14000090 = 0x0a000100 */
- ldr r1, =0x0a000100
- str r1, [r0, #0x090]
-/* setmem /32 0x14000094 = 0x01011f1f */
- ldr r1, =0x01011f1f
- str r1, [r0, #0x094]
-/* setmem /32 0x14000098 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x098]
-/* setmem /32 0x1400009c = 0x00030101 */
- ldr r1, =0x00030101
- str r1, [r0, #0x09c]
-/* setmem /32 0x140000a4 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x0a4]
-/* setmem /32 0x140000ac = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0x0ac]
-/* setmem /32 0x140000c8 = 0x02020101 */
- ldr r1, =0x02020101
- str r1, [r0, #0x0c8]
-/* setmem /32 0x140000cc = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x0cc]
-/* setmem /32 0x140000d0 = 0x01000202 */
- ldr r1, =0x01000202
- str r1, [r0, #0x0d0]
-/* setmem /32 0x140000d4 = 0x02030302 */
- ldr r1, =0x02030302
- str r1, [r0, #0x0d4]
-/* setmem /32 0x140000d8 = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x0d8]
-/* setmem /32 0x140000dc = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0x0dc]
-/* setmem /32 0x140000e0 = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0x0e0]
-/* setmem /32 0x140000e4 = 0x02020000 */
- ldr r1, =0x02020000
- str r1, [r0, #0x0e4]
-/* setmem /32 0x140000e8 = 0x02020202 */
- ldr r1, =0x02020202
- str r1, [r0, #0x0e8]
-/* setmem /32 0x140000ec = 0x00000202 */
- ldr r1, =0x00000202
- str r1, [r0, #0x0ec]
-/* setmem /32 0x140000f0 = 0x01010064 */
- ldr r1, =0x01010064
- str r1, [r0, #0x0f0]
-/* setmem /32 0x140000f4 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x0f4]
-/* setmem /32 0x140000f8 = 0x00010101 */
- ldr r1, =0x00010101
- str r1, [r0, #0x0f8]
-/* setmem /32 0x140000fc = 0x00000064 */
- ldr r1, =0x00000064
- str r1, [r0, #0x0fc]
-/* setmem /32 0x14000104 = 0x02000602 */
- ldr r1, =0x02000602
- str r1, [r0, #0x0104]
-/* setmem /32 0x14000108 = 0x06120000 */
- ldr r1, =0x06120000
- str r1, [r0, #0x0108]
-/* setmem /32 0x1400010c = 0x06120612 */
- ldr r1, =0x06120612
- str r1, [r0, #0x010c]
-/* setmem /32 0x14000110 = 0x06120612 */
- ldr r1, =0x06120612
- str r1, [r0, #0x0110]
-/* setmem /32 0x14000114 = 0x01030612 */
- ldr r1, =0x01030612
- str r1, [r0, #0x0114]
-/* setmem /32 0x14000118 = 0x01010002 */
- ldr r1, =0x01010002
- str r1, [r0, #0x0118]
-
-/*=============================================================
- * DDR PHY setting
- *===========================================================*/
-
-/* setmem /32 0x14000200 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x200]
-/* setmem /32 0x14000204 = 0x00000000 */
- str r1, [r0, #0x0204]
-/* setmem /32 0x14000208 = 0xf5002725 */
- ldr r1, =0xf5002725
- str r1, [r0, #0x0208]
-/* setmem /32 0x14000210 = 0xf5002725 */
- str r1, [r0, #0x210]
-/* setmem /32 0x14000218 = 0xf5002725 */
- str r1, [r0, #0x218]
-/* setmem /32 0x14000220 = 0xf5002725 */
- str r1, [r0, #0x0220]
-/* setmem /32 0x14000228 = 0xf5002725 */
- str r1, [r0, #0x0228]
-/* setmem /32 0x14000234 = 0x00800006*/
- ldr r1, =0x00800006
- str r1, [r0, #0x0234]
-/* setmem /32 0x1400020c = 0x070002d0 */
- ldr r1, =0x070002d0
- str r1, [r0, #0x020c]
-/* setmem /32 0x14000214 = 0x074002d0 */
- str r1, [r0, #0x0214]
-/* setmem /32 0x1400021c = 0x074002d0 */
- str r1, [r0, #0x021c]
-/* setmem /32 0x14000224 = 0x074002d0 */
- str r1, [r0, #0x0224]
-/* setmem /32 0x1400022c = 0x074002d0 */
- str r1, [r0, #0x022c]
-/* setmem /32 0x14000230 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x0230]
-/* setmem /32 0x14000238 = 0x200e1014 */
- ldr r1, =0x200e1014
- str r1, [r0, #0x0238]
-/* setmem /32 0x14000240 = 0x200e1014 */
- str r1, [r0, #0x0240]
-/* setmem /32 0x14000248 = 0x200e1014 */
- str r1, [r0, #0x0248]
-/* setmem /32 0x14000250 = 0x200e1014 */
- str r1, [r0, #0x0250]
-/* setmem /32 0x14000258 = 0x200e1014 */
- str r1, [r0, #0x0258]
-/* setmem /32 0x1400023c = 0x000d9f01 */
- ldr r1, =0x000d9f01
- str r1, [r0, #0x023c]
-/* setmem /32 0x14000244 = 0x000d9f01 */
- str r1, [r0, #0x0244]
-/* setmem /32 0x1400024c = 0x000d9f01 */
- str r1, [r0, #0x024c]
-/* setmem /32 0x14000254 = 0x000d9f01 */
- str r1, [r0, #0x0254]
-/* setmem /32 0x1400025c = 0x000d9f01 */
- str r1, [r0, #0x025c]
-
-/* Start ddr */
-/* setmem /32 0x14000000 = 0x00000101 // bit[0]: start */
- ldr r1, =0x00000101
- str r1, [r0, #0x0]
-/* poll to make sure it is done */
-1:
- ldr r1, [r0, #0xa8]
- ands r1, r1, #0x10
- beq 1b
-
-#endif
-
-/*
- * The following is to fill in those arguments for this ROM function
- * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
- *
- * This function is used to copy data from the storage media into DDR.
-
- * start - Initial (possibly partial) image load address on entry.
- * Final image load address on exit.
- * bytes - Initial (possibly partial) image size on entry.
- * Final image size on exit.
- * boot_data - Initial @ref ivt Boot Data load address.
- */
-
- ldr r0, =ROM_SI_REV
- ldr r1, [r0]
- cmp r1, #0x11
-
- adr r0, DDR_DEST_ADDR
- adr r1, COPY_SIZE
- adr r2, BOOT_DATA
-
-before_calling_rom___pu_irom_hwcnfg_setup:
- mov r3, #0x2a00
- /* Different ROM address for TO 1.0 & TO 1.1.1 */
- addeq r3, r3, #0xad
- addne r3, r3, #0x19
- cmp r4, #0xf8000000
- blxhi r3
-after_calling_rom___pu_irom_hwcnfg_setup:
-
- pop {r0-r6, r8, lr}
- mov r0, #1
- bx lr /* return back to ROM code */
-
-DDR_DEST_ADDR: .word TEXT_BASE
-COPY_SIZE: .word _end - TEXT_BASE
-BOOT_DATA: .word TEXT_BASE
- .word _end - TEXT_BASE /*data be copied by pu_irom_hwcnfg_setup()*/
- .word 0
-IVT2_HDR_OFS: .word ivt2_header - TEXT_BASE
-
-#endif
diff --git a/board/freescale/mx50_arm2/lowlevel_init.S b/board/freescale/mx50_arm2/lowlevel_init.S
deleted file mode 100644
index 4e031c7..0000000
--- a/board/freescale/mx50_arm2/lowlevel_init.S
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx50.h>
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
-.endm /* init_aips */
-
-.macro setup_pll pll, freq
- ldr r0, =\pll
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
- mov r1, #0x2
- str r1, [r0, #PLL_DP_CONFIG]
-
- ldr r1, W_DP_OP_\freq
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, W_DP_MFD_\freq
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, W_DP_MFN_\freq
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
-1: ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-.macro init_clock
-
- setup_pll PLL3_BASE_ADDR, 400
-
- /* Switch peripheral to PLL3 */
- /* Set periph_clk_sel[1:0]=0b10 to PLL3 */
-
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, [r0, #CLKCTL_CBCDR]
- orr r1, r1, #(3 << 25)
- eor r1, r1, #(3 << 25)
- orr r1, r1, #(2 << 25)
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
-
- /* Switch peripheral to PLL2 */
- /* Set periph_clk_sel[1:0]=0b01 to PLL2 */
-
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, [r0, #CLKCTL_CBCDR]
- orr r1, r1, #(3 << 25)
- eor r1, r1, #(3 << 25)
- orr r1, r1, #(1 << 25)
-
- orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
- orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
- orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL3_BASE_ADDR, 216
-
- /* Set the platform clock dividers */
- ldr r0, PLATFORM_BASE_ADDR_W
- ldr r1, PLATFORM_CLOCK_DIV_W
- str r1, [r0, #PLATFORM_ICGC]
-
- /* ARM2 run at full speed */
- ldr r0, CCM_BASE_ADDR_W
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
- str r1, [r0, #CLKCTL_CCGR7]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
- /* ARM errata ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-
- init_l2cc
-
- init_aips
-
- init_clock /* not finished */
-
- mov pc, lr
-
-/* Board level setting value */
-CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_600: .word DP_OP_600
-W_DP_MFD_600: .word DP_MFD_600
-W_DP_MFN_600: .word DP_MFN_600
-W_DP_OP_400: .word DP_OP_400
-W_DP_MFD_400: .word DP_MFD_400
-W_DP_MFN_400: .word DP_MFN_400
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
-PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W: .word 0x00000124
diff --git a/board/freescale/mx50_arm2/mx50_arm2.c b/board/freescale/mx50_arm2/mx50_arm2.c
deleted file mode 100644
index 08e8051..0000000
--- a/board/freescale/mx50_arm2/mx50_arm2.c
+++ /dev/null
@@ -1,1163 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx50.h>
-#include <asm/arch/mx50_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/errno.h>
-
-#ifdef CONFIG_IMX_CSPI
-#include <imx_spi.h>
-#include <asm/arch/imx_spi_pmic.h>
-#endif
-
-#if CONFIG_I2C_MXC
-#include <i2c.h>
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-#ifdef CONFIG_CMD_CLOCK
-#include <asm/clock.h>
-#endif
-
-#ifdef CONFIG_MXC_EPDC
-#include <lcd.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-static enum boot_device boot_dev;
-u32 mx51_io_base_addr;
-
-static inline void setup_boot_device(void)
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
- uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
-
- switch (bt_mem_ctl) {
- case 0x0:
- if (bt_mem_type)
- boot_dev = ONE_NAND_BOOT;
- else
- boot_dev = WEIM_NOR_BOOT;
- break;
- case 0x2:
- if (bt_mem_type)
- boot_dev = SATA_BOOT;
- else
- boot_dev = PATA_BOOT;
- break;
- case 0x3:
- if (bt_mem_type)
- boot_dev = SPI_NOR_BOOT;
- else
- boot_dev = I2C_BOOT;
- break;
- case 0x4:
- case 0x5:
- boot_dev = SD_BOOT;
- break;
- case 0x6:
- case 0x7:
- boot_dev = MMC_BOOT;
- break;
- case 0x8 ... 0xf:
- boot_dev = NAND_BOOT;
- break;
- default:
- boot_dev = UNKNOWN_BOOT;
- break;
- }
-}
-
-enum boot_device get_boot_device(void)
-{
- return boot_dev;
-}
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- int reg = __REG(ROM_SI_REV);
-
- switch (reg) {
- case 0x10:
- system_rev = 0x50000 | CHIP_REV_1_0;
- break;
- case 0x11:
- system_rev = 0x50000 | CHIP_REV_1_1_1;
- break;
- default:
- system_rev = 0x50000 | CHIP_REV_1_1_1;
- }
-}
-
-static inline void setup_board_rev(int rev)
-{
- system_rev |= (rev & 0xF) << 8;
-}
-
-inline int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
- unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
- unsigned long i;
-
- /*
- * Set the TTB register
- */
- asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
-
- /*
- * Set the Domain Access Control Register
- */
- i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
-
- /*
- * First clear all TT entries - ie Set them to Faulting
- */
- memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
- /* Base Base MB cached? buffered? access permissions */
- /* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
- X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IRAM */
- X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SATA */
- X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
- X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* GPU */
- X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* periperals */
- X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
- X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* iRam */
-
- /* Workaround for arm errata #709718 */
- /* Setup PRRR so device is always mapped to non-shared */
- asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
- i &= (~(3 << 0x10));
- asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
-
- /* Enable MMU */
- MMU_ON();
-}
-#endif
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-static void setup_uart(void)
-{
-
- /* UART1 RXD */
- mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4);
- mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_UART1_TXD, 0x1E4);
-}
-
-#ifdef CONFIG_I2C_MXC
-static void setup_i2c(unsigned int module_base)
-{
- switch (module_base) {
- case I2C1_BASE_ADDR:
- /* i2c1 SDA */
- mxc_request_iomux(MX50_PIN_I2C1_SDA,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- /* i2c1 SCL */
- mxc_request_iomux(MX50_PIN_I2C1_SCL,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- case I2C2_BASE_ADDR:
- /* i2c2 SDA */
- mxc_request_iomux(MX50_PIN_I2C2_SDA,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C2_SDA,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
-
- /* i2c2 SCL */
- mxc_request_iomux(MX50_PIN_I2C2_SCL,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C2_SCL,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- case I2C3_BASE_ADDR:
- /* i2c3 SDA */
- mxc_request_iomux(MX50_PIN_I2C3_SDA,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C3_SDA,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
-
- /* i2c3 SCL */
- mxc_request_iomux(MX50_PIN_I2C3_SCL,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C3_SCL,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- default:
- printf("Invalid I2C base: 0x%x\n", module_base);
- break;
- }
-}
-
-#endif
-
-#ifdef CONFIG_IMX_CSPI
-s32 spi_get_cfg(struct imx_spi_dev_t *dev)
-{
- switch (dev->slave.cs) {
- case 0:
- /* PMIC */
- dev->base = CSPI3_BASE_ADDR;
- dev->freq = 25000000;
- dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
- dev->ss = 0;
- dev->fifo_sz = 32;
- dev->us_delay = 0;
- break;
- case 1:
- /* SPI-NOR */
- dev->base = CSPI3_BASE_ADDR;
- dev->freq = 25000000;
- dev->ss_pol = IMX_SPI_ACTIVE_LOW;
- dev->ss = 1;
- dev->fifo_sz = 32;
- dev->us_delay = 0;
- break;
- default:
- printf("Invalid Bus ID! \n");
- }
-
- return 0;
-}
-
-void spi_io_init(struct imx_spi_dev_t *dev)
-{
- switch (dev->base) {
- case CSPI3_BASE_ADDR:
- mxc_request_iomux(MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_MOSI, 0x4);
-
- mxc_request_iomux(MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_MISO, 0x4);
-
- if (dev->ss == 0) {
- /* de-select SS1 of instance: cspi */
- mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
- IOMUX_CONFIG_ALT1);
-
- mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_SS0, 0xE4);
- } else if (dev->ss == 1) {
- /* de-select SS0 of instance: cspi */
- mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT1);
-
- mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
- IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_ECSPI1_MOSI, 0xE4);
- mxc_iomux_set_input(
- MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, 0x1);
- }
-
- mxc_request_iomux(MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_SCLK, 0x4);
- break;
- case CSPI2_BASE_ADDR:
- case CSPI1_BASE_ADDR:
- /* ecspi1-2 fall through */
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_NAND_GPMI
-void setup_gpmi_nand(void)
-{
- u32 src_sbmr = readl(SRC_BASE_ADDR + 0x4);
-
- /* Fix for gpmi gatelevel issue */
- mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0x00e4);
-
- /* RESETN,WRN,RDN,DATA0~7 Signals iomux*/
- /* Check if 1.8v NAND is to be supported */
- if ((src_sbmr & 0x00000004) >> 2)
- *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x58) = (0x1 << 13);
-
- /* RESETN */
- mxc_request_iomux(MX50_PIN_SD3_WP, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_WP, PAD_CTL_DRV_HIGH);
-
- /* WRN */
- mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_CMD, PAD_CTL_DRV_HIGH);
-
- /* RDN */
- mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_CLK, PAD_CTL_DRV_HIGH);
-
- /* D0 */
- mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D4, PAD_CTL_DRV_HIGH);
-
- /* D1 */
- mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D5, PAD_CTL_DRV_HIGH);
-
- /* D2 */
- mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D6, PAD_CTL_DRV_HIGH);
-
- /* D3 */
- mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D7, PAD_CTL_DRV_HIGH);
-
- /* D4 */
- mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D0, PAD_CTL_DRV_HIGH);
-
- /* D5 */
- mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D1, PAD_CTL_DRV_HIGH);
-
- /* D6 */
- mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D2, PAD_CTL_DRV_HIGH);
-
- /* D7 */
- mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_SD3_D3, PAD_CTL_DRV_HIGH);
-
- /*CE0~3,and other four controls signals muxed on KPP*/
- switch ((src_sbmr & 0x00000018) >> 3) {
- case 0:
- /* Muxed on key */
- if ((src_sbmr & 0x00000004) >> 2)
- *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x20) =
- (0x1 << 13);
-
- /* CLE */
- mxc_request_iomux(MX50_PIN_KEY_COL0, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_COL0, PAD_CTL_DRV_HIGH);
-
- /* ALE */
- mxc_request_iomux(MX50_PIN_KEY_ROW0, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_ROW0, PAD_CTL_DRV_HIGH);
-
- /* READY0 */
- mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_COL3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
- PAD_CTL_100K_PU);
- mxc_iomux_set_input(MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
-
- /* DQS */
- mxc_request_iomux(MX50_PIN_KEY_ROW3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_ROW3, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_input(MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
-
- /* CE0 */
- mxc_request_iomux(MX50_PIN_KEY_COL1, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_COL1, PAD_CTL_DRV_HIGH);
-
- /* CE1 */
- mxc_request_iomux(MX50_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_ROW1, PAD_CTL_DRV_HIGH);
-
- /* CE2 */
- mxc_request_iomux(MX50_PIN_KEY_COL2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_COL2, PAD_CTL_DRV_HIGH);
-
- /* CE3 */
- mxc_request_iomux(MX50_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
-
- break;
- case 1:
- if ((src_sbmr & 0x00000004) >> 2)
- *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0xc) =
- (0x1 << 13);
-
- /* CLE */
- mxc_request_iomux(MX50_PIN_EIM_DA8, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA8, PAD_CTL_DRV_HIGH);
-
- /* ALE */
- mxc_request_iomux(MX50_PIN_EIM_DA9, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA9, PAD_CTL_DRV_HIGH);
-
- /* READY0 */
- mxc_request_iomux(MX50_PIN_EIM_DA14, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA14,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
- PAD_CTL_100K_PU);
- mxc_iomux_set_input(MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
- INPUT_CTL_PATH2);
-
- /* DQS */
- mxc_request_iomux(MX50_PIN_EIM_DA15, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA15, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_input(MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
- INPUT_CTL_PATH2);
-
- /* CE0 */
- mxc_request_iomux(MX50_PIN_EIM_DA10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA10, PAD_CTL_DRV_HIGH);
-
- /* CE1 */
- mxc_request_iomux(MX50_PIN_EIM_DA11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA11, PAD_CTL_DRV_HIGH);
-
- /* CE2 */
- mxc_request_iomux(MX50_PIN_EIM_DA12, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA12, PAD_CTL_DRV_HIGH);
-
- /* CE3 */
- mxc_request_iomux(MX50_PIN_EIM_DA13, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA13, PAD_CTL_DRV_HIGH);
-
- break;
- case 2:
- if ((src_sbmr & 0x00000004) >> 2)
- *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x48) =
- (0x1 << 13);
-
- /* CLE */
- mxc_request_iomux(MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D8, PAD_CTL_DRV_HIGH);
-
- /* ALE */
- mxc_request_iomux(MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D9, PAD_CTL_DRV_HIGH);
-
- /* READY0 */
- mxc_request_iomux(MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D14,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
- PAD_CTL_100K_PU);
- mxc_iomux_set_input(MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
- INPUT_CTL_PATH1);
-
- /* DQS */
- mxc_request_iomux(MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D15, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_input(MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
- INPUT_CTL_PATH1);
-
- /* CE0 */
- mxc_request_iomux(MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D10, PAD_CTL_DRV_HIGH);
-
- /* CE1 */
- mxc_request_iomux(MX50_PIN_EIM_DA11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_EIM_DA11, PAD_CTL_DRV_HIGH);
-
- /* CE2 */
- mxc_request_iomux(MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D12, PAD_CTL_DRV_HIGH);
-
- /* CE3 */
- mxc_request_iomux(MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D13, PAD_CTL_DRV_HIGH);
-
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_MXC_FEC
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-
-#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10)
-
-int fec_get_mac_addr(unsigned char *mac)
-{
- u32 *ocotp_mac_base =
- (u32 *)(OCOTP_CTRL_BASE_ADDR + HW_OCOTP_MACn(0));
- int i;
-
- for (i = 0; i < 6; ++i, ++ocotp_mac_base)
- mac[6 - 1 - i] = readl(++ocotp_mac_base);
-
- return 0;
-}
-#endif
-
-static void setup_fec(void)
-{
- volatile unsigned int reg;
-
- /*FEC_MDIO*/
- mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX50_PIN_SSI_RXC, 0xC);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX50_PIN_SSI_RXFS, 0x004);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D3, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, 0x0);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D4, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, 0x0);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D6, 0x004);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D7, 0x004);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D5, 0x004);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D0, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, 0x0);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D1, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, 0);
-
- /* FEC CRS */
- mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0);
-
- /* phy reset: gpio4-6 */
- mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
-
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg &= ~0x40;
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-
- reg = readl(GPIO4_BASE_ADDR + 0x4);
- reg |= 0x40;
- writel(reg, GPIO4_BASE_ADDR + 0x4);
-
- udelay(500);
-
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg |= 0x40;
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[3] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
- {MMC_SDHC2_BASE_ADDR, 1, 1},
- {MMC_SDHC3_BASE_ADDR, 1, 1},
-};
-
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno(void)
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- int mmc_devno = 0;
-
- switch (soc_sbmr & 0x00300000) {
- default:
- case 0x0:
- mmc_devno = 0;
- break;
- case 0x00100000:
- mmc_devno = 1;
- break;
- case 0x00200000:
- mmc_devno = 2;
- break;
- }
-
- return mmc_devno;
-}
-#endif
-
-
-int esdhc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX50_PIN_SD1_CMD, 0x1E4);
- mxc_iomux_set_pad(MX50_PIN_SD1_CLK, 0xD4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D0, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D1, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D2, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D3, 0x1D4);
-
- break;
- case 1:
- mxc_request_iomux(MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX50_PIN_SD2_CMD, 0x14);
- mxc_iomux_set_pad(MX50_PIN_SD2_CLK, 0xD4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D0, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D1, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D2, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D3, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D4, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D5, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D6, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D7, 0x1D4);
-
- break;
- case 2:
-#ifndef CONFIG_NAND_GPMI
- mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX50_PIN_SD3_CMD, 0x1E4);
- mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0xD4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D0, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D1, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D2, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D3, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D4, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D5, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D6, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D7, 0x1D4);
-#endif
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-
-#endif
-
-#ifdef CONFIG_MXC_EPDC
-#ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
-{
-#ifdef CONFIG_SPLASH_IS_IN_MMC
- int mmc_dev = get_mmc_env_devno();
- ulong offset = CONFIG_SPLASH_IMG_OFFSET;
- ulong size = CONFIG_SPLASH_IMG_SIZE;
- ulong addr = 0;
- char *s = NULL;
- struct mmc *mmc = find_mmc_device(mmc_dev);
- uint blk_start, blk_cnt, n;
-
- s = getenv("splashimage");
-
- if (NULL == s) {
- puts("env splashimage not found!\n");
- return -1;
- }
- addr = simple_strtoul(s, NULL, 16);
-
- if (!mmc) {
- printf("MMC Device %d not found\n",
- mmc_dev);
- return -1;
- }
-
- if (mmc_init(mmc)) {
- puts("MMC init failed\n");
- return -1;
- }
-
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(mmc_dev, blk_start,
- blk_cnt, (u_char *)addr);
- flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
-
- return (n == blk_cnt) ? 0 : -1;
-#endif
-}
-#endif
-
-vidinfo_t panel_info = {
- .vl_refresh = 60,
- .vl_col = 800,
- .vl_row = 600,
- .vl_pixclock = 17700000,
- .vl_left_margin = 8,
- .vl_right_margin = 142,
- .vl_upper_margin = 4,
- .vl_lower_margin = 10,
- .vl_hsync = 20,
- .vl_vsync = 4,
- .vl_sync = 0,
- .vl_mode = 0,
- .vl_flag = 0,
- .vl_bpix = 3,
- cmap:0,
-};
-
-static void setup_epdc_power()
-{
- unsigned int reg;
-
- /* Setup epdc voltage */
-
- /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
- mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
-
- /* EPDC VCOM0 - GPIO4[21] for VCOM control */
- mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
- /* Set as output */
- reg = readl(GPIO4_BASE_ADDR + 0x4);
- reg |= (1 << 21);
- writel(reg, GPIO4_BASE_ADDR + 0x4);
-
- /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
- mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
- /* Set as output */
- reg = readl(GPIO6_BASE_ADDR + 0x4);
- reg |= (1 << 16);
- writel(reg, GPIO6_BASE_ADDR + 0x4);
-}
-
-void epdc_power_on()
-{
- unsigned int reg;
-
- /* Set PMIC Wakeup to high - enable Display power */
- reg = readl(GPIO6_BASE_ADDR + 0x0);
- reg |= (1 << 16);
- writel(reg, GPIO6_BASE_ADDR + 0x0);
-
- /* Wait for PWRGOOD == 1 */
- while (1) {
- reg = readl(GPIO3_BASE_ADDR + 0x0);
- if (!(reg & (1 << 28)))
- break;
-
- udelay(100);
- }
-
- /* Enable VCOM */
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg |= (1 << 21);
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-
- reg = readl(GPIO4_BASE_ADDR + 0x0);
-
- udelay(500);
-}
-
-void epdc_power_off()
-{
- unsigned int reg;
- /* Set PMIC Wakeup to low - disable Display power */
- reg = readl(GPIO6_BASE_ADDR + 0x0);
- reg |= 0 << 16;
- writel(reg, GPIO6_BASE_ADDR + 0x0);
-
- /* Disable VCOM */
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg |= 0 << 21;
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-}
-
-int setup_waveform_file()
-{
-#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
- int mmc_dev = get_mmc_env_devno();
- ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
- ulong size = CONFIG_WAVEFORM_FILE_SIZE;
- ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
- char *s = NULL;
- struct mmc *mmc = find_mmc_device(mmc_dev);
- uint blk_start, blk_cnt, n;
-
- if (!mmc) {
- printf("MMC Device %d not found\n",
- mmc_dev);
- return -1;
- }
-
- if (mmc_init(mmc)) {
- puts("MMC init failed\n");
- return -1;
- }
-
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(mmc_dev, blk_start,
- blk_cnt, (u_char *)addr);
- flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
-
- return (n == blk_cnt) ? 0 : -1;
-#else
- return -1;
-#endif
-}
-
-static void setup_epdc()
-{
- unsigned int reg;
-
- /* epdc iomux settings */
- mxc_request_iomux(MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0);
-
-
- /*** epdc Maxim PMIC settings ***/
-
- /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
- mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
-
- /* EPDC VCOM0 - GPIO4[21] for VCOM control */
- mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
-
- /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
- mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
-
-
- /*** Set pixel clock rates for EPDC ***/
-
- /* EPDC AXI clk and EPDC PIX clk from PLL1 */
- reg = readl(CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
- reg &= ~(0x3 << 4);
- reg |= (0x2 << 4) | (0x2 << 12);
- writel(reg, CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
-
- /* EPDC AXI clk enable and set to 200MHz (800/4) */
- reg = readl(CCM_BASE_ADDR + 0xA8);
- reg &= ~((0x3 << 30) | 0x3F);
- reg |= (0x2 << 30) | 0x4;
- writel(reg, CCM_BASE_ADDR + 0xA8);
-
- /* EPDC PIX clk enable and set to 20MHz (800/40) */
- reg = readl(CCM_BASE_ADDR + 0xA0);
- reg &= ~((0x3 << 30) | (0x3 << 12) | 0x3F);
- reg |= (0x2 << 30) | (0x1 << 12) | 0x2D;
- writel(reg, CCM_BASE_ADDR + 0xA0);
-
- panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
- panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
-
- panel_info.epdc_data.wv_modes.mode_init = 0;
- panel_info.epdc_data.wv_modes.mode_du = 1;
- panel_info.epdc_data.wv_modes.mode_gc4 = 3;
- panel_info.epdc_data.wv_modes.mode_gc8 = 2;
- panel_info.epdc_data.wv_modes.mode_gc16 = 2;
- panel_info.epdc_data.wv_modes.mode_gc32 = 2;
-
- setup_epdc_power();
-
- /* Assign fb_base */
- gd->fb_base = CONFIG_FB_BASE;
-}
-#endif
-
-#ifdef CONFIG_IMX_CSPI
-static void setup_power(void)
-{
- struct spi_slave *slave;
- unsigned int val;
-
- puts("PMIC Mode: SPI\n");
-
- /* Enable VGEN1 to enable ethernet */
- slave = spi_pmic_probe();
-
- val = pmic_reg(slave, 30, 0, 0);
- val |= 0x3;
- pmic_reg(slave, 30, val, 1);
-
- val = pmic_reg(slave, 32, 0, 0);
- val |= 0x1;
- pmic_reg(slave, 32, val, 1);
-
- /* Enable VCAM */
- val = pmic_reg(slave, 33, 0, 0);
- val |= 0x40;
- pmic_reg(slave, 33, val, 1);
-
- spi_pmic_free(slave);
-}
-
-void setup_voltage_cpu(void)
-{
- /* Currently VDDGP 1.05v
- * no one tell me we need increase the core
- * voltage to let CPU run at 800Mhz, not do it
- */
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
-
-}
-#endif
-
-int board_init(void)
-{
-#ifdef CONFIG_MFG
-/* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x140
- int val = readl(OTG_BASE_ADDR + USBCMD);
- val &= ~0x1; /*RS bit*/
- writel(val, OTG_BASE_ADDR + USBCMD);
-#endif
- /* boot device */
- setup_boot_device();
-
- /* soc rev */
- setup_soc_rev();
-
- /* arch id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2;
-
- /* boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* iomux for uart */
- setup_uart();
-
-#ifdef CONFIG_MXC_FEC
- /* iomux for fec */
- setup_fec();
-#endif
-
-#ifdef CONFIG_NAND_GPMI
- setup_gpmi_nand();
-#endif
-
-#ifdef CONFIG_MXC_EPDC
- setup_epdc();
-#endif
-
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_IMX_CSPI
- setup_power();
-#endif
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX50 ARM2 board\n");
-
- printf("Boot Reason: [");
-
- switch (__REG(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- printf("POR");
- break;
- case 0x0009:
- printf("RST");
- break;
- case 0x0010:
- case 0x0011:
- printf("WDOG");
- break;
- default:
- printf("unknown");
- }
- printf("]\n");
-
- printf("Boot Device: ");
- switch (get_boot_device()) {
- case WEIM_NOR_BOOT:
- printf("NOR\n");
- break;
- case ONE_NAND_BOOT:
- printf("ONE NAND\n");
- break;
- case PATA_BOOT:
- printf("PATA\n");
- break;
- case SATA_BOOT:
- printf("SATA\n");
- break;
- case I2C_BOOT:
- printf("I2C\n");
- break;
- case SPI_NOR_BOOT:
- printf("SPI NOR\n");
- break;
- case SD_BOOT:
- printf("SD\n");
- break;
- case MMC_BOOT:
- printf("MMC\n");
- break;
- case NAND_BOOT:
- printf("NAND\n");
- break;
- case UNKNOWN_BOOT:
- default:
- printf("UNKNOWN\n");
- break;
- }
-
- return 0;
-}
diff --git a/board/freescale/mx50_arm2/u-boot.lds b/board/freescale/mx50_arm2/u-boot.lds
deleted file mode 100644
index 07478dd..0000000
--- a/board/freescale/mx50_arm2/u-boot.lds
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- board/freescale/mx50_arm2/flash_header.o (.text.flasheader)
- cpu/arm_cortexa8/start.o
- board/freescale/mx50_arm2/libmx50_arm2.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
- drivers/mmc/libmmc.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/board/freescale/mx50_rdp/flash_header.S b/board/freescale/mx50_rdp/flash_header.S
index 7a547d9..98eb3eb 100644
--- a/board/freescale/mx50_rdp/flash_header.S
+++ b/board/freescale/mx50_rdp/flash_header.S
@@ -213,6 +213,7 @@ plugin2: .long 0x0
*===========================================================================*/
plugin_start:
+
/* Save the return address and the function arguments */
push {r0-r6, r8, lr}
@@ -289,6 +290,8 @@ wait_pll1_lock:
str r1, [r0, #0x80]
str r1, [r0, #0x84]
+#if defined(CONFIG_LPDDR2)
+
/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
/* setmem /32 0x53FD4098 = 0x80000003 */
ldr r1, =0x80000003
@@ -303,63 +306,64 @@ wait_pll1_lock:
/*=============================================================================
* IOMUX
*===========================================================================*/
- ldr r0, =0x53fa8600
- mov r1, #0x04000000
- ldr r3, =0x00180000
- mov r2, #0x0
+ ldr r0, =0x53fa8600
+ mov r1, #0x04000000
+ ldr r3, =0x00180000
+ mov r2, #0x0
//setmem /32 0x53fa86ac = 0x04000000
//IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, ddr_sel=2'b01 (LPDDR2)
- str r1, [r0, #0xac]
+ str r1, [r0, #0xac]
//setmem /32 0x53fa86a4 = 0x00180000
//IOMUXC_SW_PAD_CTL_GRP_CTLDS, dse=3'b100
- str r3, [r0, #0xa4]
+ str r3, [r0, #0xa4]
//setmem /32 0x53fa8668 = 0x00180000
//IOMUXC_SW_PAD_CTL_GRP_ADDDS, dse=3'b100
- str r3, [r0, #0x68]
+ str r3, [r0, #0x68]
//setmem /32 0x53fa8698 = 0x00180000
//IOMUXC_SW_PAD_CTL_GRP_B0DS, dse=3'b100
- str r3, [r0, #0x98]
+ str r3, [r0, #0x98]
//setmem /32 0x53fa86a0 = 0x00180000
//IOMUXC_SW_PAD_CTL_GRP_B1DS, dse=3'b100
- str r3, [r0, #0xa0]
+ str r3, [r0, #0xa0]
//setmem /32 0x53fa86a8 = 0x00180000
//IOMUXC_SW_PAD_CTL_GRP_B2DS, dse=3'b100
- str r3, [r0, #0xa8]
+ str r3, [r0, #0xa8]
//setmem /32 0x53fa86b4 = 0x00180000
//IOMUXC_SW_PAD_CTL_GRP_B3DS, dse=3'b100
- str r3, [r0, #0xb4]
+ str r3, [r0, #0xb4]
- ldr r0, =0x53fa8400
+ ldr r0, =0x53fa8400
//setmem /32 0x53fa8498 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
- str r3, [r0, #0x98]
+ str r3, [r0, #0x98]
//setmem /32 0x53fa849c = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
- str r3, [r0, #0x9c]
+ str r3, [r0, #0x9c]
//setmem /32 0x53fa84f0 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, dse=3'b100
- str r3, [r0, #0xf0]
+ str r3, [r0, #0xf0]
//setmem /32 0x53fa8500 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, dse=3'b100
- str r3, [r0, #0x100]
+ str r3, [r0, #0x100]
//setmem /32 0x53fa84c8 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, dse=3'b100
- str r3, [r0, #0xc8]
+ str r3, [r0, #0xc8]
//setmem /32 0x53fa8528 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, dse=3'b100
- str r3, [r0, #0x128]
+ str r3, [r0, #0x128]
//setmem /32 0x53fa84f4 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, dse=3'b100
- str r3, [r0, #0xf4]
+ str r3, [r0, #0xf4]
//setmem /32 0x53fa84fc = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, dse=3'b100
- str r3, [r0, #0xfc]
+ str r3, [r0, #0xfc]
//setmem /32 0x53fa84cc = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, dse=3'b100
- str r3, [r0, #0xcc]
+ str r3, [r0, #0xcc]
//setmem /32 0x53fa8524 = 0x00180000
//IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, dse=3'b100
- str r3, [r0, #0x124]
+ str r3, [r0, #0x124]
+
//*===========================================
// DDR controller setting
@@ -395,6 +399,12 @@ wait_pll1_lock:
str r1, [r0, #0x124]
#endif
+#if defined(CONFIG_MX50_RDP)
+
+/*===========================================================================
+ * DDR setting
+ *===========================================================================*/
+
//setmem /32 0x14000000 = 0x00000500
ldr r1, =0x00000500
str r1, [r0, #0x0]
@@ -701,19 +711,1044 @@ wait_pll1_lock:
ldr r1, =0x000a0b01
str r1, [r0, #0x25c]
+#elif defined(CONFIG_MX50_ARM2)
-//*===================================
-// Start ddr init sequence
-//*===================================
-//setmem /32 0x14000000 = 0x00000501 // bit[0]: start
- ldr r1, =0x00000501
- str r1, [r0, #0x0]
+/*=============================================================================
+ * DDR setting
+ *===========================================================================*/
+
+/* setmem /32 0x14000000 = 0x00000500 */
+ ldr r1, =0x00000500
+ str r1, [r0, #0x0]
+/* setmem /32 0x14000004 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x4]
+/* setmem /32 0x14000008 = 0x0000001b */
+ ldr r1, =0x0000001b
+ str r1, [r0, #0x8]
+/* setmem /32 0x1400000c = 0x0000d056 */
+ ldr r1, =0x0000d056
+ str r1, [r0, #0xc]
+/* setmem /32 0x14000010 = 0x0000010b */
+ ldr r1, =0x0000010b
+ str r1, [r0, #0x10]
+/* setmem /32 0x14000014 = 0x00000a6b */
+ ldr r1, =0x00000a6b
+ str r1, [r0, #0x14]
+/* setmem /32 0x14000018 = 0x02020d0c */
+ ldr r1, =0x02020d0c
+ str r1, [r0, #0x18]
+/* setmem /32 0x1400001c = 0x0c110302 */
+ ldr r1, =0x0c110302
+ str r1, [r0, #0x1c]
+/* setmem /32 0x14000020 = 0x05020503 */
+ ldr r1, =0x05020503
+ str r1, [r0, #0x20]
+/* setmem /32 0x14000024 = 0x00000105 */
+ ldr r1, =0x00000105
+ str r1, [r0, #0x24]
+/* setmem /32 0x14000028 = 0x01000403 */
+ ldr r1, =0x01000403
+ str r1, [r0, #0x28]
+/* setmem /32 0x1400002c = 0x09040501 */
+ ldr r1, =0x09040501
+ str r1, [r0, #0x2c]
+/* setmem /32 0x14000030 = 0x02000000 */
+ ldr r1, =0x02000000
+ str r1, [r0, #0x30]
+/* setmem /32 0x14000034 = 0x00000e02 */
+ ldr r1, =0x00000e02
+ str r1, [r0, #0x34]
+/* setmem /32 0x14000038 = 0x00000006 */
+ ldr r1, =0x00000006
+ str r1, [r0, #0x38]
+/* setmem /32 0x1400003c = 0x00002301 */
+ ldr r1, =0x00002301
+ str r1, [r0, #0x3c]
+/* setmem /32 0x14000040 = 0x00050300 */
+ ldr r1, =0x00050300
+ str r1, [r0, #0x40]
+/* setmem /32 0x14000044 = 0x00000300 */
+ ldr r1, =0x00000300
+ str r1, [r0, #0x44]
+/* setmem /32 0x14000048 = 0x00260026 */
+ ldr r1, =0x00260026
+ str r1, [r0, #0x48]
+/* setmem /32 0x1400004c = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0x4c]
+/* setmem /32 0x1400005c = 0x02000000 */
+ ldr r1, =0x02000000
+ str r1, [r0, #0x5c]
+/* setmem /32 0x14000060 = 0x00000002 */
+ ldr r1, =0x00000002
+ str r1, [r0, #0x60]
+/* setmem /32 0x14000064 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x64]
+/* setmem /32 0x14000068 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x68]
+/* setmem /32 0x1400006c = 0x00040042 */
+ ldr r1, =0x00040042
+ str r1, [r0, #0x6c]
+/* setmem /32 0x14000070 = 0x00000001 */
+ ldr r1, =0x00000001
+ str r1, [r0, #0x70]
+/* setmem /32 0x14000074 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x74]
+/* setmem /32 0x14000078 = 0x00040042 */
+ ldr r1, =0x00040042
+ str r1, [r0, #0x78]
+/* setmem /32 0x1400007c = 0x00000001 */
+ ldr r1, =0x00000001
+ str r1, [r0, #0x7c]
+/* setmem /32 0x14000080 = 0x010b0000 */
+ ldr r1, =0x010b0000
+ str r1, [r0, #0x80]
+/* setmem /32 0x14000084 = 0x00000060 */
+ ldr r1, =0x00000060
+ str r1, [r0, #0x84]
+/* setmem /32 0x14000088 = 0x02400018 */
+ ldr r1, =0x02400018
+ str r1, [r0, #0x88]
+/* setmem /32 0x1400008c = 0x01000e00 */
+ ldr r1, =0x01000e00
+ str r1, [r0, #0x8c]
+/* setmem /32 0x14000090 = 0x0a010101 */
+ ldr r1, =0x0a010101
+ str r1, [r0, #0x90]
+/* setmem /32 0x14000094 = 0x01011f1f */
+ ldr r1, =0x01011f1f
+ str r1, [r0, #0x94]
+/* setmem /32 0x14000098 = 0x01010101 */
+ ldr r1, =0x01010101
+ str r1, [r0, #0x98]
+/* setmem /32 0x1400009c = 0x00030101 */
+ ldr r1, =0x00030101
+ str r1, [r0, #0x9c]
+/* setmem /32 0x140000a0 = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0xa0]
+/* setmem /32 0x140000a4 = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0xa4]
+/* setmem /32 0x140000a8 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xa8]
+/* setmem /32 0x140000ac = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0xac]
+/* setmem /32 0x140000c8 = 0x02020101 */
+ ldr r1, =0x02020101
+ str r1, [r0, #0xc8]
+/* setmem /32 0x140000cc = 0x01000000 */
+ ldr r1, =0x01000000
+ str r1, [r0, #0xcc]
+/* setmem /32 0x140000d0 = 0x06060606 */
+ ldr r1, =0x06060606
+ str r1, [r0, #0xd0]
+/* setmem /32 0x140000d4 = 0x06060606 */
+ ldr r1, =0x06060606
+ str r1, [r0, #0xd4]
+/* setmem /32 0x140000d8 = 0x00000102 */
+ ldr r1, =0x00000102
+ str r1, [r0, #0xd8]
+/* setmem /32 0x140000dc = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0xdc]
+/* setmem /32 0x140000e0 = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0xdc]
+/* setmem /32 0x140000e4 = 0x02020000 */
+ ldr r1, =0x02020000
+ str r1, [r0, #0xe4]
+/* setmem /32 0x140000e8 = 0x02020202 */
+ ldr r1, =0x02020202
+ str r1, [r0, #0xe8]
+/* setmem /32 0x140000ec = 0x00000202 */
+ ldr r1, =0x00000202
+ str r1, [r0, #0xec]
+/* setmem /32 0x140000f0 = 0x01010064 */
+ ldr r1, =0x01010064
+ str r1, [r0, #0xf0]
+/* setmem /32 0x140000f4 = 0x01010101 */
+ ldr r1, =0x01010101
+ str r1, [r0, #0xf4]
+/* setmem /32 0x140000f8 = 0x00010101 */
+ ldr r1, =0x00010101
+ str r1, [r0, #0xf8]
+/* setmem /32 0x140000fc = 0x00000064 */
+ ldr r1, =0x00000064
+ str r1, [r0, #0xfc]
+/* setmem /32 0x14000100 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x100]
+/* setmem /32 0x14000104 = 0x02000802 */
+ ldr r1, =0x02000802
+ str r1, [r0, #0x104]
+/* setmem /32 0x14000108 = 0x04080000 */
+ ldr r1, =0x04080000
+ str r1, [r0, #0x108]
+/* setmem /32 0x1400010c = 0x04080408 */
+ ldr r1, =0x04080408
+ str r1, [r0, #0x10c]
+/* setmem /32 0x14000110 = 0x04080408 */
+ ldr r1, =0x04080408
+ str r1, [r0, #0x110]
+/* setmem /32 0x14000114 = 0x03060408 */
+ ldr r1, =0x03060408
+ str r1, [r0, #0x114]
+/* setmem /32 0x14000118 = 0x01010002 */
+ ldr r1, =0x01010002
+ str r1, [r0, #0x118]
+/* setmem /32 0x1400011c = 0x00001000 */
+ ldr r1, =0x00001000
+ str r1, [r0, #0x11c]
+/* setmem /32 0x14000200 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x200]
+/* setmem /32 0x14000204 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x204]
+/* setmem /32 0x14000208 = 0xf5003a27 */
+ ldr r1, =0xf5003a27
+ str r1, [r0, #0x208]
+/* setmem /32 0x14000210 = 0xf5003a27 */
+ str r1, [r0, #0x210]
+/* setmem /32 0x14000218 = 0xf5003a27 */
+ str r1, [r0, #0x218]
+/* setmem /32 0x14000220 = 0xf5003a27 */
+ str r1, [r0, #0x220]
+/* setmem /32 0x14000228 = 0xf5003a27 */
+ str r1, [r0, #0x228]
+/* setmem /32 0x1400020c = 0x074002e1 */
+ ldr r1, =0x074002e1
+ str r1, [r0, #0x20c]
+/* setmem /32 0x14000214 = 0x074002e1 */
+ str r1, [r0, #0x214]
+/* setmem /32 0x1400021c = 0x074002e1 */
+ str r1, [r0, #0x21c]
+/* setmem /32 0x14000224 = 0x074002e1 */
+ str r1, [r0, #0x224]
+/* setmem /32 0x1400022c = 0x074002e1 */
+ str r1, [r0, #0x22c]
+/* setmem /32 0x14000230 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x230]
+/* setmem /32 0x14000234 = 0x00810006 */
+ ldr r1, =0x00810006
+ str r1, [r0, #0x234]
+/* setmem /32 0x14000238 = 0x20099414 */
+ ldr r1, =0x20099414
+ str r1, [r0, #0x238]
+/* setmem /32 0x14000240 = 0x20099414 */
+ str r1, [r0, #0x240]
+/* setmem /32 0x14000248 = 0x20099414 */
+ str r1, [r0, #0x248]
+/* setmem /32 0x14000250 = 0x20099414 */
+ str r1, [r0, #0x250]
+/* setmem /32 0x14000258 = 0x20099414 */
+ str r1, [r0, #0x258]
+/* setmem /32 0x1400023c = 0x000a0b01 */
+ ldr r1, =0x000a0b01
+ str r1, [r0, #0x23c]
+/* setmem /32 0x14000244 = 0x000a0b01 */
+ str r1, [r0, #0x244]
+/* setmem /32 0x1400024c = 0x000a0b01 */
+ str r1, [r0, #0x24c]
+/* setmem /32 0x14000254 = 0x000a0b01 */
+ str r1, [r0, #0x254]
+/* setmem /32 0x1400025c = 0x000a0b01 */
+ str r1, [r0, #0x25c]
+#else
+# error "Unsupported board!"
+#endif
+
+/* Start ddr */
+/* setmem /32 0x14000000 = 0x00000501 // bit[0]: start */
+ ldr r1, =0x00000501
+ str r1, [r0, #0x0]
+/* poll to make sure it is done */
+1:
+ ldr r1, [r0, #0xa8]
+ ands r1, r1, #0x10
+ beq 1b
+
+#elif defined(CONFIG_DDR2)
+
+/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0xA0000043
+ str r1, [r0, #0x94]
+
+/* DDR clock from PLL1 */
+ ldr r1, =0x00000803
+ str r1, [r0, #0x90]
+
+/* ---------- IOMUX SETUP ---------- */
+/* 0x53fa86ac = 0x02000000 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, ddr_sel=2'b01*/
+ ldr r0, =0x53fa8600
+ mov r1, #0x02000000
+ mov r3, #0x00200000
+ mov r2, #0x0
+ str r1, [r0, #0xac]
+/* These DSE values seem to make thing work */
+/* 0x53fa86a4 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_CTLDS, dse=3'b100*/
+ str r3, [r0, #0xa4]
+/* 0x53fa8668 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_ADDDS, dse=3'b100*/
+ str r3, [r0, #0x68]
+/* 0x53fa8698 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B0DS, dse=3'b100*/
+ str r3, [r0, #0x98]
+/* 0x53fa86a0 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B1DS, dse=3'b100*/
+ str r3, [r0, #0xa0]
+/* 0x53fa86a8 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B2DS, dse=3'b100*/
+ str r3, [r0, #0xa8]
+/* 0x53fa86b4 = 0x00200000 IOMUXC_SW_PAD_CTL_GRP_B3DS, dse=3'b100*/
+ str r3, [r0, #0xb4]
+/* 0x53fa8498 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
+ ldr r0, =0x53fa8400
+ str r3, [r0, #0x98]
+/* 0x53fa849c = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
+ str r3, [r0, #0x9c]
+/* 0x53fa84f0 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, dse=3'b100*/
+ str r3, [r0, #0xf0]
+/* 0x53fa8500 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, dse=3'b100*/
+ ldr r0, =0x53fa8500
+ str r3, [r0, #0x00]
+/* 0x53fa84c8 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, dse=3'b100*/
+ ldr r0, =0x53fa8400
+ str r3, [r0, #0xc8]
+/* 0x53fa8528 = 0x00200000 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, dse=3'b100*/
+ ldr r0, =0x53fa8500
+ str r3, [r0, #0x28]
+
+/* 0x53fa84f4 = 0x00200080
+ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, dse=3'b100 , pke=1, pue=1
+ */
+ ldr r0, =0x53fa8400
+ orr r3, r3,#0x00000080
+ str r3, [r0, #0xf4]
+
+/* 0x53fa84fc = 0x00200080
+ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, dse=3'b100 , pke=1, pue=1
+ */
+ str r3, [r0, #0xfc]
+
+/* 0x53fa84cc = 0x00200080
+ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, dse=3'b100 , pke=1, pue=1
+ */
+ str r3, [r0, #0xcc]
+ ldr r0, =0x53fa8500
+
+/* 0x53fa8524 = 0x00200080
+ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, dse=3'b100 , pke=1, pue=1
+ */
+ str r3, [r0, #0x24]
+
+/* ---------- DDR SETUP ---------- */
+//*===========================================
+// DDR controller setting
+//*===========================================
+// CTL setting
+ ldr r0, =DATABAHN_BASE_ADDR
+
+#if defined(CONFIG_ZQ_CALIB)
+ do_zq_calib
+#else
+// setmem /32 0x1400012C = 0x00000817 // pd=<<8, pu=<<0
+ ldr r1, =0x00000817
+ str r1, [r0, #0x12c]
+// setmem /32 0x14000128 = 0x09180000 // (pd+1)<<24, (pu+1)<<16
+ ldr r1, =0x09180000
+ str r1, [r0, #0x128]
+// load PU, pu_pd_sel=0
+// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
+ ldr r1, =0x00310000
+ str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000 // clear for next load
+ ldr r1, =0x00200000
+ str r1, [r0, #0x124]
+// load PD, pu_pd_sel=1
+// setmem /32 0x14000128 = 0x09180010 // (pd+1)<<24, (pu+1)<<16, 1<<4
+ ldr r1, =0x09180010
+ str r1, [r0, #0x128]
+// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
+ ldr r1, =0x00310000
+ str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000 // clear for next load
+ ldr r1, =0x00200000
+ str r1, [r0, #0x124]
+#endif
+
+/* CTL setting */
+/* setmem /32 0x14000000 = 0x00000400 */
+ ldr r1, =0x00000400
+ str r1, [r0, #0x0]
+/* setmem /32 0x14000004 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x4]
+/* setmem /32 0x14000008 = 0x0000d056 */
+ ldr r1, =0x0000d056
+ str r1, [r0, #0x8]
+/* setmem /32 0x1400000c = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xc]
+/* setmem /32 0x14000010 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x10]
+/* setmem /32 0x14000014 = 0x02000000 */
+ ldr r1, =0x02000000
+ str r1, [r0, #0x14]
+/* setmem /32 0x14000018 = 0x02030808 */
+ ldr r1, =0x02030808
+ str r1, [r0, #0x18]
+/* setmem /32 0x1400001c = 0x0c100302 */
+ ldr r1, =0x0c100302
+ str r1, [r0, #0x1c]
+/* setmem /32 0x14000020 = 0x02020402 */
+ ldr r1, =0x02020402
+ str r1, [r0, #0x20]
+/* setmem /32 0x14000024 = 0x0048eb04 */
+ ldr r1, =0x0048eb04
+ str r1, [r0, #0x24]
+/* setmem /32 0x14000028 = 0x01000303 */
+ ldr r1, =0x01000303
+ str r1, [r0, #0x28]
+/* setmem /32 0x1400002c = 0x08040401 */
+ ldr r1, =0x08040401
+ str r1, [r0, #0x2c]
+/* setmem /32 0x14000030 = 0x000000c8 */
+ ldr r1, =0x000000c8
+ str r1, [r0, #0x30]
+/* setmem /32 0x14000034 = 0x006b0c02 */
+ ldr r1, =0x006b0c02
+ str r1, [r0, #0x34]
+/* setmem /32 0x14000038 = 0x00000005 */
+ ldr r1, =0x00000005
+ str r1, [r0, #0x38]
+/* setmem /32 0x1400003c = 0x00003401 */
+ ldr r1, =0x00003401
+ str r1, [r0, #0x3c]
+/* setmem /32 0x14000040 = 0x0005081b */
+ ldr r1, =0x0005081b
+ str r1, [r0, #0x40]
+/* setmem /32 0x14000044 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x44]
+/* setmem /32 0x14000048 = 0x003700c8 */
+ ldr r1, =0x003700c8
+ str r1, [r0, #0x48]
+/* setmem /32 0x1400004c = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0x4c]
+/* setmem /32 0x14000050 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x50]
+/* setmem /32 0x14000054 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x54]
+/* setmem /32 0x14000058 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x58]
+/* setmem /32 0x1400005c = 0x03000000 */
+ ldr r1, =0x03000000
+ str r1, [r0, #0x5c]
+/* setmem /32 0x14000060 = 0x00000003 */
+ ldr r1, =0x00000003
+ str r1, [r0, #0x60]
+/* setmem /32 0x14000064 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x64]
+/* setmem /32 0x14000068 = 0x06420000 */
+ ldr r1, =0x06420000
+ str r1, [r0, #0x68]
+/* setmem /32 0x1400006c = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x6c]
+/* setmem /32 0x14000070 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x70]
+/* setmem /32 0x14000074 = 0x06420000 */
+ ldr r1, =0x06420000
+ str r1, [r0, #0x74]
+/* setmem /32 0x14000078 = 0x00000004 */
+ ldr r1, =0x00000004
+ str r1, [r0, #0x78]
+/* setmem /32 0x1400007c = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x7c]
+/* setmem /32 0x14000080 = 0x02000000 */
+ ldr r1, =0x02000000
+ str r1, [r0, #0x80]
+/* setmem /32 0x14000084 = 0x00000100 */
+ ldr r1, =0x00000100
+ str r1, [r0, #0x84]
+/* setmem /32 0x14000088 = 0x02400040 */
+ ldr r1, =0x02400040
+ str r1, [r0, #0x88]
+/* setmem /32 0x1400008c = 0x01000000 */
+ ldr r1, =0x01000000
+ str r1, [r0, #0x8c]
+/* setmem /32 0x14000090 = 0x0a000101 */
+ ldr r1, =0x0a000101
+ str r1, [r0, #0x90]
+/* setmem /32 0x14000094 = 0x01011f1f */
+ ldr r1, =0x01011f1f
+ str r1, [r0, #0x94]
+/* setmem /32 0x14000098 = 0x01010101 */
+ ldr r1, =0x01010101
+ str r1, [r0, #0x98]
+/* setmem /32 0x1400009c = 0x00030103 */
+ ldr r1, =0x00030103
+ str r1, [r0, #0x9c]
+/* setmem /32 0x140000a0 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xa0]
+/* setmem /32 0x140000a4 = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0xa4]
+/* setmem /32 0x140000a8 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xa8]
+/* setmem /32 0x140000ac = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0xac]
+/* setmem /32 0x140000b0 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xb0]
+/* setmem /32 0x140000b4 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xb4]
+/* setmem /32 0x140000b8 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xb8]
+/* setmem /32 0x140000bc = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xbc]
+/* setmem /32 0x140000c0 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xc0]
+/* setmem /32 0x140000c4 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0xc4]
+/* setmem /32 0x140000c8 = 0x02020101 */
+ ldr r1, =0x02020101
+ str r1, [r0, #0xc8]
+/* setmem /32 0x140000cc = 0x01000000 */
+ ldr r1, =0x01000000
+ str r1, [r0, #0xcc]
+/* setmem /32 0x140000d0 = 0x01010201 */
+ ldr r1, =0x01010201
+ str r1, [r0, #0xd0]
+/* setmem /32 0x140000d4 = 0x00000200 */
+ ldr r1, =0x00000200
+ str r1, [r0, #0xd4]
+/* setmem /32 0x140000d8 = 0x00000101 */
+ ldr r1, =0x00000101
+ str r1, [r0, #0xd8]
+/* setmem /32 0x140000dc = 0x0003ffff */
+ ldr r1, =0x0003ffff
+ str r1, [r0, #0xdc]
+/* setmem /32 0x140000e0 = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0xe0]
+/* setmem /32 0x140000e4 = 0x02020000 */
+ ldr r1, =0x02020000
+ str r1, [r0, #0xe4]
+/* setmem /32 0x140000e8 = 0x02020202 */
+ ldr r1, =0x02020202
+ str r1, [r0, #0xe8]
+/* setmem /32 0x140000ec = 0x00000202 */
+ ldr r1, =0x00000202
+ str r1, [r0, #0xec]
+/* setmem /32 0x140000f0 = 0x01010064 */
+ ldr r1, =0x01010064
+ str r1, [r0, #0xf0]
+/* setmem /32 0x140000f4 = 0x01010101 */
+ ldr r1, =0x01010101
+ str r1, [r0, #0xf4]
+/* setmem /32 0x140000f8 = 0x00010101 */
+ ldr r1, =0x00010101
+ str r1, [r0, #0xf8]
+/* setmem /32 0x140000fc = 0x00000064 */
+ ldr r1, =0x00000064
+ str r1, [r0, #0xfc]
+/* setmem /32 0x14000100 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x100]
+/* setmem /32 0x14000104 = 0x02000702 */
+ ldr r1, =0x02000702
+ str r1, [r0, #0x104]
+/* setmem /32 0x14000108 = 0x081b0000 */
+ ldr r1, =0x081b0000
+ str r1, [r0, #0x108]
+/* setmem /32 0x1400010c = 0x081b081b */
+ ldr r1, =0x081b081b
+ str r1, [r0, #0x10c]
+/* setmem /32 0x14000110 = 0x081b081b */
+ ldr r1, =0x081b081b
+ str r1, [r0, #0x110]
+/* setmem /32 0x14000114 = 0x0304081b */
+ ldr r1, =0x0304081b
+ str r1, [r0, #0x114]
+/* setmem /32 0x14000118 = 0x01010002 */
+ ldr r1, =0x01010002
+ str r1, [r0, #0x118]
+/* setmem /32 0x1400011c = 0x00001000 */
+ ldr r1, =0x00001000
+ str r1, [r0, #0x11c]
+/* setmem /32 0x14000120 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x120]
+/* setmem /32 0x14000124 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x124]
+/* setmem /32 0x14000128 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x128]
+/* setmem /32 0x1400012c = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x12c]
+/* setmem /32 0x14000130 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x130]
+/* setmem /32 0x14000134 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x134]
+/* setmem /32 0x14000138 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x138]
+/* setmem /32 0x1400013c = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x13c]
+/* setmem /32 0x14000140 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x140]
+/* setmem /32 0x14000144 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x144]
+/* setmem /32 0x14000148 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x148]
+/* setmem /32 0x1400014c = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x14c]
+/* setmem /32 0x14000150 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x150]
+/* setmem /32 0x14000154 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x154]
+/* setmem /32 0x14000158 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x158]
+
+/* PHY setting */
+/* setmem /32 0x14000200 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x200]
+/* setmem /32 0x14000204 = 0x000f1100 */
+ ldr r1, =0x000f1100
+ str r1, [r0, #0x204]
+/* setmem /32 0x14000208 = 0xf4013a27 */
+ ldr r1, =0xf4013a27
+ str r1, [r0, #0x208]
+/* setmem /32 0x1400020c = 0x26c002c0 */
+ ldr r1, =0x26c002c0
+ str r1, [r0, #0x20c]
+/* setmem /32 0x14000210 = 0xf4013a27 */
+ ldr r1, =0xf4013a27
+ str r1, [r0, #0x210]
+/* setmem /32 0x14000214 = 0x26c002c0 */
+ ldr r1, =0x26c002c0
+ str r1, [r0, #0x214]
+/* setmem /32 0x14000218 = 0xf4013a27 */
+ ldr r1, =0xf4013a27
+ str r1, [r0, #0x218]
+/* setmem /32 0x1400021c = 0x26c002c0 */
+ ldr r1, =0x26c002c0
+ str r1, [r0, #0x21c]
+/* setmem /32 0x14000220 = 0xf4013a27 */
+ ldr r1, =0xf4013a27
+ str r1, [r0, #0x220]
+/* setmem /32 0x14000224 = 0x26c002c0 */
+ ldr r1, =0x26c002c0
+ str r1, [r0, #0x224]
+/* setmem /32 0x14000228 = 0xf4013a27 */
+ ldr r1, =0xf4013a27
+ str r1, [r0, #0x228]
+/* setmem /32 0x1400022c = 0x26c002c0 */
+ ldr r1, =0x26c002c0
+ str r1, [r0, #0x22c]
+/* setmem /32 0x14000230 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x230]
+/* setmem /32 0x14000234 = 0x00000005 */
+ ldr r1, =0x00000005
+ str r1, [r0, #0x234]
+/* setmem /32 0x14000238 = 0x20099d14 */
+ ldr r1, =0x20099d14
+ str r1, [r0, #0x238]
+/* setmem /32 0x1400023c = 0x000a1f01 */
+ ldr r1, =0x000a1f01
+ str r1, [r0, #0x23c]
+/* setmem /32 0x14000240 = 0x20099d14 */
+ ldr r1, =0x20099d14
+ str r1, [r0, #0x240]
+/* setmem /32 0x14000244 = 0x000a1f01 */
+ ldr r1, =0x000a1f01
+ str r1, [r0, #0x244]
+/* setmem /32 0x14000248 = 0x20099d14 */
+ ldr r1, =0x20099d14
+ str r1, [r0, #0x248]
+/* setmem /32 0x1400024c = 0x000a1f01 */
+ ldr r1, =0x000a1f01
+ str r1, [r0, #0x24c]
+/* setmem /32 0x14000250 = 0x20099d14 */
+ ldr r1, =0x20099d14
+ str r1, [r0, #0x250]
+/* setmem /32 0x14000254 = 0x000a1f01 */
+ ldr r1, =0x000a1f01
+ str r1, [r0, #0x254]
+/* setmem /32 0x14000258 = 0x20099d14 */
+ ldr r1, =0x20099d14
+ str r1, [r0, #0x258]
+/* setmem /32 0x1400025c = 0x000a1f01 */
+ ldr r1, =0x000a1f01
+ str r1, [r0, #0x25c]
+
+/* Start ddr */
+/* setmem /32 0x14000000 = 0x00000401 // bit[0]: start */
+ ldr r1, =0x00000401
+ str r1, [r0, #0x0]
+
+/* poll to make sure it is done */
+1:
+ ldr r1, [r0, #0xa8]
+ ands r1, r1, #0x10
+ beq 1b
+
+#else
+
+/*==================================================================
+ * lpddr1-mddr
+ *=================================================================*/
+
+/* DDR clock setting -- Set DDR to be div 4 to get 200MHz */
+/* setmem /32 0x53FD4098 = 0x80000004 */
+ ldr r1, =0x80000004
+ str r1, [r0, #0x98]
+
+/* poll to make sure DDR dividers take effect */
+1:
+ ldr r1, [r0, #0x8c]
+ ands r1, r1, #0x4
+ bne 1b
+
+/*==================================================================
+ * IOMUX
+ *=================================================================*/
+ ldr r0, =0x53fa8600
+ mov r1, #0x00000000
+ mov r3, #0x00380000
+ mov r2, #0x0
+ str r1, [r0, #0xac]
+ str r2, [r0, #0x6c]
+ str r2, [r0, #0x8c]
+ str r2, [r0, #0x70]
+ str r3, [r0, #0xa4]
+ str r3, [r0, #0x68]
+ str r3, [r0, #0x98]
+ str r3, [r0, #0xa0]
+ str r3, [r0, #0xa8]
+ str r3, [r0, #0xb4]
+
+ ldr r0, =0x53fa8400
+ str r3, [r0, #0x98]
+ str r3, [r0, #0x9c]
+ str r3, [r0, #0xf0]
+ str r3, [r0, #0x100]
+ str r3, [r0, #0xc8]
+ str r3, [r0, #0x128]
+ str r3, [r0, #0xf4]
+ str r3, [r0, #0xfc]
+ str r3, [r0, #0xcc]
+ str r3, [r0, #0x124]
+
+//*===========================================
+// DDR controller setting
+//*===========================================
+// CTL setting
+ ldr r0, =DATABAHN_BASE_ADDR
+
+#if defined(CONFIG_ZQ_CALIB)
+ do_zq_calib
+#else
+// setmem /32 0x1400012C = 0x00000817 // pd=<<8, pu=<<0
+ ldr r1, =0x00000817
+ str r1, [r0, #0x12c]
+// setmem /32 0x14000128 = 0x09180000 // (pd+1)<<24, (pu+1)<<16
+ ldr r1, =0x09180000
+ str r1, [r0, #0x128]
+// load PU, pu_pd_sel=0
+// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
+ ldr r1, =0x00310000
+ str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000 // clear for next load
+ ldr r1, =0x00200000
+ str r1, [r0, #0x124]
+// load PD, pu_pd_sel=1
+// setmem /32 0x14000128 = 0x09180010 // (pd+1)<<24, (pu+1)<<16, 1<<4
+ ldr r1, =0x09180010
+ str r1, [r0, #0x128]
+// setmem /32 0x14000124 = 0x00310000 // software load ZQ: 3<<20, 1<<16
+ ldr r1, =0x00310000
+ str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000 // clear for next load
+ ldr r1, =0x00200000
+ str r1, [r0, #0x124]
+#endif
+
+/*==============================================================
+ * DDR setting
+ *=============================================================*/
+/* setmem /32 0x14000000 = 0x00000100 */
+ ldr r1, =0x00000100
+ str r1, [r0, #0x0]
+/* setmem /32 0x14000008 = 0x00009c40 */
+ ldr r1, =0x00009c40
+ str r1, [r0, #0x8]
+/* setmem /32 0x14000014 = 0x02000000 */
+ ldr r1, =0x02000000
+ str r1, [r0, #0x14]
+/* setmem /32 0x14000018 = 0x01010706 */
+ ldr r1, =0x01010706
+ str r1, [r0, #0x018]
+/* setmem /32 0x1400001c = 0x080b0201 */
+ ldr r1, =0x080b0201
+ str r1, [r0, #0x01c]
+/* setmem /32 0x14000020 = 0x02000303 */
+ ldr r1, =0x02000303
+ str r1, [r0, #0x020]
+/* setmem /32 0x14000024 = 0x0136b002 */
+ ldr r1, =0x0136b002
+ str r1, [r0, #0x024]
+/* setmem /32 0x14000028 = 0x01000101 */
+ ldr r1, =0x01000101
+ str r1, [r0, #0x028]
+/* setmem /32 0x1400002c = 0x06030301 */
+ ldr r1, =0x06030301
+ str r1, [r0, #0x02c]
+/* setmem /32 0x14000030 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x030]
+/* setmem /32 0x14000034 = 0x00000a02 */
+ ldr r1, =0x00000a02
+ str r1, [r0, #0x034]
+/* setmem /32 0x14000038 = 0x00000003 */
+ ldr r1, =0x00000003
+ str r1, [r0, #0x038]
+/* setmem /32 0x1400003c = 0x00001401 */
+ ldr r1, =0x00001401
+ str r1, [r0, #0x03c]
+/* setmem /32 0x14000040 = 0x0005030f */
+ ldr r1, =0x0005030f
+ str r1, [r0, #0x040]
+/* setmem /32 0x14000044 = 0x00000200 */
+ ldr r1, =0x00000200
+ str r1, [r0, #0x044]
+/* setmem /32 0x14000048 = 0x00180018 */
+ ldr r1, =0x00180018
+ str r1, [r0, #0x048]
+/* setmem /32 0x1400004c = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0x04c]
+/* setmem /32 0x1400005c = 0x01000000 */
+ ldr r1, =0x01000000
+ str r1, [r0, #0x05c]
+/* setmem /32 0x14000060 = 0x00000001 */
+ ldr r1, =0x00000001
+ str r1, [r0, #0x060]
+/* setmem /32 0x14000064 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x064]
+/* setmem /32 0x14000068 = 0x00320000 */
+ ldr r1, =0x00320000
+ str r1, [r0, #0x068]
+/* setmem /32 0x1400006c = 0x00800000 */
+ ldr r1, =0x00800000
+ str r1, [r0, #0x06c]
+/* setmem /32 0x14000070 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x070]
+/* setmem /32 0x14000074 = 0x00320000 */
+ ldr r1, =0x00320000
+ str r1, [r0, #0x074]
+/* setmem /32 0x14000080 = 0x02000000 */
+ ldr r1, =0x02000000
+ str r1, [r0, #0x080]
+/* setmem /32 0x14000084 = 0x00000100 */
+ ldr r1, =0x00000100
+ str r1, [r0, #0x084]
+/* setmem /32 0x14000088 = 0x02400040 */
+ ldr r1, =0x02400040
+ str r1, [r0, #0x088]
+/* setmem /32 0x1400008c = 0x01000000 */
+ ldr r1, =0x01000000
+ str r1, [r0, #0x08c]
+/* setmem /32 0x14000090 = 0x0a000100 */
+ ldr r1, =0x0a000100
+ str r1, [r0, #0x090]
+/* setmem /32 0x14000094 = 0x01011f1f */
+ ldr r1, =0x01011f1f
+ str r1, [r0, #0x094]
+/* setmem /32 0x14000098 = 0x01010101 */
+ ldr r1, =0x01010101
+ str r1, [r0, #0x098]
+/* setmem /32 0x1400009c = 0x00030101 */
+ ldr r1, =0x00030101
+ str r1, [r0, #0x09c]
+/* setmem /32 0x140000a4 = 0x00010000 */
+ ldr r1, =0x00010000
+ str r1, [r0, #0x0a4]
+/* setmem /32 0x140000ac = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0x0ac]
+/* setmem /32 0x140000c8 = 0x02020101 */
+ ldr r1, =0x02020101
+ str r1, [r0, #0x0c8]
+/* setmem /32 0x140000cc = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x0cc]
+/* setmem /32 0x140000d0 = 0x01000202 */
+ ldr r1, =0x01000202
+ str r1, [r0, #0x0d0]
+/* setmem /32 0x140000d4 = 0x02030302 */
+ ldr r1, =0x02030302
+ str r1, [r0, #0x0d4]
+/* setmem /32 0x140000d8 = 0x00000001 */
+ ldr r1, =0x00000001
+ str r1, [r0, #0x0d8]
+/* setmem /32 0x140000dc = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0x0dc]
+/* setmem /32 0x140000e0 = 0x0000ffff */
+ ldr r1, =0x0000ffff
+ str r1, [r0, #0x0e0]
+/* setmem /32 0x140000e4 = 0x02020000 */
+ ldr r1, =0x02020000
+ str r1, [r0, #0x0e4]
+/* setmem /32 0x140000e8 = 0x02020202 */
+ ldr r1, =0x02020202
+ str r1, [r0, #0x0e8]
+/* setmem /32 0x140000ec = 0x00000202 */
+ ldr r1, =0x00000202
+ str r1, [r0, #0x0ec]
+/* setmem /32 0x140000f0 = 0x01010064 */
+ ldr r1, =0x01010064
+ str r1, [r0, #0x0f0]
+/* setmem /32 0x140000f4 = 0x01010101 */
+ ldr r1, =0x01010101
+ str r1, [r0, #0x0f4]
+/* setmem /32 0x140000f8 = 0x00010101 */
+ ldr r1, =0x00010101
+ str r1, [r0, #0x0f8]
+/* setmem /32 0x140000fc = 0x00000064 */
+ ldr r1, =0x00000064
+ str r1, [r0, #0x0fc]
+/* setmem /32 0x14000104 = 0x02000602 */
+ ldr r1, =0x02000602
+ str r1, [r0, #0x0104]
+/* setmem /32 0x14000108 = 0x06120000 */
+ ldr r1, =0x06120000
+ str r1, [r0, #0x0108]
+/* setmem /32 0x1400010c = 0x06120612 */
+ ldr r1, =0x06120612
+ str r1, [r0, #0x010c]
+/* setmem /32 0x14000110 = 0x06120612 */
+ ldr r1, =0x06120612
+ str r1, [r0, #0x0110]
+/* setmem /32 0x14000114 = 0x01030612 */
+ ldr r1, =0x01030612
+ str r1, [r0, #0x0114]
+/* setmem /32 0x14000118 = 0x01010002 */
+ ldr r1, =0x01010002
+ str r1, [r0, #0x0118]
+
+/*=============================================================
+ * DDR PHY setting
+ *===========================================================*/
+
+/* setmem /32 0x14000200 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x200]
+/* setmem /32 0x14000204 = 0x00000000 */
+ str r1, [r0, #0x0204]
+/* setmem /32 0x14000208 = 0xf5002725 */
+ ldr r1, =0xf5002725
+ str r1, [r0, #0x0208]
+/* setmem /32 0x14000210 = 0xf5002725 */
+ str r1, [r0, #0x210]
+/* setmem /32 0x14000218 = 0xf5002725 */
+ str r1, [r0, #0x218]
+/* setmem /32 0x14000220 = 0xf5002725 */
+ str r1, [r0, #0x0220]
+/* setmem /32 0x14000228 = 0xf5002725 */
+ str r1, [r0, #0x0228]
+/* setmem /32 0x14000234 = 0x00800006*/
+ ldr r1, =0x00800006
+ str r1, [r0, #0x0234]
+/* setmem /32 0x1400020c = 0x070002d0 */
+ ldr r1, =0x070002d0
+ str r1, [r0, #0x020c]
+/* setmem /32 0x14000214 = 0x074002d0 */
+ str r1, [r0, #0x0214]
+/* setmem /32 0x1400021c = 0x074002d0 */
+ str r1, [r0, #0x021c]
+/* setmem /32 0x14000224 = 0x074002d0 */
+ str r1, [r0, #0x0224]
+/* setmem /32 0x1400022c = 0x074002d0 */
+ str r1, [r0, #0x022c]
+/* setmem /32 0x14000230 = 0x00000000 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x0230]
+/* setmem /32 0x14000238 = 0x200e1014 */
+ ldr r1, =0x200e1014
+ str r1, [r0, #0x0238]
+/* setmem /32 0x14000240 = 0x200e1014 */
+ str r1, [r0, #0x0240]
+/* setmem /32 0x14000248 = 0x200e1014 */
+ str r1, [r0, #0x0248]
+/* setmem /32 0x14000250 = 0x200e1014 */
+ str r1, [r0, #0x0250]
+/* setmem /32 0x14000258 = 0x200e1014 */
+ str r1, [r0, #0x0258]
+/* setmem /32 0x1400023c = 0x000d9f01 */
+ ldr r1, =0x000d9f01
+ str r1, [r0, #0x023c]
+/* setmem /32 0x14000244 = 0x000d9f01 */
+ str r1, [r0, #0x0244]
+/* setmem /32 0x1400024c = 0x000d9f01 */
+ str r1, [r0, #0x024c]
+/* setmem /32 0x14000254 = 0x000d9f01 */
+ str r1, [r0, #0x0254]
+/* setmem /32 0x1400025c = 0x000d9f01 */
+ str r1, [r0, #0x025c]
+
+/* Start ddr */
+/* setmem /32 0x14000000 = 0x00000101 // bit[0]: start */
+ ldr r1, =0x00000101
+ str r1, [r0, #0x0]
/* poll to make sure it is done */
1:
ldr r1, [r0, #0xa8]
ands r1, r1, #0x10
beq 1b
+#endif
+
/*
* The following is to fill in those arguments for this ROM function
* pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
@@ -748,11 +1783,12 @@ after_calling_rom___pu_irom_hwcnfg_setup:
mov r0, #1
bx lr /* return back to ROM code */
+/* Data be copied by pu_irom_hwcnfg_setup() */
DDR_DEST_ADDR: .word TEXT_BASE
COPY_SIZE: .word _end - TEXT_BASE
BOOT_DATA: .word TEXT_BASE
.word _end - TEXT_BASE
.word 0
-IVT2_HDR_OFS: .word ivt2_header - TEXT_BASE
+IVT2_HDR_OFS: .word ivt2_header - TEXT_BASE
#endif
diff --git a/board/freescale/mx50_rdp/mx50_rdp.c b/board/freescale/mx50_rdp/mx50_rdp.c
index 924c7e6..6450373 100644
--- a/board/freescale/mx50_rdp/mx50_rdp.c
+++ b/board/freescale/mx50_rdp/mx50_rdp.c
@@ -52,11 +52,14 @@
#include <asm/clock.h>
#endif
+#ifdef CONFIG_MXC_EPDC
+#include <lcd.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static u32 system_rev;
static enum boot_device boot_dev;
-u32 mx51_io_base_addr;
static inline void setup_boot_device(void)
{
@@ -261,6 +264,25 @@ static void setup_i2c(unsigned int module_base)
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
break;
+ case I2C3_BASE_ADDR:
+ /* i2c3 SDA */
+ mxc_request_iomux(MX50_PIN_I2C3_SDA,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX50_PIN_I2C3_SDA,
+ PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+
+ /* i2c3 SCL */
+ mxc_request_iomux(MX50_PIN_I2C3_SCL,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX50_PIN_I2C3_SCL,
+ PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+ break;
default:
printf("Invalid I2C base: 0x%x\n", module_base);
break;
@@ -566,6 +588,7 @@ static void setup_fec(void)
{
volatile unsigned int reg;
+#if defined(CONFIG_MX50_RDP)
/* FEC_EN: gpio6-23 set to 0 to enable FEC */
mxc_request_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT1);
@@ -576,7 +599,7 @@ static void setup_fec(void)
reg = readl(GPIO6_BASE_ADDR + 0x4);
reg |= (1 << 23);
writel(reg, GPIO6_BASE_ADDR + 0x4);
-
+#endif
/*FEC_MDIO*/
mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6);
@@ -624,6 +647,7 @@ static void setup_fec(void)
mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0);
mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0);
+#if defined(CONFIG_MX50_RDP)
/* FEC_RESET_B: gpio4-12 */
mxc_request_iomux(MX50_PIN_ECSPI1_SCLK, IOMUX_CONFIG_ALT1);
@@ -640,6 +664,26 @@ static void setup_fec(void)
reg = readl(GPIO4_BASE_ADDR + 0x0);
reg |= (1 << 12);
writel(reg, GPIO4_BASE_ADDR + 0x0);
+#elif defined(CONFIG_MX50_ARM2)
+ /* phy reset: gpio4-6 */
+ mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
+
+ reg = readl(GPIO4_BASE_ADDR + 0x0);
+ reg &= ~0x40;
+ writel(reg, GPIO4_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO4_BASE_ADDR + 0x4);
+ reg |= 0x40;
+ writel(reg, GPIO4_BASE_ADDR + 0x4);
+
+ udelay(500);
+
+ reg = readl(GPIO4_BASE_ADDR + 0x0);
+ reg |= 0x40;
+ writel(reg, GPIO4_BASE_ADDR + 0x0);
+#else
+# error "Unsupported board!"
+#endif
}
#endif
@@ -772,6 +816,244 @@ int board_mmc_init(bd_t *bis)
#endif
+#ifdef CONFIG_MXC_EPDC
+#ifdef CONFIG_SPLASH_SCREEN
+int setup_splash_img()
+{
+#ifdef CONFIG_SPLASH_IS_IN_MMC
+ int mmc_dev = get_mmc_env_devno();
+ ulong offset = CONFIG_SPLASH_IMG_OFFSET;
+ ulong size = CONFIG_SPLASH_IMG_SIZE;
+ ulong addr = 0;
+ char *s = NULL;
+ struct mmc *mmc = find_mmc_device(mmc_dev);
+ uint blk_start, blk_cnt, n;
+
+ s = getenv("splashimage");
+
+ if (NULL == s) {
+ puts("env splashimage not found!\n");
+ return -1;
+ }
+ addr = simple_strtoul(s, NULL, 16);
+
+ if (!mmc) {
+ printf("MMC Device %d not found\n",
+ mmc_dev);
+ return -1;
+ }
+
+ if (mmc_init(mmc)) {
+ puts("MMC init failed\n");
+ return -1;
+ }
+
+ blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+ n = mmc->block_dev.block_read(mmc_dev, blk_start,
+ blk_cnt, (u_char *)addr);
+ flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
+
+ return (n == blk_cnt) ? 0 : -1;
+#endif
+}
+#endif
+
+vidinfo_t panel_info = {
+ .vl_refresh = 60,
+ .vl_col = 800,
+ .vl_row = 600,
+ .vl_pixclock = 17700000,
+ .vl_left_margin = 8,
+ .vl_right_margin = 142,
+ .vl_upper_margin = 4,
+ .vl_lower_margin = 10,
+ .vl_hsync = 20,
+ .vl_vsync = 4,
+ .vl_sync = 0,
+ .vl_mode = 0,
+ .vl_flag = 0,
+ .vl_bpix = 3,
+ cmap:0,
+};
+
+static void setup_epdc_power()
+{
+ unsigned int reg;
+
+ /* Setup epdc voltage */
+
+ /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
+ mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
+
+ /* EPDC VCOM0 - GPIO4[21] for VCOM control */
+ mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
+ /* Set as output */
+ reg = readl(GPIO4_BASE_ADDR + 0x4);
+ reg |= (1 << 21);
+ writel(reg, GPIO4_BASE_ADDR + 0x4);
+
+ /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
+ mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
+ /* Set as output */
+ reg = readl(GPIO6_BASE_ADDR + 0x4);
+ reg |= (1 << 16);
+ writel(reg, GPIO6_BASE_ADDR + 0x4);
+}
+
+void epdc_power_on()
+{
+ unsigned int reg;
+
+ /* Set PMIC Wakeup to high - enable Display power */
+ reg = readl(GPIO6_BASE_ADDR + 0x0);
+ reg |= (1 << 16);
+ writel(reg, GPIO6_BASE_ADDR + 0x0);
+
+ /* Wait for PWRGOOD == 1 */
+ while (1) {
+ reg = readl(GPIO3_BASE_ADDR + 0x0);
+ if (!(reg & (1 << 28)))
+ break;
+
+ udelay(100);
+ }
+
+ /* Enable VCOM */
+ reg = readl(GPIO4_BASE_ADDR + 0x0);
+ reg |= (1 << 21);
+ writel(reg, GPIO4_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO4_BASE_ADDR + 0x0);
+
+ udelay(500);
+}
+
+void epdc_power_off()
+{
+ unsigned int reg;
+ /* Set PMIC Wakeup to low - disable Display power */
+ reg = readl(GPIO6_BASE_ADDR + 0x0);
+ reg |= 0 << 16;
+ writel(reg, GPIO6_BASE_ADDR + 0x0);
+
+ /* Disable VCOM */
+ reg = readl(GPIO4_BASE_ADDR + 0x0);
+ reg |= 0 << 21;
+ writel(reg, GPIO4_BASE_ADDR + 0x0);
+}
+
+int setup_waveform_file()
+{
+#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
+ int mmc_dev = get_mmc_env_devno();
+ ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
+ ulong size = CONFIG_WAVEFORM_FILE_SIZE;
+ ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
+ char *s = NULL;
+ struct mmc *mmc = find_mmc_device(mmc_dev);
+ uint blk_start, blk_cnt, n;
+
+ if (!mmc) {
+ printf("MMC Device %d not found\n",
+ mmc_dev);
+ return -1;
+ }
+
+ if (mmc_init(mmc)) {
+ puts("MMC init failed\n");
+ return -1;
+ }
+
+ blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+ n = mmc->block_dev.block_read(mmc_dev, blk_start,
+ blk_cnt, (u_char *)addr);
+ flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
+
+ return (n == blk_cnt) ? 0 : -1;
+#else
+ return -1;
+#endif
+}
+
+static void setup_epdc()
+{
+ unsigned int reg;
+
+ /* epdc iomux settings */
+ mxc_request_iomux(MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0);
+
+
+ /*** epdc Maxim PMIC settings ***/
+
+ /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
+ mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
+
+ /* EPDC VCOM0 - GPIO4[21] for VCOM control */
+ mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
+
+ /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
+ mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
+
+
+ /*** Set pixel clock rates for EPDC ***/
+
+ /* EPDC AXI clk and EPDC PIX clk from PLL1 */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
+ reg &= ~(0x3 << 4);
+ reg |= (0x2 << 4) | (0x2 << 12);
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
+
+ /* EPDC AXI clk enable and set to 200MHz (800/4) */
+ reg = readl(CCM_BASE_ADDR + 0xA8);
+ reg &= ~((0x3 << 30) | 0x3F);
+ reg |= (0x2 << 30) | 0x4;
+ writel(reg, CCM_BASE_ADDR + 0xA8);
+
+ /* EPDC PIX clk enable and set to 20MHz (800/40) */
+ reg = readl(CCM_BASE_ADDR + 0xA0);
+ reg &= ~((0x3 << 30) | (0x3 << 12) | 0x3F);
+ reg |= (0x2 << 30) | (0x1 << 12) | 0x2D;
+ writel(reg, CCM_BASE_ADDR + 0xA0);
+
+ panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
+ panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
+
+ panel_info.epdc_data.wv_modes.mode_init = 0;
+ panel_info.epdc_data.wv_modes.mode_du = 1;
+ panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+ panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+ panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+ panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+ setup_epdc_power();
+
+ /* Assign fb_base */
+ gd->fb_base = CONFIG_FB_BASE;
+}
+#endif
+
+
#ifdef CONFIG_IMX_CSPI
static void setup_power(void)
{
@@ -828,7 +1110,13 @@ int board_init(void)
setup_soc_rev();
/* arch id for linux */
+#if defined(CONFIG_MX50_RDP)
gd->bd->bi_arch_number = MACH_TYPE_MX50_RDP;
+#elif defined(CONFIG_MX50_ARM2)
+ gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2;
+#else
+# error "Unsupported board!"
+#endif
/* boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -845,6 +1133,10 @@ int board_init(void)
setup_gpmi_nand();
#endif
+#ifdef CONFIG_MXC_EPDC
+ setup_epdc();
+#endif
+
return 0;
}
@@ -858,7 +1150,13 @@ int board_late_init(void)
int checkboard(void)
{
+#if defined(CONFIG_MX50_RDP)
printf("Board: MX50 RDP board\n");
+#elif defined(CONFIG_MX50_ARM2)
+ printf("Board: MX50 ARM2 board\n");
+#else
+# error "Unsupported board!"
+#endif
printf("Boot Reason: [");
diff --git a/include/configs/mx50_arm2_ddr2.h b/include/configs/mx50_arm2_ddr2.h
index c4dff04..493673d 100644
--- a/include/configs/mx50_arm2_ddr2.h
+++ b/include/configs/mx50_arm2_ddr2.h
@@ -27,7 +27,7 @@
/* High Level Configuration Options */
#define CONFIG_MXC
#define CONFIG_MX50
-#define CONFIG_MX50_ARM_EVK
+#define CONFIG_MX50_ARM2
#define CONFIG_DDR2
#define CONFIG_FLASH_HEADER
#define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx50_rdp.h b/include/configs/mx50_rdp.h
index bad6dd1..4317e27 100644
--- a/include/configs/mx50_rdp.h
+++ b/include/configs/mx50_rdp.h
@@ -28,6 +28,7 @@
#define CONFIG_MXC
#define CONFIG_MX50
#define CONFIG_MX50_RDP
+#define CONFIG_LPDDR2
#define CONFIG_FLASH_HEADER
#define CONFIG_FLASH_HEADER_OFFSET 0x400
generated by cgit v1.1 at 2024-09-27 19:19:30 +0000