sh: Fix compile warning

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

9 files changed, 133 insertions, 100 deletions

diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
index 332f65a..8b46595 100644
--- a/board/ms7722se/lowlevel_init.S
+++ b/board/ms7722se/lowlevel_init.S
@@ -43,48 +43,61 @@
 
 lowlevel_init:
 
-	mov.l	CCR_A, r1	! Address of Cache Control Register
-	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	/* Address of Cache Control Register */
+	mov.l	CCR_A, r1
+	/*Instruction Cache Invalidate */
+	mov.l	CCR_D, r0
 	mov.l	r0, @r1
 
-	mov.l	MMUCR_A, r1	! Address of MMU Control Register
-	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	/* Address of MMU Control Register */
+	mov.l	MMUCR_A, r1
+	/* TI == TLB Invalidate bit */
+	mov.l	MMUCR_D, r0
 	mov.l	r0, @r1
 
-	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
-	mov.l	MSTPCR0_D, r0	!
+	/* Address of Power Control Register 0 */
+	mov.l	MSTPCR0_A, r1
+	mov.l	MSTPCR0_D, r0
 	mov.l	r0, @r1
 
-	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
-	mov.l	MSTPCR2_D, r0	!
+	/* Address of Power Control Register 2 */
+	mov.l	MSTPCR2_A, r1
+	mov.l	MSTPCR2_D, r0
 	mov.l	r0, @r1
 
-	mov.l	SBSCR_A, r1	!
-	mov.w	SBSCR_D, r0	!
+	mov.l	SBSCR_A, r1
+	mov.w	SBSCR_D, r0
 	mov.w	r0, @r1
 
-	mov.l	PSCR_A, r1	!
-	mov.w	PSCR_D, r0	!
+	mov.l	PSCR_A, r1
+	mov.w	PSCR_D, r0
 	mov.w	r0, @r1
 
-!	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-!	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+!	mov.l	RWTCSR_A, r1
+	/* 0xA507 -> timer_STOP/WDT_CLK=max */
+!	mov.w	RWTCSR_D_1, r0
 !	mov.w	r0, @r1
 
-	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
-	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	/* 0xA4520000 (Watchdog Count Register) */
+	mov.l	RWTCNT_A, r1
+	/*0x5A00 -> Clear */
+	mov.w	RWTCNT_D, r0
 	mov.w	r0, @r1
 
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+	mov.l	RWTCSR_A, r1
+	/* 0xA504 -> timer_STOP/CLK=500ms */
+	mov.w	RWTCSR_D_2, r0
 	mov.w	r0, @r1
 
-	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	/* 0xA4150000 Frequency control register */
+	mov.l	FRQCR_A, r1
 	mov.l	FRQCR_D, r0	!
 	mov.l	r0, @r1
 
-	mov.l	CCR_A, r1		! Address of Cache Control Register
-	mov.l	CCR_D_2, r0	! ??
+	mov.l	CCR_A, r1
+	mov.l	CCR_D_2, r0
 	mov.l	r0, @r1
 
 bsc_init:
@@ -290,5 +303,6 @@ PSCR_D:		.word	0x0000
 RWTCSR_D_1:	.word	0xA507
 RWTCSR_D_2:	.word	0xA507
 RWTCNT_D:	.word	0x5A00
+	.align	2
 
 SR_MASK_D:	.long	0xEFFFFF0F
diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S
index 05c075b..ab0499a 100644
--- a/board/r7780mp/lowlevel_init.S
+++ b/board/r7780mp/lowlevel_init.S
@@ -325,8 +325,9 @@ repeat2:
 RWTCSR_D_1:				.word	0xA507
 RWTCSR_D_2:				.word	0xA507
 RWTCNT_D:				.word	0x5A00
+	.align	2
 
-BBG_PMMR_A:			.long	0xFF800010
+BBG_PMMR_A:				.long	0xFF800010
 BBG_PMSR1_A:			.long	0xFF800014
 BBG_PMSR2_A:			.long	0xFF800018
 BBG_PMSR3_A:			.long	0xFF80001C
diff --git a/board/sh7785lcr/selfcheck.c b/board/sh7785lcr/selfcheck.c
index d924595..ce0620f 100644
--- a/board/sh7785lcr/selfcheck.c
+++ b/board/sh7785lcr/selfcheck.c
@@ -84,7 +84,7 @@ static void test_net(void)
 	if (data == 0x816910ec)
 		printf("Ethernet OK\n");
 	else
-		printf("Ethernet NG, data = %08x\n", data);
+		printf("Ethernet NG, data = %08x\n", (unsigned int)data);
 }
 
 static void test_sata(void)
@@ -96,7 +96,7 @@ static void test_sata(void)
 	if (data == 0x35121095)
 		printf("SATA OK\n");
 	else
-		printf("SATA NG, data = %08x\n", data);
+		printf("SATA NG, data = %08x\n", (unsigned int)data);
 }
 
 static void test_pci(void)
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index a058e1d..e3a0ea0 100644
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c
@@ -23,18 +23,19 @@
  */
 
 #include <common.h>
+#include <pci.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <pci.h>
+#include <asm/pci.h>
 
 /* Register addresses and such */
 #define SH7751_BCR1	(vu_long *)0xFF800000
-#define SH7751_BCR2	(vu_short*)0xFF800004
+#define SH7751_BCR2	(vu_short *)0xFF800004
 #define SH7751_WCR1	(vu_long *)0xFF800008
 #define SH7751_WCR2	(vu_long *)0xFF80000C
 #define SH7751_WCR3	(vu_long *)0xFF800010
 #define SH7751_MCR	(vu_long *)0xFF800014
-#define SH7751_BCR3	(vu_short*)0xFF800050
+#define SH7751_BCR3	(vu_short *)0xFF800050
 #define SH7751_PCICONF0 (vu_long *)0xFE200000
 #define SH7751_PCICONF1 (vu_long *)0xFE200004
 #define SH7751_PCICONF2 (vu_long *)0xFE200008
@@ -87,12 +88,12 @@
 #define SH7751_PCIPAR   (vu_long *)0xFE2001C0
 #define SH7751_PCIPDR   (vu_long *)0xFE200220
 
-#define p4_in(addr)     *(addr)
-#define p4_out(data,addr) *(addr) = (data)
+#define p4_in(addr)	(*addr)
+#define p4_out(data, addr) (*addr) = (data)
 
 /* Double word */
 int pci_sh4_read_config_dword(struct pci_controller *hose,
-			      pci_dev_t dev, int offset, u32 * value)
+			      pci_dev_t dev, int offset, u32 *value)
 {
 	u32 par_data = 0x80000000 | dev;
 
@@ -103,7 +104,7 @@ int pci_sh4_read_config_dword(struct pci_controller *hose,
 }
 
 int pci_sh4_write_config_dword(struct pci_controller *hose,
-			       pci_dev_t dev, int offset, u32 * value)
+			       pci_dev_t dev, int offset, u32 value)
 {
 	u32 par_data = 0x80000000 | dev;
 
@@ -126,15 +127,18 @@ int pci_sh7751_init(struct pci_controller *hose)
 	/* Double-check some BSC config settings */
 	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
 	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
-		printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+		printf("SH7751_BCR1 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR1));
 		return 2;
 	}
 	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
-		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR2));
 		return 3;
 	}
 	if (p4_in(SH7751_BCR2) & 0x01) {
-		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR2));
 		return 4;
 	}
 
diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c
index 2d04b4f..7555d96 100644
--- a/drivers/pci/pci_sh7780.c
+++ b/drivers/pci/pci_sh7780.c
@@ -25,9 +25,10 @@
 
 #include <common.h>
 
+#include <pci.h>
 #include <asm/processor.h>
+#include <asm/pci.h>
 #include <asm/io.h>
-#include <pci.h>
 
 #define SH7780_VENDOR_ID	0x1912
 #define SH7780_DEVICE_ID	0x0002
@@ -41,10 +42,10 @@
 #define SH7780_PCICR_PRST	0x00000002
 #define SH7780_PCICR_CFIN	0x00000001
 
-#define p4_in(addr)			*((vu_long *)addr)
-#define p4_out(data,addr)	*(vu_long *)(addr) = (data)
-#define p4_inw(addr)		*((vu_short *)addr)
-#define p4_outw(data,addr)	*(vu_short *)(addr) = (data)
+#define p4_in(addr)			(*(vu_long *)addr)
+#define p4_out(data, addr)	(*(vu_long *)addr) = (data)
+#define p4_inw(addr)		(*(vu_short *)addr)
+#define p4_outw(data, addr)	(*(vu_short *)addr) = (data)
 
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 				    pci_dev_t dev, int offset, u32 *value)
@@ -72,9 +73,9 @@ int pci_sh7780_init(struct pci_controller *hose)
 	p4_out(0x01, SH7780_PCIECR);
 
 	if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
-	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
 		printf("PCI: Unknown PCI host bridge.\n");
-		return;
+		return -1;
 	}
 	printf("PCI: SH7780 PCI host bridge found.\n");
 
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 25b409b..2cfc0a7 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -3,29 +3,31 @@
 
 #if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
 
+int cache_control(unsigned int cmd);
+
 #define L1_CACHE_BYTES 32
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
-void dcache_wback_range (u32 start, u32 end)
+void dcache_wback_range(u32 start, u32 end)
 {
 	u32 v;
 
 	start &= ~(L1_CACHE_BYTES - 1);
 	for (v = start; v < end; v += L1_CACHE_BYTES) {
-		asm volatile ("ocbwb     %0":	/* no output */
-			      :"m" (__m (v)));
+		asm volatile ("ocbwb     %0" :	/* no output */
+			      : "m" (__m(v)));
 	}
 }
 
-void dcache_invalid_range (u32 start, u32 end)
+void dcache_invalid_range(u32 start, u32 end)
 {
 	u32 v;
 
 	start &= ~(L1_CACHE_BYTES - 1);
 	for (v = start; v < end; v += L1_CACHE_BYTES) {
-		asm volatile ("ocbi     %0":	/* no output */
-			      :"m" (__m (v)));
+		asm volatile ("ocbi     %0" :	/* no output */
+			      : "m" (__m(v)));
 	}
 }
 #endif /* CONFIG_SH4 || CONFIG_SH4A */
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 7400293..adc3f81 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -34,9 +34,9 @@
 #define __arch_getw(a)			(*(volatile unsigned short *)(a))
 #define __arch_getl(a)			(*(volatile unsigned int *)(a))
 
-#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
 
 extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
 extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
@@ -46,9 +46,9 @@ extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
 extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
 extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)		__arch_putb(v,a)
-#define __raw_writew(v,a)		__arch_putw(v,a)
-#define __raw_writel(v,a)		__arch_putl(v,a)
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
 
 #define __raw_readb(a)			__arch_getb(a)
 #define __raw_readw(a)			__arch_getw(a)
@@ -59,13 +59,13 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  * properly.  Spell it out to the compiler in some cases.
  * These are only valid for small values of "off" (< 1<<12)
  */
-#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
-#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
-#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
 
-#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
-#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
-#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
 
 /*
  * Now, pick up the machine-defined IO definitions
@@ -91,36 +91,43 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  *
  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
  */
-#define outb(v,p)               __raw_writeb(v, p)
-#define outw(v,p)               __raw_writew(cpu_to_le16(v),p)
-#define outl(v,p)               __raw_writel(cpu_to_le32(v),p)
+#define outb(v, p)               __raw_writeb(v, p)
+#define outw(v, p)               __raw_writew(cpu_to_le16(v), p)
+#define outl(v, p)               __raw_writel(cpu_to_le32(v), p)
 
 #define inb(p)  ({ unsigned int __v = __raw_readb(p); __v; })
 #define inw(p)  ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
 #define inl(p)  ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
 
-#define outsb(p,d,l)			__raw_writesb(p,d,l)
-#define outsw(p,d,l)			__raw_writesw(p,d,l)
-#define outsl(p,d,l)			__raw_writesl(p,d,l)
+#define outsb(p, d, l)			__raw_writesb(p, d, l)
+#define outsw(p, d, l)			__raw_writesw(p, d, l)
+#define outsl(p, d, l)			__raw_writesl(p, d, l)
 
-#define insb(p,d,l)			__raw_readsb(p,d,l)
-#define insw(p,d,l)			__raw_readsw(p,d,l)
-#define insl(p,d,l)			__raw_readsl(p,d,l)
+#define insb(p, d, l)			__raw_readsb(p, d, l)
+#define insw(p, d, l)			__raw_readsw(p, d, l)
+#define insl(p, d, l)			__raw_readsl(p, d, l)
 
-#define outb_p(val,port)		outb((val),(port))
-#define outw_p(val,port)		outw((val),(port))
-#define outl_p(val,port)		outl((val),(port))
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
 #define inb_p(port)			inb((port))
 #define inw_p(port)			inw((port))
 #define inl_p(port)			inl((port))
 
-#define outsb_p(port,from,len)		outsb(port,from,len)
-#define outsw_p(port,from,len)		outsw(port,from,len)
-#define outsl_p(port,from,len)		outsl(port,from,len)
-#define insb_p(port,to,len)		insb(port,to,len)
-#define insw_p(port,to,len)		insw(port,to,len)
-#define insl_p(port,to,len)		insl(port,to,len)
-
+#define outsb_p(port, from, len)		outsb(port, from, len)
+#define outsw_p(port, from, len)		outsw(port, from, len)
+#define outsl_p(port, from, len)		outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/* for U-Boot PCI */
+#define out_8(port, val)	outb(val, port)
+#define out_le16(port, val)	outw(val, port)
+#define out_le32(port, val)	outl(val, port)
+#define in_8(port)			inb(port)
+#define in_le16(port)		inw(port)
+#define in_le32(port)		inl(port)
 /*
  * ioremap and friends.
  *
@@ -128,7 +135,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  * linux/Documentation/IO-mapping.txt.  If you want a
  * physical address, use __ioremap instead.
  */
-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
 extern void __iounmap(void *addr);
 
 /*
@@ -139,20 +146,20 @@ extern void __iounmap(void *addr);
  *  iomem_to_phys(off)
  */
 #ifdef iomem_valid_addr
-#define __arch_ioremap(off,sz,nocache)				\
+#define __arch_ioremap(off, sz, nocache)				\
  ({								\
 	unsigned long _off = (off), _size = (sz);		\
 	void *_ret = (void *)0;					\
 	if (iomem_valid_addr(_off, _size))			\
-		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
 	_ret;							\
  })
 
 #define __arch_iounmap __iounmap
 #endif
 
-#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
-#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define ioremap(off, sz)			__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)		__arch_ioremap((off), (sz), 1)
 #define iounmap(_addr)			__arch_iounmap(_addr)
 
 /*
@@ -180,19 +187,21 @@ extern void _memset_io(unsigned long, int, size_t);
 #ifdef __mem_pci
 
 #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+#define readw(c)\
+	({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c)\
+	({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
 
-#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
-#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
-#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
 
-#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+#define memset_io(c, v, l)		_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
 
-#define eth_io_copy_and_sum(s,c,l,b) \
-				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+#define eth_io_copy_and_sum(s, c, l, b) \
+				eth_copy_and_sum((s), __mem_pci(c), (l), (b))
 
 static inline int
 check_signature(unsigned long io_addr, const unsigned char *signature,
@@ -216,11 +225,11 @@ out:
 #define readb(addr)	__raw_readb(addr)
 #define readw(addr)	__raw_readw(addr)
 #define readl(addr)	__raw_readl(addr)
-#define writeb(v,addr)	__raw_writeb(v, addr)
-#define writew(v,addr)	__raw_writew(v, addr)
-#define writel(v,addr)	__raw_writel(v, addr)
+#define writeb(v, addr)	__raw_writeb(v, addr)
+#define writew(v, addr)	__raw_writew(v, addr)
+#define writel(v, addr)	__raw_writel(v, addr)
 
-#define check_signature(io,sig,len)	(0)
+#define check_signature(io, sig, len)	(0)
 
 #endif	/* __mem_pci */
 
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
index bc59491..040c532 100644
--- a/include/asm-sh/pci.h
+++ b/include/asm-sh/pci.h
@@ -36,6 +36,7 @@ int pci_sh7780_init(struct pci_controller *hose);
 #error "Not support PCI."
 #endif
 
+int pci_sh4_init(struct pci_controller *hose);
 /* PCI dword read for sh4 */
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 		pci_dev_t dev, int offset, u32 *value);
diff --git a/lib_sh/bootm.c b/lib_sh/bootm.c
index d5056ae..e3d4985 100644
--- a/lib_sh/bootm.c
+++ b/lib_sh/bootm.c
@@ -48,11 +48,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 	/* Linux kernel load address */
 	void (*kernel) (void) = (void (*)(void))images->ep;
 	/* empty_zero_page */
-	unsigned char *param = (unsigned char *)image_get_ep(images);
+	unsigned char *param
+		= (unsigned char *)image_get_load(images->legacy_hdr_os);
 	/* Linux kernel command line */
-	unsigned char *cmdline = param + 0x100;
+	char *cmdline = (char *)param + 0x100;
 	/* PAGE_SIZE */
-	unsigned long size = images->ep - image_get_ep(images);
+	unsigned long size = images->ep - (unsigned long)param;
 	char *bootargs = getenv("bootargs");
 
 	/* Setup parameters */