Add missing Blackfin files.

85 files changed, 13157 insertions, 0 deletions

diff --git a/blackfin_config.mk b/blackfin_config.mk
new file mode 100644
index 0000000..e2747aa
--- /dev/null
+++ b/blackfin_config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__
diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile
new file mode 100644
index 0000000..c9b3c92
--- /dev/null
+++ b/board/ezkit533/Makefile
@@ -0,0 +1,44 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ezkit533.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk
new file mode 100644
index 0000000..e4c089d
--- /dev/null
+++ b/board/ezkit533/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+
diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c
new file mode 100644
index 0000000..f8ee900
--- /dev/null
+++ b/board/ezkit533/ezkit533.c
@@ -0,0 +1,71 @@
+/*
+ * U-boot - ezkit533.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_MISC_INIT_R)
+#include "psd4256.h"
+#endif
+
+int checkboard(void)
+{
+	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf("Board: ADI BF533 EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	printf("       Richard Klingler <richard@uclinux.net>\n");
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	int brate;
+	char *tmp = getenv("baudrate");
+	brate = simple_strtoul(tmp, NULL, 16);
+	printf("Serial Port initialized with Baud rate = %x\n",brate);
+	printf("SDRAM attributes:\n");
+	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+	       3, 3, 6, 2, 3);
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* Set direction bits for Video en/decoder reset as output	*/
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
+	/* Deactivate Video en/decoder reset lines			*/
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
+}
+#endif
diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h
new file mode 100644
index 0000000..8f9dff5
--- /dev/null
+++ b/board/ezkit533/flash-defines.h
@@ -0,0 +1,130 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
+#define TRUE			0x1
+#define FALSE			0x0
+#define BUFFER_SIZE		0x80000
+#define NO_COMMAND		0
+#define GET_CODES		1
+#define RESET			2
+#define WRITE			3
+#define FILL			4
+#define ERASE_ALL		5
+#define ERASE_SECT		6
+#define READ			7
+#define GET_SECTNUM		8
+#define FLASH_START_L 		0x0000
+#define FLASH_START_H 		0x2000
+#define FLASH_TOT_SECT		40
+#define FLASH_SIZE 		0x220000
+#define FLASH_MAN_ST 		2
+#define CFG_FLASH0_BASE		0x20000000
+#define RESET_VAL		0xF0
+
+
+asm("#define FLASH_START_L 0x0000");
+asm("#define FLASH_START_H 0x2000");
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int,unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, long lStride, int *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+#define WRITESEQ1		0x0AAA
+#define WRITESEQ2		0x0554
+#define WRITESEQ3		0x0AAA
+#define WRITESEQ4		0x0AAA
+#define WRITESEQ5		0x0554
+#define WRITESEQ6		0x0AAA
+#define WRITEDATA1		0xaa
+#define WRITEDATA2		0x55
+#define WRITEDATA3		0x80
+#define WRITEDATA4		0xaa
+#define WRITEDATA5		0x55
+#define WRITEDATA6		0x10
+#define PriFlashABegin		0
+#define SecFlashABegin		32
+#define SecFlashBBegin		36
+#define PriFlashAOff		0x0
+#define PriFlashBOff		0x100000
+#define SecFlashAOff		0x200000
+#define SecFlashBOff		0x280000
+#define INVALIDLOCNSTART	0x20270000
+#define INVALIDLOCNEND		0x20280000
+#define BlockEraseVal		0x30
+#define UNLOCKDATA1		0xaa
+#define UNLOCKDATA2		0x55
+#define UNLOCKDATA3		0xa0
+#define GETCODEDATA1		0xaa
+#define GETCODEDATA2		0x55
+#define GETCODEDATA3		0x90
+#define SecFlashASec1Off	0x200000
+#define SecFlashASec2Off	0x204000
+#define SecFlashASec3Off	0x206000
+#define SecFlashASec4Off	0x208000
+#define SecFlashAEndOff		0x210000
+#define SecFlashBSec1Off	0x280000
+#define SecFlashBSec2Off	0x284000
+#define SecFlashBSec3Off	0x286000
+#define SecFlashBSec4Off	0x288000
+#define SecFlashBEndOff		0x290000
+
+#define SECT32			32
+#define SECT33			33
+#define SECT34			34
+#define SECT35			35
+#define SECT36			36
+#define SECT37			37
+#define SECT38			38
+#define SECT39			39
+
+#define FLASH_SUCCESS	0
+#define FLASH_FAIL	-1
+
+#endif
diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c
new file mode 100644
index 0000000..0b59232
--- /dev/null
+++ b/board/ezkit533/flash.c
@@ -0,0 +1,476 @@
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+	reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
+			     int bank_flag)
+{
+	int id = 0, i = 0;
+	static int FlagDev = 1;
+
+	id = get_codes();
+	if(FlagDev)	{
+#ifdef DEBUG
+		printf("Device ID of the Flash is %x\n", id);
+#endif
+		FlagDev = 0;
+	}
+	info->flash_id = id;
+
+	switch (bank_flag) {
+	case 0:
+		for (i = PriFlashABegin; i < SecFlashABegin; i++)
+			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+		info->size = 0x200000;
+		info->sector_count = 32;
+		break;
+	case 1:
+		info->start[0] = baseaddr + SecFlashASec1Off;
+		info->start[1] = baseaddr + SecFlashASec2Off;
+		info->start[2] = baseaddr + SecFlashASec3Off;
+		info->start[3] = baseaddr + SecFlashASec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	case 2:
+		info->start[0] = baseaddr + SecFlashBSec1Off;
+		info->start[1] = baseaddr + SecFlashBSec2Off;
+		info->start[2] = baseaddr + SecFlashBSec3Off;
+		info->start[3] = baseaddr + SecFlashBSec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	}
+	return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1, size_b2;
+	int i;
+
+	size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+	printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE);
+	printf("Memory Map for the Flash\n");
+	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+	printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+	printf("Please type command flinfo for information on Sectors \n");
+#endif
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0);
+	size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1);
+	size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 >> 20);
+	}
+
+	(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
+
+	return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id) {
+	case FLASH_PSD4256GV:
+		printf("ST Microelectronics ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int cnt = 0,i;
+	int prot,sect;
+
+	prot = 0;
+        for (sect = s_first; sect <= s_last; ++sect) {
+                if (info->protect[sect])
+                        prot++;
+        }
+
+	if (prot)
+                printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+        else
+                printf ("\n");	
+
+	cnt = s_last - s_first + 1;
+
+	if (cnt == FLASH_TOT_SECT) {
+		printf("Erasing flash, Please Wait \n");
+		if(erase_flash() < 0) {
+			printf("Erasing flash failed \n");
+			return FLASH_FAIL;
+		}
+	} else {
+		printf("Erasing Flash locations, Please Wait\n");
+		for (i = s_first; i <= s_last; i++) {
+			if (info->protect[i] == 0) {	/* not protected */
+				if(erase_block_flash(i, info->start[i]) < 0) {
+					printf("Error Sector erasing \n");
+					return FLASH_FAIL;
+				}
+			}
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int ret;
+
+	ret = write_data(addr, cnt, 1, (int *) src);
+	if(ret == FLASH_FAIL)
+		return ERR_NOT_ERASED;
+	return FLASH_SUCCESS;
+}
+
+
+int write_data(long lStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+	int d;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; (j < iNumWords);
+			j++, ulOffset += (lStride * 2)) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND)) {
+				printf("Invalid locations, Try writing to another location \n");
+				return FLASH_FAIL;
+			}
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset,&d);
+			if(d != 0xffff) {
+				printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
+				return FLASH_FAIL;
+			}
+			unlock_flash(ulOffset);
+			if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
+				printf("Error programming the flash \n");
+				return FLASH_FAIL;
+			}
+			iShift += 16;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset,&d);
+		if(d != 0xffff) {
+			printf("Flash already programmed. Please erase to reprogram \n");
+			printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		if(write_flash(ulOffset, pnData[i]) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	long ulOffset = ulStart;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nHi, nLow;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+				&& (ulOffset < INVALIDLOCNEND))
+					return FLASH_FAIL;
+
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset, &nLow);
+			ulOffset += (lStride * 2);
+			read_flash(ulOffset, &nHi);
+			ulOffset += (lStride * 2);
+			pnData[i] = (nHi << 16) | nLow;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &pnData[i]);
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+	long addr;
+
+	addr = (CFG_FLASH_BASE + nOffset);
+	asm("ssync;");
+	*(unsigned volatile short *) addr = nValue;
+	asm("ssync;");
+	if(poll_toggle_bit(nOffset) < 0)
+		return FLASH_FAIL;
+	return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+	int nValue = 0x0;
+	long addr = (CFG_FLASH_BASE + nOffset);
+
+	if (nOffset != 0x2)
+		reset_flash();
+	asm("ssync;");
+	nValue = *(volatile unsigned short *) addr;
+	asm("ssync;");
+	*pnValue = nValue;
+	return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+	unsigned int u1,u2;
+	unsigned long timeout = 0xFFFFFFFF;
+	volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
+	while(1) {
+		if(timeout < 0)
+			break;
+		u1 = *(volatile unsigned short *)FB;
+		u2 = *(volatile unsigned short *)FB;
+		if((u1 & 0x0040) == (u2 & 0x0040))
+			return FLASH_SUCCESS;
+		if((u2 & 0x0020) == 0x0000)
+			continue;
+		u1 = *(volatile unsigned short *)FB;
+		if((u2 & 0x0040) == (u1 & 0x0040))
+			return FLASH_SUCCESS;
+		else {
+			reset_flash();
+			return FLASH_FAIL;
+		}
+		timeout--;
+	}
+	printf("Time out occured \n");
+	if(timeout <0)	return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+	write_flash(WRITESEQ1, RESET_VAL);
+	/* Wait for 10 micro seconds */
+	udelay(10);
+}
+
+int erase_flash(void)
+{
+	write_flash(WRITESEQ1, WRITEDATA1);
+	write_flash(WRITESEQ2, WRITEDATA2);
+	write_flash(WRITESEQ3, WRITEDATA3);
+	write_flash(WRITESEQ4, WRITEDATA4);
+	write_flash(WRITESEQ5, WRITEDATA5);
+	write_flash(WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(0x0000) < 0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(SecFlashASec1Off) < 0)
+		return FLASH_FAIL;
+
+	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(PriFlashBOff) <0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(SecFlashBOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+	long ulSectorOff = 0x0;
+
+	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+		return FALSE;
+
+	ulSectorOff = (address - CFG_FLASH_BASE);
+
+	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+	write_flash(ulSectorOff, BlockEraseVal);
+
+	if(poll_toggle_bit(ulSectorOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+	unsigned long ulOffsetAddr = ulOffset;
+	ulOffsetAddr &= 0xFFFF0000;
+
+	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+	int dev_id = 0;
+
+	write_flash(WRITESEQ1, GETCODEDATA1);
+	write_flash(WRITESEQ2, GETCODEDATA2);
+	write_flash(WRITESEQ3, GETCODEDATA3);
+
+	read_flash(0x0002, &dev_id);
+	dev_id &= 0x00FF;
+
+	reset_flash();
+
+	return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+
+	if (ulOffset >= SecFlashAOff) {
+		if ((ulOffset < SecFlashASec1Off)
+			&& (ulOffset < SecFlashASec2Off)) {
+				nSector = SECT32;
+		} else if ((ulOffset >= SecFlashASec2Off)
+			&& (ulOffset < SecFlashASec3Off)) {
+				nSector = SECT33;
+		} else if ((ulOffset >= SecFlashASec3Off)
+			&& (ulOffset < SecFlashASec4Off)) {
+				nSector = SECT34;
+		} else if ((ulOffset >= SecFlashASec4Off)
+			&& (ulOffset < SecFlashAEndOff)) {
+				nSector = SECT35;
+		}
+	} else if (ulOffset >= SecFlashBOff) {
+		if ((ulOffset < SecFlashBSec1Off)
+			&& (ulOffset < SecFlashBSec2Off)) {
+				nSector = SECT36;
+		}
+		if ((ulOffset < SecFlashBSec2Off)
+			&& (ulOffset < SecFlashBSec3Off)) {
+				nSector = SECT37;
+		}
+		if ((ulOffset < SecFlashBSec3Off)
+			&& (ulOffset < SecFlashBSec4Off)) {
+				nSector = SECT38;
+		}
+		if ((ulOffset < SecFlashBSec4Off)
+			&& (ulOffset < SecFlashBEndOff)) {
+				nSector = SECT39;
+		}
+	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+		nSector = ulOffset & 0xffff0000;
+		nSector = ulOffset >> 16;
+		nSector = nSector & 0x000ff;
+	}
+
+	if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+		*pnSector = nSector;
+	}
+}
diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h
new file mode 100644
index 0000000..9ae678b
--- /dev/null
+++ b/board/ezkit533/psd4256.h
@@ -0,0 +1,68 @@
+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTA_DIN	0x070000
+#define	PSD_PORTA_DOUT	0x070004
+#define	PSD_PORTA_DIR	0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTB_DIN	0x070001
+#define	PSD_PORTB_DOUT	0x070005
+#define	PSD_PORTB_DIR	0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define	PSDA_PPICLK1	0x20		/* PPI Clock select bit 1		*/
+#define	PSDA_PPICLK0	0x10		/* PPI Clock select bit 0		*/
+#define	PSDA_VDEC_RST	0x08		/* Video decoder reset, 0 = RESET	*/
+#define	PSDA_VENC_RST	0x04		/* Video encoder reset, 0 = RESET	*/
+#define	PSDA_CODEC_RST	0x01		/* Codec reset, 0 = RESET		*/
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define	PSDA_LED9	0x20		/* LED 9, 1 = LED ON			*/
+#define	PSDA_LED8	0x10		/* LED 8, 1 = LED ON			*/
+#define	PSDA_LED7	0x08		/* LED 7, 1 = LED ON			*/
+#define	PSDA_LED6	0x04		/* LED 6, 1 = LED ON			*/
+#define	PSDA_LED5	0x02		/* LED 5, 1 = LED ON			*/
+#define	PSDA_LED4	0x01		/* LED 4, 1 = LED ON			*/
+
diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds
new file mode 100644
index 0000000..f58b489
--- /dev/null
+++ b/board/ezkit533/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf533/start.o		(.text)
+    cpu/bf533/start1.o		(.text)
+    cpu/bf533/traps.o		(.text)
+    cpu/bf533/interrupt.o	(.text)
+    cpu/bf533/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    board/ezkit533/ezkit533.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/board/stamp/Makefile b/board/stamp/Makefile
new file mode 100644
index 0000000..ab97e1b
--- /dev/null
+++ b/board/stamp/Makefile
@@ -0,0 +1,68 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o stamp.o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/stamp/config.mk b/board/stamp/config.mk
new file mode 100644
index 0000000..4ec82cb
--- /dev/null
+++ b/board/stamp/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x07FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+
diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c
new file mode 100644
index 0000000..8485f58
--- /dev/null
+++ b/board/stamp/stamp.c
@@ -0,0 +1,278 @@
+/*
+ * U-boot - stamp.c STAMP board specific routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mem_init.h>
+#include "stamp.h"
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON  1 	
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)	
+#endif
+
+int checkboard(void)
+{
+	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf("Board: ADI BF533 Stamp board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	printf("       Richard Klingler <richard@uclinux.net>\n");
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	printf("SDRAM attributes:\n");
+	printf("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+		"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
+	(SDRAM_tRAS >> 6), ( SDRAM_tWR >> 19), (SDRAM_CL >> 2 ));
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", 128);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return (gd->bd->bi_memsize);
+}
+
+void swap_to(int device_id)
+{
+
+	if (device_id == ETHERNET)
+	{
+		*pFIO_DIR = PF0;
+		asm("ssync;");
+		*pFIO_FLAG_S = PF0;
+		asm("ssync;");
+	}
+	else if (device_id == FLASH)
+	{
+		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
+		*pFIO_FLAG_S = (PF4 | PF3 | PF2 );
+		*pFIO_MASKA_D = (PF8 | PF6 | PF5);
+		*pFIO_MASKB_D = (PF7);
+		*pFIO_POLAR = (PF8 | PF6 | PF5 );
+		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
+		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
+		*pFIO_FLAG_D = (PF4 | PF3 | PF2 );
+		asm("ssync;");
+	}
+	else {
+		printf("Unknown bank to switch\n");
+	}	
+	
+	return;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	int i;
+	int cf_stat = 0;
+
+	/* Check whether CF card is inserted */
+	*pFIO_EDGE = FIO_EDGE_CF_BITS;
+	*pFIO_POLAR = FIO_POLAR_CF_BITS;
+	for (i=0; i < 0x300 ; i++) asm("nop;");
+			
+	if ( (*pFIO_FLAG_S) & CF_STAT_BITS)
+	{
+		cf_stat = 0;
+	}
+	else
+	{
+		cf_stat = 1;
+	}
+
+	*pFIO_EDGE  = FIO_EDGE_BITS;
+	*pFIO_POLAR = FIO_POLAR_BITS;
+	
+
+	if (cf_stat)
+	{
+                printf ("Booting from COMPACT flash\n");
+
+		/* Set cycle time for CF */
+		*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
+
+		for (i=0; i < 0x1000 ; i++) asm("nop;");
+		for (i=0; i < 0x1000 ; i++) asm("nop;");
+		for (i=0; i < 0x1000 ; i++) asm("nop;");
+
+		serial_setbrg();
+		ide_init();
+
+		setenv ("bootargs", "");
+		setenv ("bootcmd", "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000" );
+	}
+	else
+        {
+		printf ("Booting from FLASH\n");
+	}
+
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_STAMP_CF
+
+void cf_outb(unsigned char val, volatile unsigned char* addr)
+{
+	/* 
+	 * Set PF1 PF0 respectively to 0 1 to divert address
+	 * to the expansion memory banks  
+	 */
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	*(addr) = val;
+	asm("ssync;");
+
+	/* Setback PF1 PF0 to 0 0 to address external 
+	 * memory banks  */
+	*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+	volatile unsigned char c;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	c = *(addr);
+	asm("ssync;");
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+
+	return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+	int i;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	for (i = 0;i < words; i++)
+	{
+		*(sect_buf + i) = *(addr);
+		asm("ssync;");
+	}
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+	int i;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	for (i = 0;i < words; i++)
+	{
+		*(addr) = *(sect_buf + i);
+		asm("ssync;");
+	}
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+}
+#endif
+
+void stamp_led_set(int LED1, int LED2, int LED3)
+{
+	*pFIO_INEN  &= ~( PF2 | PF3 | PF4);
+	*pFIO_DIR   |=  ( PF2 | PF3 | PF4);
+	
+	if(LED1 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF2;
+	else
+		*pFIO_FLAG_C = PF2;
+	if(LED2 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF3;
+	else
+		*pFIO_FLAG_C = PF3;
+	if(LED3 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF4;
+	else
+		*pFIO_FLAG_C = PF4;
+	asm("ssync;");
+}
+
+void show_boot_progress(int status)
+{
+	switch(status){
+		case 1:	
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_ON);
+			break;
+		case 2:
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_OFF);
+			break;
+		case 3:
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_ON);
+			break;	
+		case 4:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_OFF);			
+			break;
+		case 5:
+		case 6:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_ON);			
+			break;
+		case 7:
+		case 8:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_OFF);			
+			break;
+		case 9:
+		case 10:
+		case 11:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_OFF);			
+			break;
+		default:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_ON);			
+			break;
+	}
+}
+
diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h
new file mode 100644
index 0000000..7bc33b4
--- /dev/null
+++ b/board/stamp/stamp.h
@@ -0,0 +1,57 @@
+/*
+ * U-boot - stamp.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __STAMP_H__
+#define __STAMP_H__
+
+extern void init_Flags(void);
+
+extern volatile unsigned long *ambctl0;
+extern volatile unsigned long *ambctl1;
+extern volatile unsigned long *amgctl;
+
+extern unsigned long pll_div_fact;
+extern void serial_setbrg(void);
+extern void pll_set(int vco, int crystal_frq, int pll_div);
+
+/* Definitions used in  Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS 	0x0000
+#define FIO_POLAR_CF_BITS 	0x0000
+#define	FIO_EDGE_BITS  		0x1E0
+#define	FIO_POLAR_BITS  	0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS 		0x00000060
+
+/* CF Flags used to switch between expansion and external
+ * memory banks
+ */
+#define CF_PF0			0x0001
+#define CF_PF1			0x0002
+#define CF_PF1_PF0		0x0003
+
+#endif
diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds
new file mode 100644
index 0000000..ad6886f
--- /dev/null
+++ b/board/stamp/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf533/start.o		(.text)
+    cpu/bf533/start1.o		(.text)
+    cpu/bf533/traps.o		(.text)
+    cpu/bf533/interrupt.o	(.text)
+    cpu/bf533/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile
new file mode 100644
index 0000000..c63a8f6
--- /dev/null
+++ b/cpu/bf533/Makefile
@@ -0,0 +1,46 @@
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
+OBJS	= cpu.o traps.o ints.o serial.o interrupts.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h
new file mode 100644
index 0000000..ec63a5e
--- /dev/null
+++ b/cpu/bf533/bf533_serial.h
@@ -0,0 +1,78 @@
+/*
+ * U-boot - bf533_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on 
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003	Bas Vermeulen <bas@buyways.nl>
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001	Tony Z. Kou	tonyko@arcturusnetworks.com
+ * Copyright (C) 2001   Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf533_SERIAL_H
+#define _Bf533_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+extern int get_clock(void);
+int baud_table[5] = {9600, 19200, 38400, 57600, 115200};
+
+struct {
+	unsigned char dl_high;
+	unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
new file mode 100644
index 0000000..1822d1f
--- /dev/null
+++ b/cpu/bf533/cache.S
@@ -0,0 +1,125 @@
+
+
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <asm/cpu/def_LPBlackfin.h>
+
+.text
+.align 2
+ENTRY(blackfin_icache_flush_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	IFLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	IFLUSH[P0];
+	SSYNC;
+	RTS;
+
+ENTRY(blackfin_dcache_flush_range)
+	R2 = -32;
+        R2 = R0 & R2;
+        P0 = R2;
+        P1 = R1;
+        CSYNC;
+1:
+        FLUSH[P0++];
+        CC = P0 < P1(iu);
+        IF CC JUMP 1b(bp);
+        FLUSH[P0];
+        SSYNC;
+        RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(invalidate_entire_icache)
+        [--SP] = ( R7:5);
+                                                                                                                                                             
+        P0.L = (IMEM_CONTROL & 0xFFFF);
+        P0.H = (IMEM_CONTROL >> 16);
+        R7 = [P0];
+                                                                                                                                                             
+        /* Clear the IMC bit , All valid bits in the instruction
+         * cache are set to the invalid state
+         */
+        BITCLR(R7,IMC_P);
+        CLI R6;
+        SSYNC;          /* SSYNC required before invalidating cache. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        /* Configures the instruction cache agian */
+        R6 = (IMC | ENICPLB);
+        R7 = R7 | R6;
+                                                                                                                                                             
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        ( R7:5) = [SP++];
+        RTS;
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+        [--SP] = ( R7:6);
+                                                                                                                                                             
+        P0.L = (DMEM_CONTROL & 0xFFFF);
+        P0.H = (DMEM_CONTROL >> 16);
+        R7 = [P0];
+                                                                                                                                                             
+        /* Clear the DMC[1:0] bits, All valid bits in the data
+         * cache are set to the invalid state
+         */
+        BITCLR(R7,DMC0_P);
+        BITCLR(R7,DMC1_P);
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        /* Configures the data cache again */
+                                                                                                                                                             
+        R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+        R7 = R7 | R6;
+                                                                                                                                                             
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        ( R7:6) = [SP++];
+        RTS;
+
+ENTRY(blackfin_dcache_invalidate_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	FLUSHINV[P0++];
+	CC = P0 < P1 (iu);
+	IF CC JUMP 1b (bp);
+
+	/* If the data crosses a cache line, then we'll be pointing to
+	** the last cache line, but won't have flushed/invalidated it yet, so do
+	** one more.
+	*/
+	FLUSHINV[P0];
+	SSYNC;
+	RTS;
diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk
new file mode 100644
index 0000000..a9d529e
--- /dev/null
+++ b/cpu/bf533/config.mk
@@ -0,0 +1,27 @@
+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-P5
diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S
new file mode 100644
index 0000000..b5abbbc
--- /dev/null
+++ b/cpu/bf533/cplbhdlr.S
@@ -0,0 +1,194 @@
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. 
+ *
+ * Blackfin BF533/2.6 support : LG Soft India	
+ */
+
+
+/* Include an exception handler to invoke the CPLB manager
+ */
+
+#include <asm-blackfin/linkage.h>
+#include <asm/cplb.h>
+#include <asm/entry.h>
+
+
+.text
+ 
+.globl _cplb_hdr;
+.type _cplb_hdr, STT_FUNC;
+.extern _cplb_mgr;
+.type _cplb_mgr, STT_FUNC;
+.extern __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+.extern __cplb_miss_all_locked;
+.type __cplb_miss_all_locked, STT_FUNC;
+.extern __cplb_miss_without_replacement;
+.type __cplb_miss_without_replacement, STT_FUNC;
+.extern __cplb_protection_violation;
+.type __cplb_protection_violation, STT_FUNC;
+.extern panic_pv;
+
+.align 2;
+
+ENTRY(_cplb_hdr)
+	SSYNC;
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = ASTAT;
+	[--SP] = SEQSTAT;
+	[--SP] = I0;
+	[--SP] = I1;
+	[--SP] = I2;
+	[--SP] = I3;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC0;
+	[--SP] = LT1;
+	[--SP] = LB1;
+	[--SP] = LC1;
+	R2 = SEQSTAT;
+
+	/*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
+	R2 <<= 26;
+	R2 >>= 26;
+
+	R1 = 0x23; /* Data access CPLB protection violation */
+	CC = R2 == R1;
+	IF !CC JUMP not_data_write;
+	R0 = 2;		/* is a write to data space*/
+	JUMP is_icplb_miss;
+
+not_data_write:
+	R1 = 0x2C; /* CPLB miss on an instruction fetch */
+	CC = R2 == R1;
+	R0 = 0;		/* is_data_miss == False*/
+	IF CC JUMP is_icplb_miss;
+
+	R1 = 0x26;
+	CC = R2 == R1;
+	IF !CC JUMP unknown;
+
+	R0 = 1;		/* is_data_miss == True*/
+
+is_icplb_miss:
+
+#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
+#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
+	R1 = CPLB_ENABLE_ICACHE; 
+#endif
+#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+	R1 = CPLB_ENABLE_DCACHE; 
+#endif
+#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+	R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; 
+#endif
+#else
+	R1 = 0;
+#endif
+
+	[--SP] = RETS;			
+	CALL _cplb_mgr;
+	RETS = [SP++];
+	CC = R0 == 0;
+	IF !CC JUMP not_replaced;
+	LC1 = [SP++];
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC0 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	I3 = [SP++];
+	I2 = [SP++];
+	I1 = [SP++];
+	I0 = [SP++];
+	SEQSTAT = [SP++];
+	ASTAT = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+unknown:
+	[--SP] = RETS;			
+	CALL __unknown_exception_occurred;
+	RETS = [SP++];
+	JUMP unknown;
+not_replaced:
+	CC = R0 == CPLB_NO_UNLOCKED;
+	IF !CC JUMP next_check;
+	[--SP] = RETS;			
+	CALL __cplb_miss_all_locked;
+	RETS = [SP++];
+next_check:
+	CC = R0 == CPLB_NO_ADDR_MATCH;
+	IF !CC JUMP next_check2;
+	[--SP] = RETS;			
+	CALL __cplb_miss_without_replacement;
+	RETS = [SP++];
+	JUMP not_replaced;
+next_check2:
+	CC = R0 == CPLB_PROT_VIOL;
+	IF !CC JUMP strange_return_from_cplb_mgr;
+	[--SP] = RETS;			
+	CALL __cplb_protection_violation;
+	RETS = [SP++];
+	JUMP not_replaced;
+strange_return_from_cplb_mgr:
+	IDLE;
+	CSYNC;
+	JUMP strange_return_from_cplb_mgr;
+
+/************************************
+ * Diagnostic exception handlers 
+ */	
+
+__cplb_miss_all_locked:
+	sp += -12;
+	R0 = CPLB_NO_UNLOCKED;
+	call panic_bfin;
+	SP += 12;
+	RTS;
+
+ __cplb_miss_without_replacement:
+	sp += -12;
+	R0 = CPLB_NO_ADDR_MATCH;
+	call panic_bfin;
+	SP += 12;
+	RTS;
+
+__cplb_protection_violation:
+	sp += -12;
+	R0 = CPLB_PROT_VIOL;
+	call panic_bfin;
+	SP += 12;
+	RTS;
+
+__unknown_exception_occurred:
+
+	/* This function is invoked by the default exception
+	 * handler, if it does not recognise the kind of
+	 * exception that has occurred. In other words, the
+	 * default handler only handles some of the system's
+	 * exception types, and it does not expect any others
+	 * to occur. If your application is going to be using
+	 * other kinds of exceptions, you must replace the
+	 * default handler with your own, that handles all the
+	 * exceptions you will use.
+	 * 
+	 * Since there's nothing we can do, we just loop here
+	 * at what we hope is a suitably informative label.
+	 */
+	
+	IDLE;
+do_not_know_what_to_do:
+	CSYNC;
+	JUMP __unknown_exception_occurred;
+
+	RTS;
+.__unknown_exception_occurred.end:
+.global __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+
+panic_bfin:
+	RTS;
+
diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S
new file mode 100644
index 0000000..fc3e3a8
--- /dev/null
+++ b/cpu/bf533/cplbmgr.S
@@ -0,0 +1,601 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Modification: Dec 07 2004
+ *	1. Correction in icheck_lock.  Valid lock entries were 
+ *	   geting victimized, for instruction cplb replacement.
+ *	2. Setup loop's are modified as now toolchain support's P Indexed
+ *	   addressing
+ *	   :LG Soft India
+ *
+ */
+
+/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
+ * is_data_miss==2 => Mark as Dirty, write to the clean data page
+ * is_data_miss==1 => Replace a data CPLB.
+ * is_data_miss==0 => Replace an instruction CPLB.
+ *
+ * Returns:
+ * CPLB_RELOADED	=> Successfully updated CPLB table.
+ * CPLB_NO_UNLOCKED	=> All CPLBs are locked, so cannot be evicted.This indicates 
+ *				that the CPLBs in the configuration tablei are badly 
+ *				configured, as this should never occur.
+ * CPLB_NO_ADDR_MATCH	=> The address being accessed, that triggered the exception, 
+ *				is not covered by any of the CPLBs in the configuration 
+ *				table. The application isi presumably misbehaving.
+ * CPLB_PROT_VIOL	=> The address being accessed, that triggered thei exception, 
+ *				was not a first-write to a clean Write Back Data page, 
+ *				and so presumably is a genuine violation of the page's 
+ *				protection attributes. The application is misbehaving.
+ */
+#define ASSEMBLY
+
+#include <asm-blackfin/linkage.h>
+#include <asm-blackfin/blackfin.h>
+#include <asm-blackfin/cplbtab.h>
+#include <asm-blackfin/cplb.h>
+ 	
+.text
+ 
+.align 2;
+ENTRY(_cplb_mgr)
+
+	[--SP]=( R7:0,P5:0 );
+
+	CC = R0 == 2;
+	IF CC JUMP dcplb_write;
+
+	CC = R0 == 0;
+	IF !CC JUMP dcplb_miss_compare;
+
+	/* ICPLB Miss Exception. We need to choose one of the
+	* currently-installed CPLBs, and replace it with one
+	* from the configuration table.	
+ 	*/
+
+	P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
+	P4.H = (ICPLB_FAULT_ADDR >> 16);
+
+	P1 = 16;
+	P5.L = page_size_table;
+	P5.H = page_size_table;
+
+	P0.L = (ICPLB_DATA0 & 0xFFFF);
+	P0.H = (ICPLB_DATA0 >> 16);
+	R4 = [P4];		/* Get faulting address*/
+	R6 = 64;		/* Advance past the fault address, which*/
+	R6 = R6 + R4;		/* we'll use if we find a match*/
+	R3 = ((16 << 8) | 2);	/* Extract mask, bits 16 and 17.*/
+
+	R5 = 0;
+isearch:
+
+	R1 = [P0-0x100];	/* Address for this CPLB */
+	
+	R0 = [P0++];		/* Info for this CPLB*/
+	CC = BITTST(R0,0);	/* Is the CPLB valid?*/
+	IF !CC JUMP nomatch;	/* Skip it, if not.*/
+	CC = R4 < R1(IU);	/* If fault address less than page start*/
+	IF CC JUMP nomatch;	/* then skip this one.*/
+	R2 = EXTRACT(R0,R3.L) (Z);	/* Get page size*/
+	P1 = R2;
+	P1 = P5 + (P1<<2);	/* index into page-size table*/
+	R2 = [P1];		/* Get the page size*/
+	R1 = R1 + R2;		/* and add to page start, to get page end*/
+	CC = R4 < R1(IU);	/* and see whether fault addr is in page.*/
+	IF !CC R4 = R6;		/* If so, advance the address and finish loop.*/
+	IF !CC JUMP isearch_done;
+nomatch:
+	/* Go around again*/
+	R5 += 1;
+	CC = BITTST(R5, 4);	/* i.e CC = R5 >= 16*/
+	IF !CC JUMP isearch;
+
+isearch_done:
+	I0 = R4;		/* Fault address we'll search for*/
+	
+	/* set up pointers */
+	P0.L = (ICPLB_DATA0 & 0xFFFF);
+	P0.H = (ICPLB_DATA0 >> 16);
+
+	/* The replacement procedure for ICPLBs */
+
+	P4.L = (IMEM_CONTROL & 0xFFFF);
+	P4.H = (IMEM_CONTROL >> 16);
+
+	/* disable cplbs */
+	R5 = [P4];		/* Control Register*/
+	BITCLR(R5,ENICPLB_P);
+	CLI R1;
+	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R1;
+
+	R1 = -1;		/* end point comparison */
+	R3 = 16;		/* counter */
+
+	/* Search through CPLBs for first non-locked entry */
+	/* Overwrite it by moving everyone else up by 1 */
+icheck_lock:
+	R0 = [P0++];
+	R3 = R3 + R1;
+	CC = R3 == R1;
+	IF CC JUMP all_locked;
+	CC = BITTST(R0, 0);		/* an invalid entry is good */
+	IF !CC JUMP ifound_victim;
+	CC = BITTST(R0,1);		/* but a locked entry isn't */
+	IF CC JUMP icheck_lock;
+
+ifound_victim:
+#ifdef CONFIG_CPLB_INFO
+	R7 = [P0 - 0x104];
+	P2.L = ipdt_table;
+	P2.H = ipdt_table;
+	P3.L = ipdt_swapcount_table;
+	P3.H = ipdt_swapcount_table;
+	P3 += -4;
+icount:
+	R2 = [P2];	/* address from config table */			
+	P2 += 8;
+	P3 += 8;
+	CC = R2==-1;
+	IF CC JUMP icount_done;
+	CC = R7==R2;
+	IF !CC JUMP icount;
+	R7 = [P3];
+	R7 += 1;
+	[P3] = R7;
+	CSYNC;
+icount_done:
+#endif
+	LC0=R3;
+	LSETUP(is_move,ie_move) LC0;
+is_move: 
+	R0 = [P0];
+	[P0 - 4] = R0;
+	R0 = [P0 - 0x100];
+	[P0-0x104] = R0; 
+ie_move:P0+=4;
+	
+	/* We've made space in the ICPLB table, so that ICPLB15
+	 * is now free to be overwritten. Next, we have to determine
+	 * which CPLB we need to install, from the configuration
+	 * table. This is a matter of getting the start-of-page
+	 * addresses and page-lengths from the config table, and
+	 * determining whether the fault address falls within that
+	 * range.
+ 	 */
+	
+	P2.L = ipdt_table;
+	P2.H = ipdt_table;
+#ifdef	CONFIG_CPLB_INFO
+	P3.L = ipdt_swapcount_table;
+	P3.H = ipdt_swapcount_table;
+	P3 += -8;
+#endif
+	P0.L = page_size_table;
+	P0.H = page_size_table;
+
+	/* Retrieve our fault address (which may have been advanced
+	 * because the faulting instruction crossed a page boundary).
+	 */
+
+	R0 = I0;
+
+	/* An extraction pattern, to get the page-size bits from
+	 * the CPLB data entry. Bits 16-17, so two bits at posn 16.
+	 */
+
+	R1 = ((16<<8)|2);
+inext:	R4 = [P2++];	/* address from config table */			
+	R2 = [P2++];	/* data from config table */
+#ifdef	CONFIG_CPLB_INFO
+	P3 += 8;
+#endif
+
+	CC = R4 == -1;	/* End of config table*/
+	IF CC JUMP no_page_in_table;
+
+	/* See if failed address > start address */
+	CC = R4 <= R0(IU);
+ 	IF !CC JUMP inext;
+
+	/* extract page size (17:16)*/
+	R3 = EXTRACT(R2, R1.L) (Z);
+
+	/* add page size to addr to get range */
+
+	P5 = R3;
+	P5 = P0 + (P5 << 2);	/* scaled, for int access*/
+	R3 = [P5];
+	R3 = R3 + R4;
+
+	/* See if failed address < (start address + page size) */
+	CC = R0 < R3(IU);
+	IF !CC JUMP inext;
+
+	/* We've found a CPLB in the config table that covers
+	 * the faulting address, so install this CPLB into the
+	 * last entry of the table.
+	 */
+
+	P1.L = (ICPLB_DATA15 & 0xFFFF);		/*ICPLB_DATA15*/
+	P1.H = (ICPLB_DATA15 >> 16);
+	[P1] = R2;
+	[P1-0x100] = R4;
+#ifdef	CONFIG_CPLB_INFO
+	R3 = [P3];
+	R3 += 1;
+	[P3] = R3;
+#endif
+
+	/* P4 points to IMEM_CONTROL, and R5 contains its old
+	 * value, after we disabled ICPLBS. Re-enable them.
+	 */
+
+	BITSET(R5,ENICPLB_P);
+	CLI R2;
+	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R2;
+
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_RELOADED;
+	RTS;
+
+/* FAILED CASES*/
+no_page_in_table:
+        ( R7:0,P5:0 ) = [SP++];
+        R0 = CPLB_NO_ADDR_MATCH;
+        RTS;
+all_locked:
+        ( R7:0,P5:0 ) = [SP++];
+        R0 = CPLB_NO_UNLOCKED;
+        RTS;
+prot_violation:
+        ( R7:0,P5:0 ) = [SP++];
+        R0 = CPLB_PROT_VIOL;
+        RTS;
+
+dcplb_write:
+
+	/* if a DCPLB is marked as write-back (CPLB_WT==0), and
+	 * it is clean (CPLB_DIRTY==0), then a write to the
+	 * CPLB's page triggers a protection violation. We have to
+	 * mark the CPLB as dirty, to indicate that there are
+	 * pending writes associated with the CPLB.
+	 */
+
+	P4.L = (DCPLB_STATUS & 0xFFFF);
+	P4.H = (DCPLB_STATUS >> 16);
+	P3.L = (DCPLB_DATA0 & 0xFFFF);
+	P3.H = (DCPLB_DATA0 >> 16);
+	R5 = [P4];	
+
+	/* A protection violation can be caused by more than just writes
+	 * to a clean WB page, so we have to ensure that:
+	 * - It's a write
+	 * - to a clean WB page
+	 * - and is allowed in the mode the access occurred.
+	 */
+
+	CC = BITTST(R5, 16);	/* ensure it was a write*/
+	IF !CC JUMP prot_violation;
+
+	/* to check the rest, we have to retrieve the DCPLB.*/
+
+	/* The low half of DCPLB_STATUS is a bit mask*/
+
+	R2 = R5.L (Z);	/* indicating which CPLB triggered the event.*/
+	R3 = 30;	/* so we can use this to determine the offset*/
+	R2.L = SIGNBITS R2;
+	R2 = R2.L (Z);	/* into the DCPLB table.*/
+	R3 = R3 - R2;
+	P4 = R3;
+	P3 = P3 + (P4<<2);
+	R3 = [P3];	/* Retrieve the CPLB*/
+
+	/* Now we can check whether it's a clean WB page*/
+
+	CC = BITTST(R3, 14);	/* 0==WB, 1==WT*/
+	IF CC JUMP prot_violation;
+	CC = BITTST(R3, 7);	/* 0 == clean, 1 == dirty*/
+	IF CC JUMP prot_violation;
+
+	/* Check whether the write is allowed in the mode that was active.*/
+
+	R2 = 1<<3;		/* checking write in user mode*/
+	CC = BITTST(R5, 17);	/* 0==was user, 1==was super*/
+	R5 = CC;
+	R2 <<= R5;		/* if was super, check write in super mode*/
+	R2 = R3 & R2;
+	CC = R2 == 0;
+	IF CC JUMP prot_violation;	
+
+	/* It's a genuine write-to-clean-page.*/
+
+	BITSET(R3, 7);		/* mark as dirty*/
+	[P3] = R3;		/* and write back.*/
+	CSYNC;
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_RELOADED;
+	RTS;
+
+dcplb_miss_compare:
+
+	/* Data CPLB Miss event. We need to choose a CPLB to
+	 * evict, and then locate a new CPLB to install from the
+	 * config table, that covers the faulting address.
+	 */
+
+	P1.L = (DCPLB_DATA15 & 0xFFFF);	
+	P1.H = (DCPLB_DATA15 >> 16);
+
+	P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
+	P4.H = (DCPLB_FAULT_ADDR >> 16);
+	R4 = [P4];
+	I0 = R4;
+
+	/* The replacement procedure for DCPLBs*/
+
+	R6 = R1;	/* Save for later*/
+
+	/* Turn off CPLBs while we work.*/
+	P4.L = (DMEM_CONTROL & 0xFFFF);
+	P4.H = (DMEM_CONTROL >> 16);
+	R5 = [P4];
+	BITCLR(R5,ENDCPLB_P);
+	CLI R0;
+	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R0;
+
+	/* Start looking for a CPLB to evict. Our order of preference
+	 * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
+	 * are no good.
+	 */
+
+	I1.L = (DCPLB_DATA0 & 0xFFFF);
+	I1.H = (DCPLB_DATA0 >> 16);
+	P1 = 3;
+	P2 = 16;
+	I2.L = dcplb_preference;
+	I2.H = dcplb_preference;
+	LSETUP(sdsearch1, edsearch1) LC0 = P1;
+sdsearch1:
+	R0 = [I2++];		/* Get the bits we're interested in*/
+	P0 = I1;		/* Go back to start of table*/
+	LSETUP (sdsearch2, edsearch2) LC1 = P2;
+sdsearch2:
+	R1 = [P0++];		/* Fetch each installed CPLB in turn*/
+	R2 = R1 & R0;		/* and test for interesting bits.*/
+	CC = R2 == 0;		/* If none are set, it'll do.*/
+	IF !CC JUMP skip_stack_check;
+
+	R2 = [P0 - 0x104]; 	/* R2 - PageStart */
+	P3.L = page_size_table; /* retrive end address */
+	P3.H = page_size_table; /* retrive end address */
+	R3 = 0x2;		/* 0th - position, 2 bits -length */
+	nop;			/*Anamoly 05000209*/
+	R7 = EXTRACT(R1,R3.l);
+	R7 = R7 << 2;		/* Page size index offset */
+	P5 = R7;
+	P3 = P3 + P5;
+	R7 = [P3];		/* page size in 1K bytes */
+
+	R7 = R7 << 0xA;		/* in bytes * 1024*/
+	R7 = R2 + R7;		/* R7 - PageEnd */
+	R4 = SP; 		/* Test SP is in range */
+
+	CC = R7 < R4;		/* if PageEnd < SP */
+	IF CC JUMP dfound_victim;
+	R3 = 0x284;		/* stack length from start of trap till the point */
+				/* 20 stack locations for future modifications */
+	R4 = R4 + R3;	
+	CC = R4 < R2;		/* if SP + stacklen < PageStart */
+	IF CC JUMP dfound_victim;
+skip_stack_check:
+
+edsearch2: NOP;
+edsearch1: NOP;
+
+	/* If we got here, we didn't find a DCPLB we considered
+	 * replacable, which means all of them were locked.
+	 */
+	
+	JUMP all_locked;
+dfound_victim:
+
+#ifdef CONFIG_CPLB_INFO
+	R1 = [P0 - 0x104];
+	P2.L = dpdt_table;
+	P2.H = dpdt_table;
+	P3.L = dpdt_swapcount_table;
+	P3.H = dpdt_swapcount_table;
+	P3 += -4;
+dicount:
+	R2 = [P2];
+	P2 += 8;
+	P3 += 8;
+	CC = R2==-1;
+	IF CC JUMP dicount_done;
+	CC = R1==R2;
+	IF !CC JUMP dicount;
+	R1 = [P3];
+	R1 += 1;
+	[P3] = R1;
+	CSYNC;
+dicount_done:
+#endif
+
+	/* Clean down the hardware loops*/
+	R2 = 0;
+	LC1 = R2;
+	LC0 = R2;
+
+	/* There's a suitable victim in [P0-4] (because we've
+	 * advanced already). If it's a valid dirty write-back
+	 * CPLB, we need to flush the pending writes first.
+	 */
+
+	CC = BITTST(R1, 0);	/* Is it valid?*/
+	IF !CC JUMP Ddoverwrite;/* nope.*/
+	CC = BITTST(R1, 7);	/* Is it dirty?*/
+	IF !CC JUMP Ddoverwrite (BP);	/* Nope.*/
+	CC = BITTST(R1, 14);	/* Is it Write-Through?*/
+	IF CC JUMP Ddoverwrite;	/* Yep*/
+
+	/* This is a dirty page, so we need to flush all writes
+	 * that are pending on the page.
+	 */
+
+	/* Retrieve the page start address*/
+        R0 = [P0 - 0x104];
+	[--sp] = rets;
+	CALL dcplb_flush;	/* R0==CPLB addr, R1==CPLB data*/
+	rets = [sp++];
+Ddoverwrite:
+
+	/* [P0-4] is a suitable victim CPLB, so we want to
+	 * overwrite it by moving all the following CPLBs
+	 * one space closer to the start.
+	 */
+	
+	R1.L = ((DCPLB_DATA15+4) & 0xFFFF);		/*DCPLB_DATA15+4*/
+	R1.H = ((DCPLB_DATA15+4) >> 16);
+	R0 = P0;
+
+	/* If the victim happens to be in DCPLB15,
+	 * we don't need to move anything.
+	 */
+
+	CC = R1 == R0;
+	IF CC JUMP de_moved;
+	R1 = R1 - R0;
+	R1 >>= 2;
+	P1 = R1;
+	LSETUP(ds_move, de_move) LC0=P1;
+ds_move:
+	 R0 = [P0++];	/* move data */
+	[P0 - 8] = R0;
+	R0 = [P0-0x104]	/* move address */
+de_move: [P0-0x108] = R0;
+
+	/* We've now made space in DCPLB15 for the new CPLB to be
+	 * installed. The next stage is to locate a CPLB in the
+	 * config table that covers the faulting address.
+	 */
+
+de_moved:NOP;
+	R0 = I0;		/* Our faulting address */
+
+	P2.L = dpdt_table;
+	P2.H = dpdt_table;
+#ifdef	CONFIG_CPLB_INFO
+	P3.L = dpdt_swapcount_table;
+	P3.H = dpdt_swapcount_table;
+	P3 += -8;
+#endif
+
+	P1.L = page_size_table;
+	P1.H = page_size_table;
+
+	/* An extraction pattern, to retrieve bits 17:16.*/
+
+	R1 = (16<<8)|2;
+dnext:	R4 = [P2++];	/* address */			
+	R2 = [P2++];	/* data */
+#ifdef	CONFIG_CPLB_INFO
+	P3 += 8;
+#endif
+
+	CC = R4 == -1;
+	IF CC JUMP no_page_in_table;
+
+	/* See if failed address > start address */
+	CC = R4 <= R0(IU);
+ 	IF !CC JUMP dnext;
+
+	/* extract page size (17:16)*/
+	R3 = EXTRACT(R2, R1.L) (Z);
+
+	/* add page size to addr to get range */
+
+	P5 = R3;
+	P5 = P1 + (P5 << 2);
+	R3 = [P5];
+	R3 = R3 + R4;
+
+	/* See if failed address < (start address + page size) */
+	CC = R0 < R3(IU);
+	IF !CC JUMP dnext;
+
+	/* We've found the CPLB that should be installed, so
+	 * write it into CPLB15, masking off any caching bits
+	 * if necessary.
+	 */
+
+	P1.L = (DCPLB_DATA15 & 0xFFFF);
+	P1.H = (DCPLB_DATA15 >> 16);
+
+	/* If the DCPLB has cache bits set, but caching hasn't
+	 * been enabled, then we want to mask off the cache-in-L1
+	 * bit before installing. Moreover, if caching is off, we
+	 * also want to ensure that the DCPLB has WT mode set, rather
+	 * than WB, since WB pages still trigger first-write exceptions
+	 * even when not caching is off, and the page isn't marked as
+	 * cachable. Finally, we could mark the page as clean, not dirty,
+	 * but we choose to leave that decision to the user; if the user
+	 * chooses to have a CPLB pre-defined as dirty, then they always
+	 * pay the cost of flushing during eviction, but don't pay the
+	 * cost of first-write exceptions to mark the page as dirty.
+	 */
+
+#ifdef CONFIG_BLKFIN_WT
+	BITSET(R6, 14);		/* Set WT*/
+#endif
+
+	[P1] = R2;
+	[P1-0x100] = R4;
+#ifdef	CONFIG_CPLB_INFO
+	R3 = [P3];
+	R3 += 1;
+	[P3] = R3;
+#endif
+
+	/* We've installed the CPLB, so re-enable CPLBs. P4
+	 * points to DMEM_CONTROL, and R5 is the value we
+	 * last wrote to it, when we were disabling CPLBs.
+	 */
+
+	BITSET(R5,ENDCPLB_P);
+	CLI R2;
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R2;
+
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_RELOADED;
+	RTS;
+
+.data
+.align 4;
+page_size_table:
+.byte4	0x00000400;	/* 1K */
+.byte4	0x00001000;	/* 4K */
+.byte4	0x00100000;	/* 1M */
+.byte4	0x00400000;	/* 4M */
+
+.align 4;
+dcplb_preference:
+.byte4	0x00000001;	/* valid bit */
+.byte4	0x00000082;	/* dirty+lock bits */
+.byte4	0x00000002;	/* lock bit */
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
new file mode 100644
index 0000000..2c139f5
--- /dev/null
+++ b/cpu/bf533/cpu.c
@@ -0,0 +1,194 @@
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+
+#define SSYNC() asm("ssync;")
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+#define ANOMALY_05000158		0x200	
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+static unsigned int icplb_table[16][2]={
+			{0xFFA00000, L1_IMEMORY},
+			{0x00000000, SDRAM_IKERNEL},	/*SDRAM_Page1*/
+			{0x00400000, SDRAM_IKERNEL},	/*SDRAM_Page1*/
+			{0x07C00000, SDRAM_IKERNEL},    /*SDRAM_Page14*/
+			{0x00800000, SDRAM_IGENERIC},	/*SDRAM_Page2*/
+			{0x00C00000, SDRAM_IGENERIC},	/*SDRAM_Page2*/
+			{0x01000000, SDRAM_IGENERIC},	/*SDRAM_Page4*/
+			{0x01400000, SDRAM_IGENERIC},	/*SDRAM_Page5*/
+			{0x01800000, SDRAM_IGENERIC},	/*SDRAM_Page6*/
+			{0x01C00000, SDRAM_IGENERIC},	/*SDRAM_Page7*/
+			{0x02000000, SDRAM_IGENERIC},	/*SDRAM_Page8*/
+			{0x02400000, SDRAM_IGENERIC},	/*SDRAM_Page9*/
+			{0x02800000, SDRAM_IGENERIC},	/*SDRAM_Page10*/
+			{0x02C00000, SDRAM_IGENERIC},	/*SDRAM_Page11*/
+			{0x03000000, SDRAM_IGENERIC},	/*SDRAM_Page12*/
+			{0x03400000, SDRAM_IGENERIC},	/*SDRAM_Page13*/
+};
+
+static unsigned int dcplb_table[16][2]={
+			{0xFFA00000,L1_DMEMORY},	
+			{0x00000000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
+			{0x00400000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
+			{0x07C00000,SDRAM_DKERNEL},	/*SDRAM_Page15*/
+			{0x00800000,SDRAM_DGENERIC},	/*SDRAM_Page2*/
+			{0x00C00000,SDRAM_DGENERIC},	/*SDRAM_Page3*/
+			{0x01000000,SDRAM_DGENERIC},	/*SDRAM_Page4*/
+			{0x01400000,SDRAM_DGENERIC},	/*SDRAM_Page5*/
+			{0x01800000,SDRAM_DGENERIC},	/*SDRAM_Page6*/
+			{0x01C00000,SDRAM_DGENERIC},	/*SDRAM_Page7*/
+			{0x02000000,SDRAM_DGENERIC},	/*SDRAM_Page8*/
+			{0x02400000,SDRAM_DGENERIC},	/*SDRAM_Page9*/
+			{0x02800000,SDRAM_DGENERIC},	/*SDRAM_Page10*/
+			{0x02C00000,SDRAM_DGENERIC},	/*SDRAM_Page11*/
+			{0x03000000,SDRAM_DGENERIC},	/*SDRAM_Page12*/
+			{0x20000000,SDRAM_EBIU},	/*For Network */	
+};
+
+
+			
+			
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	__asm__ __volatile__
+	("cli r3;"
+	"P0 = %0;"
+	"JUMP (P0);"
+	:
+	: "r" (L1_ISRAM)
+	);
+
+	return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	return 0;
+}
+
+void icache_enable(void)
+{
+	unsigned int *I0,*I1;
+	int i;
+
+	I0 = (unsigned int *)ICPLB_ADDR0;
+	I1 = (unsigned int *)ICPLB_DATA0;
+	
+	for(i=0;i<16;i++){
+		*I0++ = icplb_table[i][0];
+		*I1++ = icplb_table[i][1];
+		}
+	cli();
+	SSYNC();
+	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+	SSYNC();
+	sti();
+}
+
+void icache_disable(void)
+{
+	cli();
+	SSYNC();
+	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+	SSYNC();
+	sti();
+}
+
+int icache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)IMEM_CONTROL;
+
+	if( value & (IMC|ENICPLB) )
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+	unsigned int *I0,*I1;
+	unsigned int temp;
+	int i;
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	for(i=0;i<16;i++){
+		*I0++ = dcplb_table[i][0];
+		*I1++ = dcplb_table[i][1];
+		}
+	cli();
+	temp = *(unsigned int *)DMEM_CONTROL; 
+	SSYNC();
+	*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
+	SSYNC();
+	sti();
+}
+		
+
+void dcache_disable(void)
+{
+	cli();
+	SSYNC();
+	*(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
+	SSYNC();
+	sti();
+}
+
+int dcache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)DMEM_CONTROL;
+	if( value & (ENDCPLB))
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h
new file mode 100644
index 0000000..7ec3387
--- /dev/null
+++ b/cpu/bf533/cpu.h
@@ -0,0 +1,65 @@
+/*
+ *  U-boot - cpu.h
+ *
+ *  Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+#define INTERNAL_IRQS (32)
+#define NUM_IRQ_NODES 16
+#define DEF_INTERRUPT_FLAGS 1
+#define MAX_TIM_LOAD	0xFFFFFFFF
+
+void blackfin_irq_panic(int reason, struct pt_regs * reg);
+extern void dump(struct pt_regs * regs);
+void display_excp(void);
+asmlinkage void evt_nmi(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_rst(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+void blackfin_irq_panic(int reason, struct pt_regs * regs);
+void blackfin_free_irq(unsigned int irq, void *dev_id);
+void call_isr(int irq, struct pt_regs * fp);
+void blackfin_do_irq(int vec, struct pt_regs *fp);
+void blackfin_init_IRQ(void);
+void blackfin_enable_irq(unsigned int irq);
+void blackfin_disable_irq(unsigned int irq);
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int blackfin_request_irq(unsigned int irq,
+		     void (*handler)(int, void *, struct pt_regs *),
+		     unsigned long flags,const char *devname,void *dev_id);
+void timer_init(void);
+#endif
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
new file mode 100644
index 0000000..1f9ec98
--- /dev/null
+++ b/cpu/bf533/flush.S
@@ -0,0 +1,402 @@
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ */
+#define ASSEMBLY
+
+#include <asm/linkage.h>
+#include <asm/cplb.h>
+#include <asm/blackfin.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the instruction cache.
+ */
+
+ENTRY(flush_instruction_cache)
+	[--SP] = ( R7:6, P5:4 );
+	LINK 12;
+	SP += -12;
+	P5.H = (ICPLB_ADDR0 >> 16);
+	P5.L = (ICPLB_ADDR0 & 0xFFFF);
+	P4.H = (ICPLB_DATA0 >> 16);
+	P4.L = (ICPLB_DATA0 & 0xFFFF);
+	R7 = CPLB_VALID | CPLB_L1_CHBL;
+	R6 = 16;
+inext:	R0 = [P5++];
+	R1 = [P4++];
+	[--SP] =  RETS;
+	CALL icplb_flush;	/* R0 = page, R1 = data*/
+	RETS = [SP++];
+iskip:	R6 += -1;
+	CC = R6;
+	IF CC JUMP inext;
+	SSYNC;
+	SP += 12;
+	UNLINK;
+	( R7:6, P5:4 ) = [SP++];
+	RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular ICPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(icplb_flush)
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = LC0;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC1;
+	[--SP] = LT1;
+	[--SP] = LB1;
+	
+	/* If it's a 1K or 4K page, then it's quickest to
+	 * just systematically flush all the addresses in
+	 * the page, regardless of whether they're in the
+	 * cache, or dirty. If it's a 1M or 4M page, there
+	 * are too many addresses, and we have to search the
+	 * cache for lines corresponding to the page.
+	 */
+
+	CC = BITTST(R1, 17);	/* 1MB or 4MB */
+	IF !CC JUMP iflush_whole_page;
+
+	/* We're only interested in the page's size, so extract
+	 * this from the CPLB (bits 17:16), and scale to give an
+	 * offset into the page_size and page_prefix tables.
+	 */
+
+	R1 <<= 14;
+	R1 >>= 30;
+	R1 <<= 2;
+
+	/* We can also determine the sub-bank used, because this is
+	 * taken from bits 13:12 of the address.
+	 */
+
+	R3 = ((12<<8)|2);		/* Extraction pattern */
+	nop;				/*Anamoly 05000209*/
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
+	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
+
+	
+	/* So:
+	 * R0 = Page start
+	 * R1 = Page length (actually, offset into size/prefix tables)
+	 * R3 = sub-bank deposit values
+  	 *
+	 * The cache has 2 Ways, and 64 sets, so we iterate through
+	 * the sets, accessing the tag for each Way, for our Bank and
+	 * sub-bank, looking for dirty, valid tags that match our
+	 * address prefix.
+	 */
+	
+	P5.L = (ITEST_COMMAND & 0xFFFF);
+	P5.H = (ITEST_COMMAND >> 16);
+	P4.L = (ITEST_DATA0 & 0xFFFF);
+	P4.H = (ITEST_DATA0 >> 16);
+
+	P0.L = page_prefix_table;
+	P0.H = page_prefix_table;
+	P1 = R1;
+	R5 = 0;			/* Set counter*/
+	P0 = P1 + P0;
+	R4 = [P0];		/* This is the address prefix*/
+
+	/* We're reading (bit 1==0) the tag (bit 2==0), and we
+	 * don't care about which double-word, since we're only
+	 * fetching tags, so we only have to set Set, Bank,
+	 * Sub-bank and Way.
+	 */
+	
+	P2 = 4;
+	LSETUP (ifs1, ife1) LC1 = P2;
+ifs1:	P0 = 32;		/* iterate over all sets*/
+	LSETUP (ifs0, ife0) LC0 = P0;
+ifs0:	R6 = R5 << 5;		/* Combine set*/
+	R6.H = R3.H << 0 ;	/* and sub-bank*/
+	[P5] = R6;		/* Issue Command*/
+	SSYNC;			/* CSYNC will not work here :(*/
+	R7 = [P4];		/* and read Tag.*/
+	CC = BITTST(R7, 0);	/* Check if valid*/
+	IF !CC JUMP ifskip;	/* and skip if not.*/
+
+	/* Compare against the page address. First, plant bits 13:12
+	 * into the tag, since those aren't part of the returned data.
+	 */
+
+	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
+	R1 = R7 & R4;		/* Mask off lower bits*/
+	CC = R1 == R0;		/* Compare against page start.*/
+	IF !CC JUMP ifskip;	/* Skip it if it doesn't match.*/
+
+	/* Tag address matches against page, so this is an entry
+	 * we must flush. 
+	 */
+
+	R7 >>= 10;		/* Mask off the non-address bits*/
+	R7 <<= 10;
+	P3 = R7;
+	IFLUSH [P3];		/* And flush the entry*/
+ifskip:
+ife0:	R5 += 1;		/* Advance to next Set*/
+ife1:	NOP;
+
+ifinished:
+	SSYNC;			/* Ensure the data gets out to mem.*/
+
+	/*Finished. Restore context.*/
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC1 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	LC0 = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+iflush_whole_page:
+	/* It's a 1K or 4K page, so quicker to just flush the
+	 * entire page.
+	 */
+
+	P1 = 32;		/* For 1K pages*/
+	P2 = P1 << 2;		/* For 4K pages*/
+	P0 = R0;		/* Start of page*/
+	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
+	IF CC P1 = P2;
+	P1 += -1;		/* Unroll one iteration*/
+	SSYNC;
+	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
+	LSETUP (isall, ieall) LC0 = P1;
+isall:IFLUSH [P0++];
+ieall: NOP;	
+	SSYNC;
+	JUMP ifinished;
+
+/* This is an external function being called by the user 
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(flush_data_cache)
+	[--SP] = ( R7:6, P5:4 );
+	LINK 12;
+	SP += -12;
+	P5.H = (DCPLB_ADDR0 >> 16);
+	P5.L = (DCPLB_ADDR0 & 0xFFFF);
+	P4.H = (DCPLB_DATA0 >> 16);
+	P4.L = (DCPLB_DATA0 & 0xFFFF);
+	R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+	R6 = 16;
+next:	R0 = [P5++];
+	R1 = [P4++];
+	CC = BITTST(R1, 14);	/* Is it write-through?*/
+	IF CC JUMP skip;	/* If so, ignore it.*/
+	R2 = R1 & R7;		/* Is it a dirty, cached page?*/
+	CC = R2;
+	IF !CC JUMP skip;	/* If not, ignore it.*/
+	[--SP] = RETS;
+	CALL dcplb_flush;	/* R0 = page, R1 = data*/
+	RETS = [SP++];
+skip:	R6 += -1;
+	CC = R6;
+	IF CC JUMP next;
+	SSYNC;
+	SP += 12;
+	UNLINK;
+	( R7:6, P5:4 ) = [SP++];
+	RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ * 
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(dcplb_flush)
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = LC0;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC1;
+	[--SP] = LT1;
+	[--SP] = LB1;
+	
+	/* If it's a 1K or 4K page, then it's quickest to
+	 * just systematically flush all the addresses in
+	 * the page, regardless of whether they're in the
+	 * cache, or dirty. If it's a 1M or 4M page, there
+	 * are too many addresses, and we have to search the
+	 * cache for lines corresponding to the page.
+	 */
+
+	CC = BITTST(R1, 17);	/* 1MB or 4MB */
+	IF !CC JUMP dflush_whole_page;
+
+	/* We're only interested in the page's size, so extract
+	 * this from the CPLB (bits 17:16), and scale to give an
+	 * offset into the page_size and page_prefix tables.	
+	 */
+		
+	R1 <<= 14;
+	R1 >>= 30;
+	R1 <<= 2;
+
+	/* The page could be mapped into Bank A or Bank B, depending
+	 * on (a) whether both banks are configured as cache, and
+	 * (b) on whether address bit A[x] is set. x is determined
+	 * by DCBS in DMEM_CONTROL		
+	 */
+	
+	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
+
+	P0.L = (DMEM_CONTROL & 0xFFFF);
+	P0.H = (DMEM_CONTROL >> 16);
+
+	R3 = [P0];		/* If Bank B is not enabled as cache*/
+	CC = BITTST(R3, 2);	/* then Bank A is our only option.*/
+	IF CC JUMP bank_chosen;
+
+	R4 = 1<<14;		/* If DCBS==0, use A[14].*/
+	R5 = R4 << 7;		/* If DCBS==1, use A[23];*/
+	CC = BITTST(R3, 4);
+	IF CC R4 = R5;		/* R4 now has either bit 14 or bit 23 set.*/
+	R5 = R0 & R4;		/* Use it to test the Page address*/
+	CC = R5;		/* and if that bit is set, we use Bank B,*/
+	R2 = CC;		/* else we use Bank A.*/
+	R2 <<= 23;		/* The Bank selection's at posn 23.*/
+
+bank_chosen:
+
+	/* We can also determine the sub-bank used, because this is
+	 * taken from bits 13:12 of the address.
+	 */
+
+	R3 = ((12<<8)|2);		/* Extraction pattern */
+	nop;				/*Anamoly 05000209*/
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
+	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
+
+	/* So:
+	 * R0 = Page start
+	 * R1 = Page length (actually, offset into size/prefix tables)
+	 * R2 = Bank select mask
+	 * R3 = sub-bank deposit values
+  	 *
+	 * The cache has 2 Ways, and 64 sets, so we iterate through
+	 * the sets, accessing the tag for each Way, for our Bank and
+	 * sub-bank, looking for dirty, valid tags that match our
+	 * address prefix.
+	 */
+	
+	P5.L = (DTEST_COMMAND & 0xFFFF);
+	P5.H = (DTEST_COMMAND >> 16);
+	P4.L = (DTEST_DATA0 & 0xFFFF);
+	P4.H = (DTEST_DATA0 >> 16);
+
+	P0.L = page_prefix_table;
+	P0.H = page_prefix_table;
+	P1 = R1;
+	R5 = 0;			/* Set counter*/
+	P0 = P1 + P0;
+	R4 = [P0];		/* This is the address prefix*/
+
+
+	/* We're reading (bit 1==0) the tag (bit 2==0), and we
+	 * don't care about which double-word, since we're only
+	 * fetching tags, so we only have to set Set, Bank,
+	 * Sub-bank and Way.
+	 */
+	
+	P2 = 2;
+	LSETUP (fs1, fe1) LC1 = P2;
+fs1:	P0 = 64;		/* iterate over all sets*/
+	LSETUP (fs0, fe0) LC0 = P0;
+fs0:	R6 = R5 << 5;		/* Combine set*/
+	R6.H = R3.H << 0 ;	/* and sub-bank*/
+	R6 = R6 | R2;		/* and Bank. Leave Way==0 at first.*/
+	BITSET(R6,14);
+	[P5] = R6;		/* Issue Command*/
+	SSYNC;
+	R7 = [P4];		/* and read Tag.*/
+	CC = BITTST(R7, 0);	/* Check if valid*/
+	IF !CC JUMP fskip;	/* and skip if not.*/
+	CC = BITTST(R7, 1);	/* Check if dirty*/
+	IF !CC JUMP fskip;	/* and skip if not.*/
+
+	/* Compare against the page address. First, plant bits 13:12
+	 * into the tag, since those aren't part of the returned data.
+	 */
+
+	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
+	R1 = R7 & R4;		/* Mask off lower bits*/
+	CC = R1 == R0;		/* Compare against page start.*/
+	IF !CC JUMP fskip;	/* Skip it if it doesn't match.*/
+
+	/* Tag address matches against page, so this is an entry
+	 * we must flush.
+	 */
+
+	R7 >>= 10;		/* Mask off the non-address bits*/
+	R7 <<= 10;
+	P3 = R7;
+	SSYNC;
+	FLUSHINV [P3];		/* And flush the entry*/
+fskip:
+fe0:	R5 += 1;		/* Advance to next Set*/
+fe1:	BITSET(R2, 26);		/* Go to next Way.*/
+
+dfinished:
+	SSYNC;			/* Ensure the data gets out to mem.*/
+
+	/*Finished. Restore context.*/
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC1 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	LC0 = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+dflush_whole_page:
+
+	/* It's a 1K or 4K page, so quicker to just flush the
+	 * entire page.
+	 */
+
+	P1 = 32;		/* For 1K pages*/
+	P2 = P1 << 2;		/* For 4K pages*/
+	P0 = R0;		/* Start of page*/
+	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
+	IF CC P1 = P2;
+	P1 += -1;		/* Unroll one iteration*/
+    SSYNC;
+	FLUSHINV [P0++];	/* because CSYNC can't end loops.*/
+	LSETUP (eall, eall) LC0 = P1;
+eall:	FLUSHINV [P0++];
+	SSYNC;
+	JUMP dfinished;
+
+.align 4;
+page_prefix_table:
+.byte4 	0xFFFFFC00;	/* 1K */
+.byte4	0xFFFFF000;	/* 4K */
+.byte4	0xFFF00000;	/* 1M */
+.byte4	0xFFC00000;	/* 4M */
+.page_prefix_table.end:
diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
new file mode 100644
index 0000000..b4d2579
--- /dev/null
+++ b/cpu/bf533/interrupt.S
@@ -0,0 +1,391 @@
+/*
+ * U-boot - interrupt.S Processing of interrupts and exception handling
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on interrupt.S
+ *
+ * Copyright (C) 2003  Metrowerks, Inc. <mwaddel@metrowerks.com>
+ * Copyright (C) 2002  Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * This file is also based on exception.asm
+ * (C) Copyright 2001-2005 - Analog Devices, Inc.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+
+#include <asm/hw_irq.h>
+#include <asm/entry.h>
+#include <asm/blackfin_defs.h>
+#include <asm/cpu/bf533_irq.h>
+
+.global blackfin_irq_panic;
+
+.text
+.align 2
+
+#ifndef CONFIG_KGDB
+.global evt_emulation
+evt_emulation:
+	SAVE_CONTEXT
+	r0 = IRQ_EMU;
+	r1 = seqstat;
+	sp += -12;
+	call blackfin_irq_panic;
+	sp += 12;
+	rte;
+#endif
+
+.global evt_nmi
+evt_nmi:
+	SAVE_CONTEXT
+	r0 = IRQ_NMI;
+	r1 = RETN;
+	sp += -12;
+	call blackfin_irq_panic;
+	sp += 12;
+
+_evt_nmi_exit:
+	rtn;
+
+.global trap
+trap:
+	[--sp] = r0;
+	[--sp] = r1;
+	[--sp] = p0;
+	[--sp] = p1;
+	[--sp] = astat;
+	r0 = seqstat;
+	R0 <<= 26;
+	R0 >>= 26;
+	p0 = r0;
+	p1.l = EVTABLE;
+	p1.h = EVTABLE;
+	p0 = p1 + (p0 << 1);
+	r1 = W[p0] (Z);
+	p1 = r1;
+	jump (pc + p1);
+
+.global _EVENT1
+_EVENT1:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT2
+_EVENT2:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT3
+_EVENT3:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT4
+_EVENT4:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT5
+_EVENT5:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT6
+_EVENT6:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT7
+_EVENT7:
+	RAISE 15;
+	JUMP.S _EXIT;
+
+.global _EVENT8
+_EVENT8:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT9
+_EVENT9:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT10
+_EVENT10:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT11
+_EVENT11:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT12
+_EVENT12:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT13
+_EVENT13:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT14
+_EVENT14:
+/*	RAISE 14;	*/
+	CALL	_cplb_hdr;
+	JUMP.S _EXIT;
+
+.global _EVENT19
+_EVENT19:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT20
+_EVENT20:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EVENT21
+_EVENT21:
+	RAISE 14;
+	JUMP.S _EXIT;
+
+.global _EXIT
+_EXIT:
+	ASTAT = [sp++];
+	p1 = [sp++];
+	p0 = [sp++];
+	r1 = [sp++];
+	r0 = [sp++];
+	RTX;
+
+EVTABLE:
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x0000;
+	.byte2 0x003E;
+	.byte2 0x0042;
+	.byte4 0x0000;
+	.byte4 0x0000;
+	.byte4 0x0000;
+	.byte4 0x0000;
+	.byte4 0x0000;
+	.byte4 0x0000;
+	.byte4 0x0000;
+	.byte2 0x0000;
+	.byte2 0x001E;
+	.byte2 0x0022;
+	.byte2 0x0032;
+	.byte2 0x002e;
+	.byte2 0x0002;
+	.byte2 0x0036;
+	.byte2 0x002A;
+	.byte2 0x001A;
+	.byte2 0x0016;
+	.byte2 0x000A;
+	.byte2 0x000E;
+	.byte2 0x0012;
+	.byte2 0x0006;
+	.byte2 0x0026;
+
+.global evt_rst
+evt_rst:
+	SAVE_CONTEXT
+	r0 = IRQ_RST;
+	r1 = RETN;
+	sp += -12;
+	call do_reset;
+	sp += 12;
+
+_evt_rst_exit:
+	rtn; 
+
+irq_panic:
+	r0 = IRQ_EVX;
+	r1 =  sp;
+	sp += -12;
+	call blackfin_irq_panic;
+	sp += 12;
+
+.global evt_ivhw
+evt_ivhw:
+	SAVE_CONTEXT
+	RAISE 14;
+
+_evt_ivhw_exit:
+	 rti;
+
+.global evt_timer
+evt_timer:
+	SAVE_CONTEXT
+	r0 = IRQ_CORETMR;
+	sp += -12;
+	/* Polling method used now. */
+	/* call timer_int; */
+	sp += 12;
+	RESTORE_CONTEXT
+	rti;
+	nop;
+
+.global evt_evt7
+evt_evt7:
+	SAVE_CONTEXT
+	r0 = 7;
+	sp += -12;
+	call process_int;
+	sp += 12;
+
+evt_evt7_exit:
+	RESTORE_CONTEXT
+	rti; 
+
+.global evt_evt8
+evt_evt8:
+	SAVE_CONTEXT
+	r0 = 8;
+	sp += -12;
+	call process_int;
+	sp += 12;
+
+evt_evt8_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global evt_evt9
+evt_evt9:
+	SAVE_CONTEXT
+	r0 = 9;
+	sp += -12;
+	call process_int;
+	sp += 12;
+
+evt_evt9_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global evt_evt10
+evt_evt10:
+	SAVE_CONTEXT
+	r0 = 10;
+	sp += -12;
+	call process_int;
+	sp += 12;
+
+evt_evt10_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global evt_evt11
+evt_evt11:
+	SAVE_CONTEXT
+	r0 = 11;
+	sp += -12;
+	call process_int;
+	sp += 12;
+
+evt_evt11_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global evt_evt12
+evt_evt12:
+	SAVE_CONTEXT
+	r0 = 12;
+	sp += -12;
+	call process_int;
+	sp += 12;
+evt_evt12_exit:
+	 RESTORE_CONTEXT
+	 rti;
+
+.global evt_evt13
+evt_evt13:
+	SAVE_CONTEXT
+	r0 = 13;
+	sp += -12;
+	call process_int;
+	sp += 12;
+
+evt_evt13_exit:
+	 RESTORE_CONTEXT
+	 rti;
+
+.global evt_system_call
+evt_system_call:
+	[--sp] = r0;
+	[--SP] = RETI;
+	r0 = [sp++];
+	r0 += 2;
+	[--sp] = r0;
+	RETI = [SP++];
+	r0 = [SP++];
+	SAVE_CONTEXT
+	sp += -12;
+	call display_excp;
+	sp += 12;
+	RESTORE_CONTEXT
+	RTI;
+
+evt_system_call_exit:
+	rti;
+
+.global evt_soft_int1
+evt_soft_int1:
+	[--sp] = r0;
+	[--SP] = RETI;
+	r0 = [sp++];
+	r0 += 2;
+	[--sp] = r0;
+	RETI = [SP++];
+	r0 = [SP++];
+	SAVE_CONTEXT
+	sp += -12;
+	call display_excp;
+	sp += 12;
+	RESTORE_CONTEXT
+	RTI;
+
+evt_soft_int1_exit:
+	rti;
diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c
new file mode 100644
index 0000000..df1a25e
--- /dev/null
+++ b/cpu/bf533/interrupts.c
@@ -0,0 +1,165 @@
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/cpu/defBF533.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags; /* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On BF533 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On BF533 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+void enable_interrupts(void)
+{
+	restore_flags(int_flag);
+}
+
+int disable_interrupts(void)
+{
+	save_and_cli(int_flag);
+	return 1;
+}
+
+int interrupt_init(void)
+{
+	return (0);
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned long delay, start, stop;
+	unsigned long cclk;
+	cclk = (CONFIG_CCLK_HZ);
+
+	while ( usec > 1 ) {
+	       /*
+		* how many clock ticks to delay?
+		*  - request(in useconds) * clock_ticks(Hz) / useconds/second
+		*/
+		if (usec < 1000) {
+			delay = (usec * (cclk/244)) >> 12 ;
+			usec = 0;
+		} else {
+			delay = (1000 * (cclk/244)) >> 12 ;
+			usec -= 1000;
+		}
+
+		asm volatile (" %0 = CYCLES;": "=g"(start));
+		do {
+			asm volatile (" %0 = CYCLES; ": "=g"(stop));
+		} while (stop - start < delay);
+	}
+
+	return;
+}
+
+void timer_init(void)
+{
+	*pTCNTL = 0x1;
+	*pTSCALE = 0x0;
+	*pTCOUNT  = MAX_TIM_LOAD;
+	*pTPERIOD = MAX_TIM_LOAD;
+	*pTCNTL = 0x7;
+	asm("CSYNC;");
+
+	timestamp = 0;
+	last_time = 0;
+}
+
+/* Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ *  As get_timer is used in the u-boot
+ *  only for timeouts this should be
+ *  sufficient
+ */
+ulong get_timer(ulong base)
+{
+	ulong milisec;
+
+	/* Number of clocks elapsed */
+	ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
+
+	/* Find if the TCOUNT is reset
+	timestamp gives the number of times
+	TCOUNT got reset */
+	if(clocks < last_time)
+		timestamp++;
+	last_time = clocks;
+
+	/* Get the number of milliseconds */
+	milisec = clocks/(CONFIG_CCLK_HZ / 1000);
+
+	/* Find the number of millisonds
+	that got elapsed before this TCOUNT
+	cycle */
+	milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000));
+
+	return (milisec - base);
+}
diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c
new file mode 100644
index 0000000..859f4b2
--- /dev/null
+++ b/cpu/bf533/ints.c
@@ -0,0 +1,107 @@
+/*
+ * U-boot - ints.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on ints.c
+ *
+ * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
+ *             drivers
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+void blackfin_irq_panic(int reason, struct pt_regs *regs)
+{
+	printf("\n\nException: IRQ 0x%x entered\n", reason);
+	printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f));
+	printf("stack frame=0x%x, ", (unsigned int) regs);
+	printf("bad PC=0x%04x\n", (unsigned int) regs->pc);
+	dump(regs);
+	printf("Unhandled IRQ or exceptions!\n");
+	printf("Please reset the board \n");
+}
+
+void blackfin_init_IRQ(void)
+{
+	*(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
+	cli();
+#ifndef CONFIG_KGDB
+	*(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
+#endif
+	*(unsigned volatile long *) (EVT_NMI_ADDR) =
+		(unsigned volatile long) evt_nmi;
+	*(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
+		(unsigned volatile long) trap;
+	*(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
+		(unsigned volatile long) evt_ivhw;
+	*(unsigned volatile long *) (EVT_RESET_ADDR) =
+		(unsigned volatile long) evt_rst;
+	*(unsigned volatile long *) (EVT_TIMER_ADDR) =
+		(unsigned volatile long) evt_timer;
+	*(unsigned volatile long *) (EVT_IVG7_ADDR) =
+		(unsigned volatile long) evt_evt7;
+	*(unsigned volatile long *) (EVT_IVG8_ADDR) =
+		(unsigned volatile long) evt_evt8;
+	*(unsigned volatile long *) (EVT_IVG9_ADDR) =
+		(unsigned volatile long) evt_evt9;
+	*(unsigned volatile long *) (EVT_IVG10_ADDR) =
+		(unsigned volatile long) evt_evt10;
+	*(unsigned volatile long *) (EVT_IVG11_ADDR) =
+		(unsigned volatile long) evt_evt11;
+	*(unsigned volatile long *) (EVT_IVG12_ADDR) =
+		(unsigned volatile long) evt_evt12;
+	*(unsigned volatile long *) (EVT_IVG13_ADDR) =
+		(unsigned volatile long) evt_evt13;
+	*(unsigned volatile long *) (EVT_IVG14_ADDR) =
+		(unsigned volatile long) evt_system_call;
+	*(unsigned volatile long *) (EVT_IVG15_ADDR) =
+		(unsigned volatile long) evt_soft_int1;
+	*(volatile unsigned long *) ILAT = 0;
+	asm("csync;");
+	sti();
+	*(volatile unsigned long *) IMASK = 0xffbf;
+	asm("csync;");
+}
+
+void display_excp(void)
+{
+	printf("Exception!\n");
+}
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
new file mode 100644
index 0000000..8f0cd16
--- /dev/null
+++ b/cpu/bf533/serial.c
@@ -0,0 +1,194 @@
+/*
+ * U-boot - serial.c Serial driver for BF533
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
+ * Copyright (c) 2003	Bas Vermeulen <bas@buyways.nl>,
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on blkfinserial.c
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003	Metrowerks	<mwaddel@metrowerks.com>
+ * Copyright(c)	2001	Tony Z. Kou	<tonyko@arcturusnetworks.com>
+ * Copyright(c)	2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ * 
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com> 
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/bitops.h>
+#include <asm/delay.h>
+#include <asm/uaccess.h>
+#include "bf533_serial.h"
+
+unsigned long pll_div_fact;
+
+void calc_baud(void)
+{
+	unsigned char i;
+	int	temp;
+
+	for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) {
+		temp =  CONFIG_SCLK_HZ/(baud_table[i]*8);
+		if ( temp && 0x1 == 1 ) {
+			temp++;
+		}
+		temp = temp/2;
+		hw_baud_table[i].dl_high = (temp >> 8)& 0xFF;
+		hw_baud_table[i].dl_low = (temp) & 0xFF;
+	}
+}
+
+void serial_setbrg(void)
+{
+	int i;
+	DECLARE_GLOBAL_DATA_PTR;
+
+	calc_baud();
+
+	for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+		if (gd->baudrate == baud_table[i])
+			break;
+	}
+
+	/* Enable UART */
+	*pUART_GCTL |= UART_GCTL_UCEN;
+	asm("ssync;");
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH;
+	asm("ssync;");
+
+	*pUART_DLL = hw_baud_table[i].dl_low;
+	asm("ssync;");
+	*pUART_DLH = hw_baud_table[i].dl_high;
+	asm("ssync;");
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER;
+	asm("ssync;");
+
+	/* Enable  ERBFI and ELSI interrupts
+	* to poll SIC_ISR register*/
+	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
+	asm("ssync;");
+
+	/* Set LCR to Word Lengh 8-bit word select */
+	*pUART_LCR = UART_LCR_WLS8;
+	asm("ssync;");
+
+	return;
+}
+
+int serial_init(void)
+{
+	serial_setbrg();
+	return (0);
+}
+
+void serial_putc(const char c)
+{
+	if ((*pUART_LSR) & UART_LSR_TEMT)
+	{
+		if (c == '\n')
+			serial_putc('\r');
+
+		local_put_char(c);
+	}
+
+	while (!((*pUART_LSR) & UART_LSR_TEMT))
+		SYNC_ALL;
+
+	return;
+}
+
+int serial_tstc(void)
+{
+	if (*pUART_LSR & UART_LSR_DR)
+		return 1;
+	else
+		return 0;
+}
+
+int serial_getc(void)
+{
+	unsigned short uart_lsr_val, uart_rbr_val;
+	unsigned long isr_val;
+	int ret;
+
+	/* Poll for RX Interrupt */
+	while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT));
+	asm("csync;");
+
+	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
+	uart_rbr_val = *pUART_RBR;	/* getc() */
+
+	if (isr_val & IRQ_UART_ERROR_BIT) {
+		ret =  -1;
+	}
+	else
+	{
+		ret = uart_rbr_val & 0xff;
+	}
+
+	return ret;
+}
+
+void serial_puts(const char *s)
+{
+	while (*s) {
+		serial_putc(*s++);
+	}
+}
+
+static void local_put_char(char ch)
+{
+	int flags = 0;
+	unsigned long isr_val;
+
+	save_and_cli(flags);
+
+        /* Poll for TX Interruput */
+        while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
+        asm("csync;");
+
+	*pUART_THR = ch;			/* putc() */
+
+	if (isr_val & IRQ_UART_ERROR_BIT) {
+		printf("?");
+	}
+
+	restore_flags(flags);
+
+	return ;
+}
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
new file mode 100644
index 0000000..7414d88
--- /dev/null
+++ b/cpu/bf533/start.S
@@ -0,0 +1,435 @@
+/*
+ * U-boot - start.S Startup file of u-boot for BF533
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003  Metrowerks/Motorola
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: A change in this file subsequently requires a change in
+ *       board/$(board_name)/config.mk for a valid u-boot.bin 
+ */
+
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+#include <config.h>
+#include <asm/mem_init.h>
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global _bf533_data_dest;
+.global _bf533_data_size;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+
+.text
+_start:
+start:
+_stext:
+
+	R0 = 0x30;
+	SYSCFG = R0;
+	SSYNC;
+
+	/* As per HW reference manual DAG registers,
+	 * DATA and Address resgister shall be zero'd 
+	 * in initialization, after a reset state
+	 */
+	r1 = 0;	/* Data registers zero'd */
+	r2 = 0;
+	r3 = 0;
+	r4 = 0;
+	r5 = 0;
+	r6 = 0;
+	r7 = 0;
+
+	p0 = 0; /* Address registers zero'd */
+	p1 = 0;
+	p2 = 0;
+	p3 = 0;
+	p4 = 0;
+	p5 = 0;
+	
+	i0 = 0; /* DAG Registers zero'd */
+	i1 = 0;
+	i2 = 0;
+	i3 = 0;
+	m0 = 0;
+	m1 = 0;
+	m3 = 0;
+	m3 = 0;
+	l0 = 0;
+	l1 = 0;
+	l2 = 0;
+	l3 = 0;
+	b0 = 0;
+	b1 = 0;
+	b2 = 0;
+	b3 = 0;
+
+	/* Set loop counters to zero, to make sure that
+	 * hw loops are disabled.
+	 */
+	lc0 = 0;
+	lc1 = 0;
+
+	SSYNC;
+
+	/* Check soft reset status */
+	p0.h = SWRST >> 16;
+	p0.l = SWRST & 0xFFFF;
+	r0.l = w[p0];
+
+	cc = bittst(r0, 15);
+	if !cc jump no_soft_reset;
+
+	/* Clear Soft reset */
+	r0 = 0x0000;
+	w[p0] = r0;
+	ssync;
+
+no_soft_reset:
+	nop;
+
+	/* Clear EVT registers */
+	p0.h = (EVT_EMULATION_ADDR >> 16);
+	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0 += 8;
+	p1 = 14;
+	r1 = 0;
+	LSETUP(4,4) lc0 = p1;
+	[ p0 ++ ] = r1;
+
+	/*
+	 *  Set PLL_CTL
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT;	/* Load the VCO multiplier */
+	r0 = r0 << 9;		/* Shift it over */
+	r1 =  CONFIG_CLKIN_HALF;	/* Do we need to divide CLKIN by 2? */
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;	/* Bypass the PLL?                 */
+	r1 = r1 << 8;	/* Shift it over */
+	r0 = r1 | r0;	/* add them all together */
+
+	p0.h = (PLL_CTL >> 16);
+	p0.l = (PLL_CTL & 0xFFFF);	/* Load the address */
+	cli r2;				/* Disable interrupts */
+	w[p0] = r0;			/* Set the value */
+	idle;				/* Wait for the PLL to stablize */
+	sti r2;				/* Enable interrupts */
+	ssync;
+
+	/*
+	 * Turn on the CYCLES COUNTER
+	 */
+	r2 = SYSCFG;
+	BITSET (r2,1);
+	SYSCFG = r2;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
+	p0.h = (PLL_DIV >> 16);
+	p0.l = (PLL_DIV & 0xFFFF);
+	w[p0] = r0;
+	ssync;
+
+wait_for_pll_stab:
+	p0.h = (PLL_STAT >> 16);
+	p0.l = (PLL_STAT & 0xFFFF);
+	r0.l = w[p0];
+	cc = bittst(r0,5);
+	if !cc jump wait_for_pll_stab;
+
+	/* Configure SDRAM if SDRAM is already not enabled */
+	p0.l = (EBIU_SDSTAT & 0xFFFF);
+	p0.h = (EBIU_SDSTAT >> 16);
+	r0.l = w[p0];
+	cc = bittst(r0, 3);
+	if !cc jump skip_sdram_enable;
+
+	/* SDRAM initialization */
+	p0.l = (EBIU_SDGCTL & 0xFFFF);
+	p0.h = (EBIU_SDGCTL >> 16);	/* SDRAM Memory Global Control Register */
+	r0.h = (mem_SDGCTL >> 16);
+	r0.l = (mem_SDGCTL & 0xFFFF);
+	[p0] = r0;
+	ssync;
+
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);	/* SDRAM Memory Bank Control Register */
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	p0.l = (EBIU_SDRRC & 0xFFFF);
+	p0.h = (EBIU_SDRRC >> 16);	/* SDRAM Refresh Rate Control Register */
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+skip_sdram_enable:
+	nop;
+
+#ifndef	CFG_NO_FLASH
+	/* relocate into to RAM */
+	p1.l = (CFG_FLASH_BASE & 0xffff);
+	p1.h = (CFG_FLASH_BASE >> 16);
+	p2.l = (CFG_MONITOR_BASE & 0xffff);
+	p2.h = (CFG_MONITOR_BASE >> 16);
+	r0.l = (CFG_MONITOR_LEN & 0xffff);
+	r0.h = (CFG_MONITOR_LEN >> 16);
+loop1:
+	r1 = [p1];
+	[p2] = r1;
+	p3=0x4;
+	p1=p1+p3;	
+	p2=p2+p3;
+	r2=0x4;	
+	r0=r0-r2;
+	cc=r0==0x0;
+	if !cc jump loop1;
+#endif
+	/*
+	 * configure STACK
+	 */
+	r0.h = (CONFIG_STACKBASE >> 16);
+	r0.l = (CONFIG_STACKBASE & 0xFFFF);
+	sp = r0;
+	fp = sp;
+
+	/*
+	 * This next section keeps the processor in supervisor mode
+	 * during kernel boot.  Switches to user mode at end of boot.
+	 * See page 3-9 of Hardware Reference manual for documentation.
+	 */
+
+	/* To keep ourselves in the supervisor mode */
+	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
+	p0.h = (EVT_IVG15_ADDR >> 16);
+
+	p1.l = _real_start;
+	p1.h = _real_start;
+	[p0] = p1;
+
+	p0.l = (IMASK & 0xFFFF);
+	p0.h = (IMASK >> 16);
+	r0 = IVG15_POS;
+	[p0] = r0;
+	raise 15;
+	p0.l = WAIT_HERE;
+	p0.h = WAIT_HERE;
+	reti = p0;
+	rti;
+
+WAIT_HERE:
+	jump WAIT_HERE;
+
+.global _real_start;
+_real_start:
+	[ -- sp ] = reti;
+
+#ifdef CONFIG_EZKIT533
+	p0.l = (WDOG_CTL & 0xFFFF);
+	p0.h = (WDOG_CTL >> 16);
+	r0 = WATCHDOG_DISABLE(z);
+	w[p0] = r0;
+#endif
+
+	/* Code for initializing Async mem banks */
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+	/* DMA reset code to Hi of L1 SRAM */
+copy:
+	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
+	P1.L = lo(SYSMMR_BASE);
+
+	R0.H = reset_start;	/* Source Address (high) */
+	R0.L = reset_start;	/* Source Address (low) */
+	R1.H = reset_end;
+	R1.L = reset_end;
+	R2 = R1 - R0;		/* Count */
+	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
+
+DMA:
+	R6 = 0x1 (Z);
+	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
+	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
+
+	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
+	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
+	/* Set Source  DMAConfig = DMA Enable,
+	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
+	/* Set Destination DMAConfig = DMA Enable,
+	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+	IDLE;	/* Wait for DMA to Complete */
+
+	R0 = 0x1;
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
+
+	/* DMA reset code to DATA BANK A which uses this port
+	 * to avoid following problem
+	 * " Data from a Data Cache fill can be corrupoted after or during
+	 *   instruction DMA if certain core stalls exist"
+	 */
+
+copy_as_data:
+	R0.H = reset_start;	/* Source Address (high) */
+	R0.L = reset_start;	/* Source Address (low) */
+	R1.H = reset_end;
+	R1.L = reset_end;
+	R2 = R1 - R0;	/* Count */
+	R1.H = hi(DATA_BANKA_SRAM);	/* Destination Address (high) */
+	R1.L = lo(DATA_BANKA_SRAM);	/* Destination Address (low) */
+	R3.L = DMAEN;	/* Source DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
+
+DMA_DATA:
+	R6 = 0x1 (Z);
+	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
+	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
+
+ 	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
+	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
+	/* Set Source      DMAConfig = DMA Enable,
+	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
+	/* Set Destination DMAConfig = DMA Enable,
+	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+	IDLE;	/* Wait for DMA to Complete */
+
+	R0 = 0x1;
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
+
+copy_end: nop;
+
+	/* Initialize BSS Section with 0 s */
+	p1.l = __bss_start;
+	p1.h = __bss_start;
+	p2.l = _end;
+	p2.h = _end;
+	r1 = p1;
+	r2 = p2;
+	r3 = r2 - r1;
+	r3 = r3 >> 2;
+	p3 = r3;
+	lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
+	CC = p2<=p1;
+	if CC jump _clear_bss_skip;
+	r0 = 0;
+_clear_bss:
+_clear_bss_end:
+ 	[p1++] = r0;
+_clear_bss_skip:
+
+	p0.l = _start1;
+	p0.h = _start1;
+	jump (p0);
+
+reset_start:
+	p0.h = WDOG_CNT >> 16;
+	p0.l = WDOG_CNT & 0xffff;
+	r0 = 0x0010;
+	w[p0] = r0;
+	p0.h = WDOG_CTL >> 16;
+	p0.l = WDOG_CTL & 0xffff;
+	r0 = 0x0000;
+	w[p0] = r0;
+reset_wait:
+	jump reset_wait;
+
+reset_end: nop;
+
+_exit:
+	jump.s	_exit;
diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S
new file mode 100644
index 0000000..6f48124
--- /dev/null
+++ b/cpu/bf533/start1.S
@@ -0,0 +1,38 @@
+/*
+ * U-boot - start1.S Code running out of RAM after relocation
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <linux/config.h>
+#include <asm/blackfin.h>
+#include <config.h>
+
+.global	start1;
+.global	_start1;
+
+.text
+_start1:
+start1:
+	sp += -12;
+	call	board_init_f;
+	sp += 12;
diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
new file mode 100644
index 0000000..37470d5
--- /dev/null
+++ b/cpu/bf533/traps.c
@@ -0,0 +1,73 @@
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/machdep.h>
+#include "cpu.h"
+
+void init_IRQ(void)
+{
+	blackfin_init_IRQ();
+	return;
+}
+
+void process_int(unsigned long vec, struct pt_regs *fp)
+{
+	return;
+}
+
+void dump(struct pt_regs *fp)
+{
+	printf("PC: %08lx\n", fp->pc);
+	printf("SEQSTAT: %08lx    SP: %08lx\n", (long) fp->seqstat,
+		(long) fp);
+	printf("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+		fp->r0, fp->r1, fp->r2, fp->r3);
+	printf("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+		fp->r4, fp->r5, fp->r6, fp->r7);
+	printf("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+		fp->p0, fp->p1, fp->p2, fp->p3);
+	printf("P4: %08lx    P5: %08lx    FP: %08lx\n", fp->p4, fp->p5,
+		fp->fp);
+	printf("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+		fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+	printf("\n");
+}
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
new file mode 100644
index 0000000..65d2c25
--- /dev/null
+++ b/include/asm-blackfin/bitops.h
@@ -0,0 +1,380 @@
+/*
+ * U-boot - bitops.h Routines for bit operations
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_BITOPS_H
+#define _BLACKFIN_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+
+#ifdef __KERNEL__
+/*
+ * Function prototypes to keep gcc -Wall happy
+ */
+
+/*
+ * The __ functions are not atomic
+ */
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+	unsigned long result = 0;
+
+	while (word & 1) {
+		result++;
+		word >>= 1;
+	}
+	return result;
+}
+
+static __inline__ void set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *) addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_and_cli(flags);
+	*a |= mask;
+	restore_flags(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *) addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *) addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_and_cli(flags);
+	*a &= ~mask;
+	restore_flags(flags);
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+	int mask, flags;
+	unsigned long *ADDR = (unsigned long *) addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	save_and_cli(flags);
+	*ADDR ^= mask;
+	restore_flags(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *) addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static __inline__ int __constant_test_bit(int nr,
+					  const volatile void *addr)
+{
+	return ((1UL << (nr & 31)) &
+		(((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int __test_bit(int nr, volatile void *addr)
+{
+	int *a = (int *) addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	return ((mask & *a) != 0);
+}
+
+#define	test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define	find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32 - offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+      found_first:
+	tmp |= ~0UL >> size;
+      found_middle:
+	return result + ffz(tmp);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x)		generic_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x)	generic_hweight32(x)
+#define hweight16(x)	generic_hweight16(x)
+#define hweight8(x)	generic_hweight8(x)
+
+static __inline__ int ext2_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	unsigned long flags;
+	volatile unsigned char *ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_and_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	restore_flags(flags);
+	return retval;
+}
+
+static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	unsigned long flags;
+	volatile unsigned char *ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_and_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	restore_flags(flags);
+	return retval;
+}
+
+static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
+{
+	int mask;
+	const volatile unsigned char *ADDR = (const unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+							unsigned long size,
+							unsigned long
+							offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32 - offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+      found_first:
+	tmp |= ~0UL >> size;
+      found_middle:
+	return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)		test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)			set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)			test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+#endif
+
+#endif
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
new file mode 100644
index 0000000..fbdbf30
--- /dev/null
+++ b/include/asm-blackfin/blackfin.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - blackfin.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_H_
+#define _BLACKFIN_H_
+
+#include <asm/cpu/defBF533.h>
+#include <asm/cpu/bf533_serial.h>
+
+#ifndef __ASSEMBLY__
+#ifndef ASSEMBLY
+
+#ifdef SHARED_RESOURCES
+ #include <asm/shared_resources.h>
+#endif
+#include <asm/cpu/cdefBF53x.h>
+
+#endif
+#endif
+
+#include <asm/cpu/defBF533.h>
+#include <asm/cpu/defBF533_extn.h>
+#include <asm/cpu/bf533_serial.h>
+
+#endif
diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h
new file mode 100644
index 0000000..2190215
--- /dev/null
+++ b/include/asm-blackfin/blackfin_defs.h
@@ -0,0 +1,83 @@
+/*
+ * U-boot - blackfin_defs.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_DEFS_H__
+#define __BLACKFIN_DEFS_H__
+
+#define TS_MAGICKEY		0x5a5a5a5a
+#define TASK_STATE		0
+#define TASK_FLAGS		4
+#define TASK_PTRACE		24
+#define TASK_BLOCKED		636
+#define TASK_COUNTER		32
+#define TASK_SIGPENDING		8
+#define TASK_NEEDRESCHED	20
+#define TASK_THREAD		600
+#define TASK_MM			44
+#define TASK_ACTIVE_MM		80
+#define THREAD_KSP		0
+#define THREAD_USP		4
+#define THREAD_SR		8
+#define THREAD_ESP0		12
+#define THREAD_PC		16
+#define PT_ORIG_R0		208
+#define PT_R0			204
+#define PT_R1			200
+#define PT_R2			196
+#define PT_R3			192
+#define PT_R4			188
+#define PT_R5			184
+#define PT_R6			180
+#define PT_R7			176
+#define PT_P0			172
+#define PT_P1			168
+#define PT_P2			164
+#define PT_P3			160
+#define PT_P4			156
+#define PT_P5			152
+#define PT_A0w			72
+#define PT_A1w			64
+#define PT_A0x			76
+#define PT_A1x			68
+#define PT_RETS			28
+#define PT_RESERVED		32
+#define PT_ASTAT		36
+#define PT_SEQSTAT		8
+#define PT_PC			24
+#define PT_IPEND		0
+#define PT_USP			144
+#define PT_FP			148
+#define PT_SYSCFG		4
+#define IRQ_HANDLER		0
+#define IRQ_DEVID		8
+#define IRQ_NEXT		16
+#define STAT_IRQ		5148
+#define SIGSEGV			11
+#define SEGV_MAPERR		196609
+#define SIGTRAP			5
+#define PT_PTRACED		1
+#define PT_TRACESYS		2
+#define PT_DTRACE		4
+
+#endif
diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
new file mode 100644
index 0000000..3b4df4e
--- /dev/null
+++ b/include/asm-blackfin/byteorder.h
@@ -0,0 +1,40 @@
+/*
+ * U-boot -  byteorder.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_BYTEORDER_H
+#define _BLACKFIN_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
new file mode 100644
index 0000000..7715f64
--- /dev/null
+++ b/include/asm-blackfin/cplb.h
@@ -0,0 +1,48 @@
+/************************************************************************
+ *
+ * cplb.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+/* Defines necessary for cplb initialisation routines. */
+
+#ifndef _CPLB_H
+#define _CPLB_H
+
+#define CPLB_ENABLE_ICACHE_P	0
+#define CPLB_ENABLE_DCACHE_P	1
+#define CPLB_ENABLE_DCACHE2_P	2
+#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated!*/
+#define CPLB_ENABLE_ICPLBS_P	4
+#define CPLB_ENABLE_DCPLBS_P	5
+
+#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
+				CPLB_ENABLE_ICPLBS | \
+				CPLB_ENABLE_DCPLBS
+
+#define CPLB_RELOADED		0x0000
+#define CPLB_NO_UNLOCKED	0x0001
+#define CPLB_NO_ADDR_MATCH	0x0002
+#define CPLB_PROT_VIOL		0x0003
+
+#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
+#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
+
+#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
+
+#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
+#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
+#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL
+
+#endif /* _CPLB_H */
diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h
new file mode 100644
index 0000000..dc6aee2
--- /dev/null
+++ b/include/asm-blackfin/cplbtab.h
@@ -0,0 +1,572 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's 
+ *	        shouldn't be victimized. cplbmgr.S search logic is corrected
+ *	        to findout the appropriate victim.	
+ *	     2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ *	     : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*************************************************************************
+ *  			ICPLB TABLE					  	
+ *************************************************************************/
+
+.data
+
+/* This table is configurable */ 	
+
+.align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158		0x200	
+#ifdef CONFIG_BLKFIN_WB 	/*Write Back Policy */
+	#define SDRAM_DGENERIC  	(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else  /*Write Through*/
+	#define SDRAM_DGENERIC 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)	
+	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif 
+
+.global icplb_table
+icplb_table:
+.byte4 0xFFA00000;
+.byte4 (L1_IMEMORY);	
+.byte4 0x00000000;
+.byte4 (SDRAM_IKERNEL);			/*SDRAM_Page1*/
+.byte4 0x00400000;
+.byte4 (SDRAM_IKERNEL);		/*SDRAM_Page1*/
+.byte4 0x07C00000;
+.byte4 (SDRAM_IKERNEL);		/*SDRAM_Page14*/
+.byte4 0x00800000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page2*/
+.byte4 0x01000000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT			/*STAMP Memory regions*/
+.byte4 0x02000000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page13*/
+#endif
+.byte4 0xffffffff;			/* end of section - termination*/
+
+.align 4;
+.global ipdt_table
+ipdt_table:
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x00000000;
+.byte4 (SDRAM_IKERNEL);               /*SDRAM_Page0*/
+.byte4 0x00400000;
+.byte4 (SDRAM_IKERNEL);               /*SDRAM_Page1*/
+#endif
+.byte4 0x00800000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page3*/
+.byte4 0x01000000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT                  /*STAMP Memory regions*/
+.byte4  0x02000000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page8*/
+.byte4  0x02400000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page9*/
+.byte4  0x02800000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page10*/
+.byte4  0x02C00000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page11*/
+.byte4  0x03000000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page12*/
+.byte4  0x03400000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page13*/
+.byte4  0x03800000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page14*/
+.byte4  0x03C00000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page15*/
+#endif
+.byte4  0x20200000;
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank 2 (Secnd)*/
+.byte4  0x20100000;
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank 1 (Prim B)*/
+.byte4  0x20000000;
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank 0 (Prim A)*/
+.byte4  0x20300000;             /*Fix for Network*/
+.byte4  (SDRAM_EBIU);    /*Async Memory bank 3*/
+
+#ifdef CONFIG_STAMP
+.byte4        0x04000000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x04400000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x04800000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x04C00000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05000000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05400000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05800000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05C00000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x06000000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page25*/
+.byte4        0x06400000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page26*/
+.byte4        0x06800000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page27*/
+.byte4        0x06C00000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page28*/
+.byte4        0x07000000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page29*/
+.byte4        0x07400000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page30*/
+.byte4        0x07800000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page31*/
+#ifdef CONFIG_CPLB_INFO
+.byte4        0x07C00000;
+.byte4  (SDRAM_IKERNEL);        /*SDRAM_Page32*/
+#endif
+#endif
+.byte4 0xffffffff;                    /* end of section - termination*/
+
+/*********************************************************************
+ *			DCPLB TABLE		
+ ********************************************************************/
+
+.global dcplb_table
+dcplb_table:
+.byte4	0x00000000;
+.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
+.byte4	0x00400000; 
+.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
+.byte4	0x07C00000;
+.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page15*/
+.byte4	0x00800000; 
+.byte4 	(SDRAM_DGENERIC);	/*SDRAM_Page2*/
+.byte4 	0x00C00000; 
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page3*/
+.byte4	0x01000000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page4*/
+.byte4	0x01400000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page5*/
+.byte4	0x01800000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page6*/
+.byte4	0x01C00000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT	
+.byte4	0x02000000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page8*/
+.byte4	0x02400000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page9*/
+.byte4	0x02800000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page10*/
+.byte4	0x02C00000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page11*/
+.byte4	0x03000000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page12*/
+.byte4	0x03400000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page13*/
+.byte4	0x03800000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page14*/
+#endif
+.byte4	0xffffffff;		/*end of section - termination*/
+
+/**********************************************************************
+ *		PAGE DESCRIPTOR TABLE
+ * 
+ **********************************************************************/
+
+/* Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ * 
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */   
+.global dpdt_table
+dpdt_table:
+#ifdef CONFIG_CPLB_INFO
+.byte4        0x00000000;
+.byte4        (SDRAM_DKERNEL);        /*SDRAM_Page0*/
+.byte4        0x00400000; 
+.byte4        (SDRAM_DKERNEL);        /*SDRAM_Page1*/
+#endif
+.byte4        0x00800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page2*/
+.byte4        0x00C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page3*/
+.byte4        0x01000000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page4*/
+.byte4        0x01400000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page5*/
+.byte4        0x01800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page6*/
+.byte4        0x01C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page7*/
+
+#ifndef CONFIG_EZKIT
+.byte4        0x02000000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page8*/
+.byte4        0x02400000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page9*/
+.byte4        0x02800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page10*/
+.byte4        0x02C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page11*/
+.byte4        0x03000000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page12*/
+.byte4        0x03400000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page13*/
+.byte4        0x03800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page14*/
+.byte4        0x03C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page15*/
+#endif
+.byte4	0x20200000;
+.byte4	(SDRAM_EBIU);	/* Async Memory Bank 2 (Secnd)*/
+.byte4	0x20100000;
+.byte4	(SDRAM_EBIU);	/* Async Memory Bank 1 (Prim B)*/
+.byte4	0x20000000;	
+.byte4	(SDRAM_EBIU);	/* Async Memory Bank 0 (Prim A)*/
+.byte4	0x20300000;		/*Fix for Network*/
+.byte4  (SDRAM_EBIU);	/*Async Memory bank 3*/
+
+#ifdef CONFIG_STAMP	
+.byte4	0x04000000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x04400000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x04800000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x04C00000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x05000000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x05400000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x05800000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x05C00000;
+.byte4  (SDRAM_DGENERIC);
+.byte4	0x06000000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page25*/
+.byte4	0x06400000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page26*/
+.byte4	0x06800000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page27*/
+.byte4	0x06C00000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page28*/
+.byte4	0x07000000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page29*/
+.byte4	0x07400000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page30*/
+.byte4	0x07800000;
+.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page31*/
+#ifdef CONFIG_CPLB_INFO
+.byte4	0x07C00000;
+.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page32*/
+#endif
+#endif
+
+.byte4  0xFF900000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF901000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF902000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF903000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF904000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF905000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF906000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF907000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF800000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF801000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF802000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF803000;
+.byte4  (L1_DMEMORY);
+
+.byte4	0xffffffff;		/*end of section - termination*/
+
+#ifdef CONFIG_CPLB_INFO
+.global ipdt_swapcount_table;	/* swapin count first, then swapout count*/
+ipdt_swapcount_table:
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 10 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 20 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 30 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 40 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 50 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 60 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 70 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 80 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 90 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 100 */
+
+.global dpdt_swapcount_table;	/* swapin count first, then swapout count*/
+dpdt_swapcount_table:
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 10 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 20 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 30 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 40 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 50 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 60 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 70 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 80 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 80 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 100 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 110 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;	/* 120 */
+
+#endif
+
+#endif	/*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h
new file mode 100644
index 0000000..902308a
--- /dev/null
+++ b/include/asm-blackfin/cpu/bf533_irq.h
@@ -0,0 +1,137 @@
+/*
+ * U-boot bf533_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_IRQ_H_
+#define _BF533_IRQ_H_
+
+/*
+ * Interrupt source definitions
+ * Event Source			Core Event Name		Number
+ * 				EMU			0
+ * Reset			RST			1
+ * NMI				NMI			2
+ * Exception			EVX			3
+ * Reserved			--			4
+ * Hardware Error		IVHW			5
+ * Core Timer			IVTMR			6
+ * PLL Wakeup Interrupt		IVG7			7
+ * DMA Error (generic)		IVG7			8
+ * PPI Error Interrupt		IVG7			9
+ * SPORT0 Error Interrupt	IVG7			10
+ * SPORT1 Error Interrupt	IVG7			11
+ * SPI Error Interrupt		IVG7			12
+ * UART Error Interrupt		IVG7			13
+ * RTC Interrupt		IVG8			14
+ * DMA0 Interrupt (PPI)		IVG8			15
+ * DMA1 (SPORT0 RX)		IVG9			16
+ * DMA2 (SPORT0 TX)		IVG9			17
+ * DMA3 (SPORT1 RX)		IVG9			18
+ * DMA4 (SPORT1 TX)		IVG9			19
+ * DMA5 (PPI)			IVG10			20
+ * DMA6 (UART RX)		IVG10			21
+ * DMA7 (UART TX)		IVG10			22
+ * Timer0			IVG11			23
+ * Timer1			IVG11			24
+ * Timer2			IVG11			25
+ * PF Interrupt A		IVG12			26
+ * PF Interrupt B		IVG12			27
+ * DMA8/9 Interrupt		IVG13			28
+ * DMA10/11 Interrupt		IVG13			29
+ * Watchdog Timer		IVG13			30
+ * Software Interrupt 1		IVG14			31
+ * Software Interrupt 2		--
+ * (lowest priority)		IVG15			32
+ */
+
+/* The ABSTRACT IRQ definitions */
+
+/* The first seven of the following are fixed, 
+ * the rest you change if you need to
+ */
+
+#define	IRQ_EMU			0	/* Emulation */
+#define	IRQ_RST			1	/* reset */
+#define	IRQ_NMI			2	/* Non Maskable */
+#define	IRQ_EVX			3	/* Exception */
+#define	IRQ_UNUSED		4	/*  - unused interrupt */
+#define	IRQ_HWERR		5	/* Hardware Error */
+#define	IRQ_CORETMR		6	/* Core timer */
+#define	IRQ_PLL_WAKEUP		7	/* PLL Wakeup Interrupt */
+#define	IRQ_DMA_ERROR		8	/* DMA Error (general) */
+#define	IRQ_PPI_ERROR		9	/* PPI Error Interrupt */
+#define	IRQ_SPORT0_ERROR	10	/* SPORT0 Error Interrupt */
+#define	IRQ_SPORT1_ERROR	11	/* SPORT1 Error Interrupt */
+#define	IRQ_SPI_ERROR		12	/* SPI Error Interrupt */
+#define	IRQ_UART_ERROR		13	/* UART Error Interrupt */
+#define	IRQ_RTC			14	/* RTC Interrupt */
+#define	IRQ_PPI			15	/* DMA0 Interrupt (PPI) */
+#define	IRQ_SPORT0		16	/* DMA1 Interrupt (SPORT0 RX) */
+#define	IRQ_SPARE1		17	/* DMA2 Interrupt (SPORT0 TX) */
+#define	IRQ_SPORT1		18	/* DMA3 Interrupt (SPORT1 RX) */
+#define	IRQ_SPARE2		19	/* DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI			20	/* DMA5 Interrupt (SPI) */
+#define	IRQ_UART		21	/* DMA6 Interrupt (UART RX) */
+#define	IRQ_SPARE3		22	/* DMA7 Interrupt (UART TX) */
+#define	IRQ_TMR0		23	/* Timer 0 */
+#define	IRQ_TMR1		24	/* Timer 1 */
+#define	IRQ_TMR2		25	/* Timer 2 */
+#define	IRQ_PROG_INTA		26	/* Programmable Flags A (8) */
+#define	IRQ_PROG_INTB		27	/* Programmable Flags B (8) */
+#define	IRQ_MEM_DMA0		28	/* DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define	IRQ_MEM_DMA1		29	/* DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define	IRQ_WATCH	   	30	/* Watch Dog Timer */
+#define	IRQ_SW_INT1		31	/* Software Int 1 */
+#define	IRQ_SW_INT2		32	/* Software Int 2 (reserved for SYSCALL) */
+
+#define IRQ_UART_RX_BIT		0x4000
+#define IRQ_UART_TX_BIT		0x8000
+#define IRQ_UART_ERROR_BIT	0x40
+
+#define IVG7			7
+#define IVG8			8
+#define IVG9			9
+#define IVG10			10
+#define IVG11			11
+#define IVG12			12
+#define IVG13			13
+#define IVG14			14
+#define IVG15			15
+#define SYS_IRQS		33
+
+#endif
diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/cpu/bf533_rtc.h
new file mode 100644
index 0000000..bc09922
--- /dev/null
+++ b/include/asm-blackfin/cpu/bf533_rtc.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - bf533_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_RTC_H_
+#define _BF533_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_)	(60 * _x_)
+#define HRS_TO_SECS(_x_)	(60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_)	(24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY		(24 * 3600)
+#define NUM_SECS_IN_HOUR	(3600)
+#define NUM_SECS_IN_MIN		(60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF		17
+#define HOUR_BITS_OFF		12
+#define MIN_BITS_OFF		6
+#define SEC_BITS_OFF		0
+
+#endif
diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/cpu/bf533_serial.h
new file mode 100644
index 0000000..d5e162a
--- /dev/null
+++ b/include/asm-blackfin/cpu/bf533_serial.h
@@ -0,0 +1,79 @@
+/*
+ * U-boot bf533_serial.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _BF533_SERIAL_H_
+#define _BF533_SERIAL_H_
+
+#define BYTE_REF(addr)		(*((volatile char*)addr))
+#define HALFWORD_REF(addr)	(*((volatile short*)addr))
+#define WORD_REF(addr)		(*((volatile long*)addr))
+
+#define UART_THR_LO		HALFWORD_REF(UART_THR)
+#define UART_RBR_LO		HALFWORD_REF(UART_RBR)
+#define UART_DLL_LO		HALFWORD_REF(UART_DLL)
+#define UART_IER_LO		HALFWORD_REF(UART_IER)
+#define UART_IER_ERBFI		0x01
+#define UART_IER_ETBEI		0x02
+#define UART_IER_ELSI		0x04
+#define UART_IER_EDDSI		0x08
+
+#define UART_DLH_LO		HALFWORD_REF(UART_DLH)
+#define UART_IIR_LO		HALFWORD_REF(UART_IIR)
+#define UART_IIR_NOINT		0x01
+#define UART_IIR_STATUS		0x06
+#define UART_IIR_LSR		0x06
+#define UART_IIR_RBR		0x04
+#define UART_IIR_THR		0x02
+#define UART_IIR_MSR		0x00
+
+#define UART_LCR_LO		HALFWORD_REF(UART_LCR)
+#define UART_LCR_WLS5		0
+#define UART_LCR_WLS6		0x01
+#define UART_LCR_WLS7		0x02
+#define UART_LCR_WLS8		0x03
+#define UART_LCR_STB		0x04
+#define UART_LCR_PEN		0x08
+#define UART_LCR_EPS		0x10
+#define UART_LCR_SP		0x20
+#define UART_LCR_SB		0x40
+#define UART_LCR_DLAB		0x80
+
+#define UART_MCR_LO		HALFWORD_REF(UART_MCR)
+
+#define UART_LSR_LO		HALFWORD_REF(UART_LSR)
+#define UART_LSR_DR		0x01
+#define UART_LSR_OE		0x02
+#define UART_LSR_PE		0x04
+#define UART_LSR_FE		0x08
+#define UART_LSR_BI		0x10
+#define UART_LSR_THRE		0x20
+#define UART_LSR_TEMT		0x40
+
+#define UART_MSR_LO		HALFWORD_REF(UART_MSR)
+#define UART_SCR_LO		HALFWORD_REF(UART_SCR)
+#define UART_GCTL_LO		HALFWORD_REF(UART_GCTL)
+#define UART_GCTL_UCEN		0x01
+
+#endif
diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h
new file mode 100644
index 0000000..68d841d
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF531.h
@@ -0,0 +1,24 @@
+/*
+ * cdefBF531.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEFBF531_H
+#define _CDEFBF531_H
+
+#include <cdefBF532.h>
+
+#endif	/* _CDEFBF531_H */
diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h
new file mode 100644
index 0000000..a4d422f
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF532.h
@@ -0,0 +1,398 @@
+/*
+ * cdefBF532.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEF_BF532_H
+#define _CDEF_BF532_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning cdefBF532.h should only be included for 532 compatible chips.
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/cpu/defBF532.h>
+
+/* include core specific register pointer definitions */
+#include <asm/cpu/cdef_LPBlackfin.h>
+
+/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+
+/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
+#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
+#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
+#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
+#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
+#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
+#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
+#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
+#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
+#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
+#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
+#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
+#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
+#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
+#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
+#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
+#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
+#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
+
+/* DMA Test Registers */
+#define pDMA_CCOMP	((volatile unsigned long *)DMA_CCOMP)
+#define	pDMA_ACOMP	((volatile unsigned long *)DMA_ACOMP)
+#define	pDMA_MISR	((volatile unsigned long *)DMA_MISR)
+#define	pDMA_TCPER	((volatile unsigned short *)DMA_TCPER)
+#define	pDMA_TCCNT	((volatile unsigned short *)DMA_TCCNT)
+#define	pDMA_TMODE	((volatile unsigned short *)DMA_TMODE)
+#define	pDMA_TMCHAN	((volatile unsigned short *)DMA_TMCHAN)
+#define	pDMA_TMSTAT	((volatile unsigned short *)DMA_TMSTAT)
+#define	pDMA_TMBD	((volatile unsigned short *)DMA_TMBD)
+#define	pDMA_TMM0D	((volatile unsigned short *)DMA_TMM0D)
+#define	pDMA_TMM1D	((volatile unsigned short *)DMA_TMM1D)
+#define pDMA_TMMA	((volatile void **)DMA_TMMA)
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+
+/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
+/* #define L1SBAR 0xFFC04840 */	/* L1 SRAM Base Address Register */
+/* #define L1CSR  0xFFC04844 */	/* L1 SRAM Control Initialization Register */
+
+/*
+ * #define pDB_ACOMP ((volatile void **)DB_ACOMP)
+ * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
+ */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+
+/* UART Controller */
+#define pUART_THR ((volatile unsigned short *)UART_THR)
+#define pUART_RBR ((volatile unsigned short *)UART_RBR)
+#define pUART_DLL ((volatile unsigned short *)UART_DLL)
+#define pUART_IER ((volatile unsigned short *)UART_IER)
+#define pUART_DLH ((volatile unsigned short *)UART_DLH)
+#define pUART_IIR ((volatile unsigned short *)UART_IIR)
+#define pUART_LCR ((volatile unsigned short *)UART_LCR)
+#define pUART_MCR ((volatile unsigned short *)UART_MCR)
+#define pUART_LSR ((volatile unsigned short *)UART_LSR)
+
+/*
+ * #define UART_MSR
+ */
+#define pUART_SCR ((volatile unsigned short *)UART_SCR)
+#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
+
+/* SPI Controller */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+/* TIMER 0, 1, 2 Registers */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
+
+/* SPORT0 Controller */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* SPORT1 Controller */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+/* Parallel Peripheral Interface (PPI) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+#endif	/* _CDEF_BF532_H */
diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h
new file mode 100644
index 0000000..8c751e6
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF533.h
@@ -0,0 +1,24 @@
+/*
+ * cdefBF533.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEFBF533_H
+#define _CDEFBF533_H
+
+#include <asm/cpu/cdefBF532.h>
+
+#endif	/* _CDEFBF533_H */
diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h
new file mode 100644
index 0000000..db4eaa9
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF53x.h
@@ -0,0 +1,32 @@
+/************************************************************************
+ *
+ * cdefBF53x.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF53x_H
+#define _CDEFBF53x_H
+
+#if defined(__ADSPBF531__)
+	#include <asm/cpu/cdefBF531.h>
+#elif defined(__ADSPBF532__)
+	#include <asm/cpu/cdefBF532.h>
+#elif defined(__ADSPBF533__)
+	#include <asm/cpu/cdefBF533.h>
+#elif defined(__ADSPBF561__)
+	#include <asm/cpu/cdefBF561.h>
+#elif defined(__ADSPBF535__)
+	#include <asm/cpu/cdefBF535.h>
+#elif defined(__AD6532__)
+	#include <sam/cpu/cdefAD6532.h>
+#else
+	#if defined(__ADSPLPBLACKFIN__)
+		#include <asm/cpu/cdefBF532.h>
+	#else
+		#include <asm/cpu/cdefBF535.h>
+	#endif
+#endif
+
+#endif	/* _CDEFBF53x_H */
diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h
new file mode 100644
index 0000000..e6471cb
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdef_LPBlackfin.h
@@ -0,0 +1,185 @@
+/*
+ * cdef_LPBlackfin.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEF_LPBLACKFIN_H
+#define _CDEF_LPBLACKFIN_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+ * #endif
+ */
+#include <asm/cpu/def_LPBlackfin.h>
+
+/* Cache & SRAM Memory */
+#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
+#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
+#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
+#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
+
+/* #define MMR_TIMEOUT 0xFFE00010 */	/* Memory-Mapped Register Timeout Register */
+#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
+#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
+#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
+#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
+#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
+#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
+#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
+#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
+#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
+#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
+#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
+#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
+#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
+#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
+#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
+#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
+#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
+#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
+#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
+#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
+#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
+#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
+#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
+#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
+#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
+#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
+#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
+#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
+#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
+#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
+#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
+#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
+#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
+
+/* #define DTEST_INDEX            0xFFE00304 */ 	/* Data Test Index Register */
+#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
+#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
+
+/*
+ * # define DTEST_DATA2	0xFFE00408   Data Test Data Register
+ * #define DTEST_DATA3	0xFFE0040C   Data Test Data Register
+ */
+#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
+#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
+#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
+#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
+#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
+#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
+#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
+#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
+#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
+#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
+#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
+#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
+#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
+#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
+#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
+#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
+#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
+#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
+#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
+#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
+#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
+#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
+#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
+#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
+#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
+#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
+#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
+#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
+#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
+#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
+#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
+#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
+#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
+#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
+#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
+#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
+
+/* #define ITEST_INDEX 0xFFE01304 */	/* Instruction Test Index Register */
+#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
+#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
+
+/* Event/Interrupt Registers */
+#define pEVT0 ((volatile void **)EVT0)
+#define pEVT1 ((volatile void **)EVT1)
+#define pEVT2 ((volatile void **)EVT2)
+#define pEVT3 ((volatile void **)EVT3)
+#define pEVT4 ((volatile void **)EVT4)
+#define pEVT5 ((volatile void **)EVT5)
+#define pEVT6 ((volatile void **)EVT6)
+#define pEVT7 ((volatile void **)EVT7)
+#define pEVT8 ((volatile void **)EVT8)
+#define pEVT9 ((volatile void **)EVT9)
+#define pEVT10 ((volatile void **)EVT10)
+#define pEVT11 ((volatile void **)EVT11)
+#define pEVT12 ((volatile void **)EVT12)
+#define pEVT13 ((volatile void **)EVT13)
+#define pEVT14 ((volatile void **)EVT14)
+#define pEVT15 ((volatile void **)EVT15)
+#define pIMASK ((volatile unsigned long *)IMASK)
+#define pIPEND ((volatile unsigned long *)IPEND)
+#define pILAT ((volatile unsigned long *)ILAT)
+
+/* Core Timer Registers */
+#define pTCNTL ((volatile unsigned long *)TCNTL)
+#define pTPERIOD ((volatile unsigned long *)TPERIOD)
+#define pTSCALE ((volatile unsigned long *)TSCALE)
+#define pTCOUNT ((volatile unsigned long *)TCOUNT)
+
+/* Debug/MP/Emulation Registers */
+#define pDSPID ((volatile unsigned long *)DSPID)
+#define pDBGCTL ((volatile unsigned long *)DBGCTL)
+#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
+#define pEMUDAT ((volatile unsigned long *)EMUDAT)
+
+/* Trace Buffer Registers */
+#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
+#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
+#define pTBUF ((volatile void **)TBUF)
+
+/* Watch Point Control Registers */
+#define pWPIACTL ((volatile unsigned long *)WPIACTL)
+#define pWPIA0 ((volatile void **)WPIA0)
+#define pWPIA1 ((volatile void **)WPIA1)
+#define pWPIA2 ((volatile void **)WPIA2)
+#define pWPIA3 ((volatile void **)WPIA3)
+#define pWPIA4 ((volatile void **)WPIA4)
+#define pWPIA5 ((volatile void **)WPIA5)
+#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
+#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
+#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
+#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
+#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
+#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
+#define pWPDACTL ((volatile unsigned long *)WPDACTL)
+#define pWPDA0 ((volatile void **)WPDA0)
+#define pWPDA1 ((volatile void **)WPDA1)
+#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
+#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
+#define pWPSTAT ((volatile unsigned long *)WPSTAT)
+
+/* Performance Monitor Registers */
+#define pPFCTL ((volatile unsigned long *)PFCTL)
+#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
+#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+
+/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
+
+#endif	/* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h
new file mode 100644
index 0000000..6c7cd5a
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF531.h
@@ -0,0 +1,24 @@
+/*
+ * defBF531.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEFBF531_H
+#define _DEFBF531_H
+
+#include <defBF532.h>
+
+#endif /* _DEFBF531_H */
diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h
new file mode 100644
index 0000000..c30d5cd
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF532.h
@@ -0,0 +1,1159 @@
+/*
+ * defBF532.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_BF532_H
+#define _DEF_BF532_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning defBF532.h should only be included for 532 compatible chips
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/cpu/def_LPBlackfin.h>
+
+/* Helper macros 
+ * usage:
+ *  P0.H = HI(UART_THR);
+ *  P0.L = LO(UART_THR);
+ */
+
+#define LO(con32)		((con32) & 0xFFFF)
+#define lo(con32)		((con32) & 0xFFFF)
+#define HI(con32)		(((con32) >> 16) & 0xFFFF)
+#define hi(con32)		(((con32) >> 16) & 0xFFFF)
+
+/*
+ * System MMR Register Map
+ */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL			0xFFC00000	/* PLL Control register (16-bit) */
+#define PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
+#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
+#define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count register (16-bit) */
+#define	CHIPID			0xFFC00014	/* Chip ID register (32-bit)	*/
+#define SWRST			0xFFC00100	/* Software Reset Register (16-bit) */
+#define SYSCR			0xFFC00104	/* System Configuration register */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SIC_RVECT		0xFFC00108	/* Interrupt Reset Vector Address Register */
+#define SIC_IMASK		0xFFC0010C	/* Interrupt Mask Register */
+#define SIC_IAR0		0xFFC00110	/* Interrupt Assignment Register 0 */
+#define SIC_IAR1		0xFFC00114	/* Interrupt Assignment Register 1 */
+#define SIC_IAR2		0xFFC00118	/* Interrupt Assignment Register 2 */
+#define SIC_ISR			0xFFC00120	/* Interrupt Status Register */
+#define SIC_IWR			0xFFC00124	/* Interrupt Wakeup Register */
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL		0xFFC00200	/* Watchdog Control Register */
+#define WDOG_CNT		0xFFC00204	/* Watchdog Count Register */
+#define WDOG_STAT		0xFFC00208	/* Watchdog Status Register */
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT		0xFFC00300	/* RTC Status Register */
+#define RTC_ICTL		0xFFC00304	/* RTC Interrupt Control Register */
+#define RTC_ISTAT		0xFFC00308	/* RTC Interrupt Status Register */
+#define RTC_SWCNT		0xFFC0030C	/* RTC Stopwatch Count Register */
+#define RTC_ALARM		0xFFC00310	/* RTC Alarm Time Register */
+#define RTC_FAST		0xFFC00314	/* RTC Prescaler Enable Register */
+#define RTC_PREN		0xFFC00314	/* RTC Prescaler Enable Register (alternate macro) */
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR		0xFFC00400	/* Transmit Holding register */
+#define UART_RBR		0xFFC00400	/* Receive Buffer register */
+#define UART_DLL		0xFFC00400	/* Divisor Latch (Low-Byte) */
+#define UART_IER		0xFFC00404	/* Interrupt Enable Register */
+#define UART_DLH		0xFFC00404	/* Divisor Latch (High-Byte) */
+#define UART_IIR		0xFFC00408	/* Interrupt Identification Register */
+#define UART_LCR		0xFFC0040C	/* Line Control Register */
+#define UART_MCR		0xFFC00410	/* Modem Control Register */
+#define UART_LSR		0xFFC00414	/* Line Status Register */
+/* #define UART_MSR 0xFFC00418 */	/* Modem Status Register (UNUSED in ADSP-BF532) */
+#define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
+#define UART_GCTL		0xFFC00424	/* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL			0xFFC00500	/* SPI Control Register */
+#define SPI_FLG			0xFFC00504	/* SPI Flag register */
+#define SPI_STAT		0xFFC00508	/* SPI Status register */
+#define SPI_TDBR		0xFFC0050C	/* SPI Transmit Data Buffer Register */
+#define SPI_RDBR		0xFFC00510	/* SPI Receive Data Buffer Register */
+#define SPI_BAUD		0xFFC00514	/* SPI Baud rate Register */
+#define SPI_SHADOW		0xFFC00518	/* SPI_RDBR Shadow Register */
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register */
+#define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register */
+#define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register */
+#define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register */
+
+#define TIMER1_CONFIG		0xFFC00610	/*  Timer 1 Configuration Register */
+#define TIMER1_COUNTER		0xFFC00614	/*  Timer 1 Counter Register */
+#define TIMER1_PERIOD		0xFFC00618	/*  Timer 1 Period Register */
+#define TIMER1_WIDTH		0xFFC0061C	/*  Timer 1 Width Register */
+
+#define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register */
+#define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register */
+#define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register */
+#define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register */
+
+#define TIMER_ENABLE		0xFFC00640	/* Timer Enable Register */
+#define TIMER_DISABLE		0xFFC00644	/* Timer Disable Register */
+#define TIMER_STATUS		0xFFC00648	/* Timer Status Register */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D		0xFFC00700	/* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C		0xFFC00704	/* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S		0xFFC00708	/* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T		0xFFC0070C	/* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D		0xFFC00710	/* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C		0xFFC00714	/* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S		0xFFC00718	/* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T		0xFFC0071C	/* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D		0xFFC00720	/* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C		0xFFC00724	/* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S		0xFFC00728	/* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T		0xFFC0072C	/* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR			0xFFC00730	/* Peripheral Flag Direction Register */
+#define FIO_POLAR		0xFFC00734	/* Flag Source Polarity Register */
+#define FIO_EDGE		0xFFC00738	/* Flag Source Sensitivity Register */
+#define FIO_BOTH		0xFFC0073C	/* Flag Set on BOTH Edges Register */
+#define FIO_INEN		0xFFC00740	/* Flag Input Enable Register */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1		0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2		0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX		0xFFC00810	/* SPORT0 TX Data Register */
+#define SPORT0_RX		0xFFC00818	/* SPORT0 RX Data Register */
+#define SPORT0_RCR1		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT		0xFFC00830	/* SPORT0 Status Register */
+#define SPORT0_CHNL		0xFFC00834	/* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX		0xFFC00910	/* SPORT1 TX Data Register */
+#define SPORT1_RX		0xFFC00918	/* SPORT1 RX Data Register */
+#define SPORT1_RCR1		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT		0xFFC00930	/* SPORT1 Status Register */
+#define SPORT1_CHNL		0xFFC00934	/* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */
+#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */
+#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register */
+
+/* DMA Test Registers */
+#define DMA_CCOMP		0xFFC00B04	/* DMA Cycle Count Register */
+#define DMA_ACOMP		0xFFC00B00	/* Debug Compare Address Register */
+#define DMA_MISR		0xFFC00B08	/* MISR Register */
+#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */
+#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register */
+#define DMA_TMODE		0xFFC00B14	/* DMA Test Modes Register */
+#define DMA_TMCHAN		0xFFC00B18	/* DMA Testmode Selected Channel Register */
+#define DMA_TMSTAT		0xFFC00B1C	/* DMA Testmode Channel Status Register */
+#define DMA_TMBD		0xFFC00B20	/* DMA Testmode DAB Bus Data Register */
+#define DMA_TMM0D		0xFFC00B24	/* DMA Testmode Mem0 Data Register */
+#define DMA_TMM1D		0xFFC00B28	/* DMA Testmode Mem1 Data Register */
+#define DMA_TMMA		0xFFC00B2C	/* DMA Testmode Memory Address Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_CONFIG		0xFFC00C08	/* DMA Channel 0 Configuration Register */
+#define DMA0_NEXT_DESC_PTR	0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR		0xFFC00C04	/* DMA Channel 0 Start Address Register */
+#define DMA0_X_COUNT		0xFFC00C10	/* DMA Channel 0 X Count Register */
+#define DMA0_Y_COUNT		0xFFC00C18	/* DMA Channel 0 Y Count Register */
+#define DMA0_X_MODIFY		0xFFC00C14	/* DMA Channel 0 X Modify Register */
+#define DMA0_Y_MODIFY		0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR	0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR		0xFFC00C24	/* DMA Channel 0 Current Address Register */
+#define DMA0_CURR_X_COUNT	0xFFC00C30	/* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT	0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
+#define DMA0_IRQ_STATUS		0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register */
+
+#define DMA1_CONFIG		0xFFC00C48	/* DMA Channel 1 Configuration Register */
+#define DMA1_NEXT_DESC_PTR	0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR		0xFFC00C44	/* DMA Channel 1 Start Address Register */
+#define DMA1_X_COUNT		0xFFC00C50	/* DMA Channel 1 X Count Register */
+#define DMA1_Y_COUNT		0xFFC00C58	/* DMA Channel 1 Y Count Register */
+#define DMA1_X_MODIFY		0xFFC00C54	/* DMA Channel 1 X Modify Register */
+#define DMA1_Y_MODIFY		0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR	0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR		0xFFC00C64	/* DMA Channel 1 Current Address Register */
+#define DMA1_CURR_X_COUNT	0xFFC00C70	/* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT	0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
+#define DMA1_IRQ_STATUS		0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register */
+
+#define DMA2_CONFIG		0xFFC00C88	/* DMA Channel 2 Configuration Register */
+#define DMA2_NEXT_DESC_PTR	0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR		0xFFC00C84	/* DMA Channel 2 Start Address Register */
+#define DMA2_X_COUNT		0xFFC00C90	/* DMA Channel 2 X Count Register */
+#define DMA2_Y_COUNT		0xFFC00C98	/* DMA Channel 2 Y Count Register */
+#define DMA2_X_MODIFY		0xFFC00C94	/* DMA Channel 2 X Modify Register */
+#define DMA2_Y_MODIFY		0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR	0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR		0xFFC00CA4	/* DMA Channel 2 Current Address Register */
+#define DMA2_CURR_X_COUNT	0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT	0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
+#define DMA2_IRQ_STATUS		0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register */
+
+#define DMA3_CONFIG		0xFFC00CC8	/* DMA Channel 3 Configuration Register */
+#define DMA3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR		0xFFC00CC4	/* DMA Channel 3 Start Address Register */
+#define DMA3_X_COUNT		0xFFC00CD0	/* DMA Channel 3 X Count Register */
+#define DMA3_Y_COUNT		0xFFC00CD8	/* DMA Channel 3 Y Count Register */
+#define DMA3_X_MODIFY		0xFFC00CD4	/* DMA Channel 3 X Modify Register */
+#define DMA3_Y_MODIFY		0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR	0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR		0xFFC00CE4	/* DMA Channel 3 Current Address Register */
+#define DMA3_CURR_X_COUNT	0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT	0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
+#define DMA3_IRQ_STATUS		0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register */
+
+#define DMA4_CONFIG		0xFFC00D08	/* DMA Channel 4 Configuration Register */
+#define DMA4_NEXT_DESC_PTR	0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR		0xFFC00D04	/* DMA Channel 4 Start Address Register */
+#define DMA4_X_COUNT		0xFFC00D10	/* DMA Channel 4 X Count Register */
+#define DMA4_Y_COUNT		0xFFC00D18	/* DMA Channel 4 Y Count Register */
+#define DMA4_X_MODIFY		0xFFC00D14	/* DMA Channel 4 X Modify Register */
+#define DMA4_Y_MODIFY		0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR	0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR		0xFFC00D24	/* DMA Channel 4 Current Address Register */
+#define DMA4_CURR_X_COUNT	0xFFC00D30	/* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT	0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
+#define DMA4_IRQ_STATUS		0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register */
+
+#define DMA5_CONFIG		0xFFC00D48	/* DMA Channel 5 Configuration Register */
+#define DMA5_NEXT_DESC_PTR	0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR		0xFFC00D44	/* DMA Channel 5 Start Address Register */
+#define DMA5_X_COUNT		0xFFC00D50	/* DMA Channel 5 X Count Register */
+#define DMA5_Y_COUNT		0xFFC00D58	/* DMA Channel 5 Y Count Register */
+#define DMA5_X_MODIFY		0xFFC00D54	/* DMA Channel 5 X Modify Register */
+#define DMA5_Y_MODIFY		0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR	0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR		0xFFC00D64	/* DMA Channel 5 Current Address Register */
+#define DMA5_CURR_X_COUNT	0xFFC00D70	/* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT	0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
+#define DMA5_IRQ_STATUS		0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register */
+
+#define DMA6_CONFIG		0xFFC00D88	/* DMA Channel 6 Configuration Register */
+#define DMA6_NEXT_DESC_PTR	0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR		0xFFC00D84	/* DMA Channel 6 Start Address Register */
+#define DMA6_X_COUNT		0xFFC00D90	/* DMA Channel 6 X Count Register */
+#define DMA6_Y_COUNT		0xFFC00D98	/* DMA Channel 6 Y Count Register */
+#define DMA6_X_MODIFY		0xFFC00D94	/* DMA Channel 6 X Modify Register */
+#define DMA6_Y_MODIFY		0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR	0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR		0xFFC00DA4	/* DMA Channel 6 Current Address Register */
+#define DMA6_CURR_X_COUNT	0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT	0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */
+#define DMA6_IRQ_STATUS		0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register */
+
+#define DMA7_CONFIG		0xFFC00DC8	/* DMA Channel 7 Configuration Register */
+#define DMA7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR		0xFFC00DC4	/* DMA Channel 7 Start Address Register */
+#define DMA7_X_COUNT		0xFFC00DD0	/* DMA Channel 7 X Count Register */
+#define DMA7_Y_COUNT		0xFFC00DD8	/* DMA Channel 7 Y Count Register */
+#define DMA7_X_MODIFY		0xFFC00DD4	/* DMA Channel 7 X Modify Register */
+#define DMA7_Y_MODIFY		0xFFC00DDC	/* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR	0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR		0xFFC00DE4	/* DMA Channel 7 Current Address Register */
+#define DMA7_CURR_X_COUNT	0xFFC00DF0	/* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT	0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */
+#define DMA7_IRQ_STATUS		0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register */
+
+#define MDMA_D1_CONFIG		0xFFC00E88	/* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_NEXT_DESC_PTR	0xFFC00E80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR	0xFFC00E84	/* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_X_COUNT		0xFFC00E90	/* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_Y_COUNT		0xFFC00E98	/* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_X_MODIFY	0xFFC00E94	/* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_MODIFY	0xFFC00E9C	/* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR	0xFFC00EA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR	0xFFC00EA4	/* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_CURR_X_COUNT	0xFFC00EB0	/* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT	0xFFC00EB8	/* MemDMA Stream 1 Destination Current Y Count Register */
+#define MDMA_D1_IRQ_STATUS	0xFFC00EA8	/* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP	0xFFC00EAC	/* MemDMA Stream 1 Destination Peripheral Map Register */
+
+#define MDMA_S1_CONFIG		0xFFC00EC8	/* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_NEXT_DESC_PTR	0xFFC00EC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR	0xFFC00EC4	/* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_X_COUNT		0xFFC00ED0	/* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_Y_COUNT		0xFFC00ED8	/* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_X_MODIFY	0xFFC00ED4	/* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_MODIFY	0xFFC00EDC	/* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR	0xFFC00EE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR	0xFFC00EE4	/* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_CURR_X_COUNT	0xFFC00EF0	/* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT	0xFFC00EF8	/* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_S1_IRQ_STATUS	0xFFC00EE8	/* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP	0xFFC00EEC	/* MemDMA Stream 1 Source Peripheral Map Register */
+
+#define MDMA_D0_CONFIG		0xFFC00E08	/* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_NEXT_DESC_PTR	0xFFC00E00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR	0xFFC00E04	/* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_X_COUNT		0xFFC00E10	/* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_Y_COUNT		0xFFC00E18	/* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_X_MODIFY	0xFFC00E14	/* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_MODIFY	0xFFC00E1C	/* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR	0xFFC00E20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR	0xFFC00E24	/* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_CURR_X_COUNT	0xFFC00E30	/* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT	0xFFC00E38	/* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_D0_IRQ_STATUS	0xFFC00E28	/* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP	0xFFC00E2C	/* MemDMA Stream 0 Destination Peripheral Map Register */
+
+#define MDMA_S0_CONFIG		0xFFC00E48	/* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_NEXT_DESC_PTR	0xFFC00E40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR	0xFFC00E44	/* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_X_COUNT		0xFFC00E50	/* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_Y_COUNT		0xFFC00E58	/* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_X_MODIFY	0xFFC00E54	/* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_MODIFY	0xFFC00E5C	/* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR	0xFFC00E60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR	0xFFC00E64	/* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_CURR_X_COUNT	0xFFC00E70	/* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT	0xFFC00E78	/* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_S0_IRQ_STATUS	0xFFC00E68	/* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP	0xFFC00E6C	/* MemDMA Stream 0 Source Peripheral Map Register */
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL		0xFFC01000	/* PPI Control Register */
+#define PPI_STATUS		0xFFC01004	/* PPI Status Register */
+#define PPI_COUNT		0xFFC01008	/* PPI Transfer Count Register */
+#define PPI_DELAY		0xFFC0100C	/* PPI Delay Count Register */
+#define PPI_FRAME		0xFFC01010	/* PPI Frame Length Register */
+
+/*
+ * System MMR Register Bits
+ */
+/*
+ * PLL AND RESET MASKS
+ */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN		0x00000000	/* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2		0x00000001	/* Pass CLKIN/2 to PLL */
+#define PLL_OFF			0x00000002	/* Shut off PLL clocks */
+#define STOPCK_OFF		0x00000008	/* Core clock off */
+#define PDWN			0x00000020	/* Put the PLL in a Deep Sleep state */
+#define BYPASS			0x00000100	/* Bypass the PLL */
+
+/* PLL_DIV Masks */
+#define SCLK_DIV(x)		(x)		/* SCLK = VCO / x */
+
+#define CCLK_DIV1		0x00000000	/* CCLK = VCO / 1 */
+#define CCLK_DIV2		0x00000010	/* CCLK = VCO / 2 */
+#define CCLK_DIV4		0x00000020	/* CCLK = VCO / 4 */
+#define CCLK_DIV8		0x00000030	/* CCLK = VCO / 8 */
+
+/* SWRST Mask */
+#define SYSTEM_RESET		0x00000007	/* Initiates a system software reset */
+
+/*
+ * SYSTEM INTERRUPT CONTROLLER MASKS
+ */
+
+/* SIC_IAR0 Masks */
+#define P0_IVG(x)		((x)-7)		/* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x)		((x)-7) << 0x4	/* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x)		((x)-7) << 0x8	/* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x)		((x)-7) << 0xC	/* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x)		((x)-7) << 0x10	/* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x)		((x)-7) << 0x14	/* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x)		((x)-7) << 0x18	/* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x)		((x)-7) << 0x1C	/* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Masks */
+#define P8_IVG(x)		((x)-7)		/* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x)		((x)-7) << 0x4	/* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x)		((x)-7) << 0x8	/* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x)		((x)-7) << 0xC	/* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x)		((x)-7) << 0x10	/* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x)		((x)-7) << 0x14	/* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x)		((x)-7) << 0x18	/* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x)		((x)-7) << 0x1C	/* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Masks */
+#define P16_IVG(x)		((x)-7)		/* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x)		((x)-7) << 0x4	/* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x)		((x)-7) << 0x8	/* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x)		((x)-7) << 0xC	/* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x)		((x)-7) << 0x10	/* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x)		((x)-7) << 0x14	/* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x)		((x)-7) << 0x18	/* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x)		((x)-7) << 0x1C	/* Peripheral #23 assigned IVG #x */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL		0x00000000	/* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL		0xFFFFFFFF	/* Mask all peripheral interrupts */
+#define SIC_MASK(x)		(1 << (x))	/* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)		(0xFFFFFFFF ^ (1 << (x)))	/* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL		0x00000000	/* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL		0xFFFFFFFF	/* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x)		(1 << (x))	/* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)		(0xFFFFFFFF ^ (1 << (x)))	/*  Wakeup Disable Peripheral #x */
+
+/*
+ * WATCHDOG TIMER MASKS
+ */
+/* Watchdog Timer WDOG_CTL Register */
+#define ICTL(x)			((x<<1) & 0x0006)
+#define ENABLE_RESET		0x00000000	/* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI		0x00000002	/* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI		0x00000004	/* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT		0x00000006	/* Disable Watchdog Timer interrupts */
+
+#define TMR_EN			0x0000
+#define TMR_DIS			0x0AD0
+#define TRO			0x8000
+
+#define ICTL_P0			0x01
+#define ICTL_P1			0x02
+#define TRO_P			0x0F
+
+/* RTC_STAT and RTC_ALARM register */
+#define	RTSEC			0x0000003F	/* Real-Time Clock Seconds */
+#define	RTMIN			0x00000FC0	/* Real-Time Clock Minutes */
+#define	RTHR			0x0001F000	/* Real-Time Clock Hours */
+#define	RTDAY			0xFFFE0000	/* Real-Time Clock Days */
+
+/* RTC_ICTL register */
+#define	SWIE			0x0001		/* Stopwatch Interrupt Enable */
+#define	AIE			0x0002		/* Alarm Interrupt Enable */
+#define	SIE			0x0004		/* Seconds (1 Hz) Interrupt Enable */
+#define	MIE			0x0008		/* Minutes Interrupt Enable */
+#define	HIE			0x0010		/* Hours Interrupt Enable */
+#define	DIE			0x0020		/* 24 Hours (Days) Interrupt Enable */
+#define	DAIE			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define	WCIE			0x8000		/* Write Complete Interrupt Enable */
+
+/* RTC_ISTAT register */
+#define	SWEF			0x0001		/* Stopwatch Event Flag */
+#define	AEF			0x0002		/* Alarm Event Flag */
+#define	SEF			0x0004		/* Seconds (1 Hz) Event Flag */
+#define	MEF			0x0008		/* Minutes Event Flag */
+#define	HEF			0x0010		/* Hours Event Flag */
+#define	DEF			0x0020		/* 24 Hours (Days) Event Flag */
+#define	DAEF			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define	WPS			0x4000		/* Write Pending Status (RO) */
+#define	WCOM			0x8000		/* Write Complete */
+
+/* RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE		0x00000001	/* Enable prescaler so RTC runs at 1 Hz */
+#define PREN			0x00000001	/* ** Must be set after power-up for proper operation of RTC */
+
+/*
+ * UART CONTROLLER MASKS
+ */
+
+/* UART_LCR Register */
+#define DLAB			0x80
+#define SB			0x40
+#define STP			0x20
+#define EPS			0x10
+#define PEN			0x08
+#define STB			0x04
+#define WLS(x)			((x-5) & 0x03)
+
+#define DLAB_P			0x07
+#define SB_P			0x06
+#define STP_P			0x05
+#define EPS_P			0x04
+#define PEN_P			0x03
+#define STB_P			0x02
+#define WLS_P1			0x01
+#define WLS_P0			0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA		0x10
+#define LOOP_ENA_P		0x04
+
+/* UART_LSR Register */
+#define TEMT			0x40
+#define THRE			0x20
+#define BI			0x10
+#define FE			0x08
+#define PE			0x04
+#define OE			0x02
+#define DR			0x01
+
+#define TEMP_P			0x06
+#define THRE_P			0x05
+#define BI_P			0x04
+#define FE_P			0x03
+#define PE_P			0x02
+#define OE_P			0x01
+#define DR_P			0x00
+
+/* UART_IER Register */
+#define ELSI			0x04
+#define ETBEI			0x02
+#define ERBFI			0x01
+
+#define ELSI_P			0x02
+#define ETBEI_P			0x01
+#define ERBFI_P			0x00
+
+/* UART_IIR Register */
+#define STATUS(x)		((x << 1) & 0x06)
+#define NINT			0x01
+#define STATUS_P1		0x02
+#define STATUS_P0		0x01
+#define NINT_P			0x00
+
+/* UART_GCTL Register */
+#define FFE			0x20
+#define FPE			0x10
+#define RPOLC			0x08
+#define TPOLC			0x04
+#define IREN			0x02
+#define UCEN			0x01
+
+#define FFE_P			0x05
+#define FPE_P			0x04
+#define RPOLC_P			0x03
+#define TPOLC_P			0x02
+#define IREN_P			0x01
+#define UCEN_P			0x00
+
+/*
+ * SERIAL PORT MASKS
+ */
+/* SPORTx_TCR1 Masks */
+#define TSPEN    		0x0001		/* TX enable */
+#define ITCLK    		0x0002		/* Internal TX Clock Select */
+#define TDTYPE			0x000C		/* TX Data Formatting Select */
+#define TLSBIT			0x0010		/* TX Bit Order */
+#define ITFS			0x0200		/* Internal TX Frame Sync Select */
+#define TFSR			0x0400		/* TX Frame Sync Required Select */
+#define DITFS			0x0800		/* Data Independent TX Frame Sync Select */
+#define LTFS			0x1000		/* Low TX Frame Sync Select */
+#define LATFS			0x2000		/* Late TX Frame Sync Select */
+#define TCKFE			0x4000		/* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN			0x001F		/*TX Word Length */
+#define TXSE			0x0100		/*TX Secondary Enable */
+#define TSFSE			0x0200		/*TX Stereo Frame Sync Enable */
+#define TRFST			0x0400		/*TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN			0x0001		/* RX enable */
+#define IRCLK			0x0002		/* Internal RX Clock Select */
+#define RDTYPE			0x000C		/* RX Data Formatting Select */
+#define RULAW			0x0008		/* u-Law enable */
+#define RALAW			0x000C		/* A-Law enable */
+#define RLSBIT			0x0010		/* RX Bit Order */
+#define IRFS			0x0200		/* Internal RX Frame Sync Select */
+#define RFSR			0x0400		/* RX Frame Sync Required Select */
+#define LRFS			0x1000		/* Low RX Frame Sync Select */
+#define LARFS			0x2000		/* Late RX Frame Sync Select */
+#define RCKFE			0x4000		/* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN			0x001F		/* RX Word Length */
+#define RXSE			0x0100		/* RX Secondary Enable */
+#define RSFSE			0x0200		/* RX Stereo Frame Sync Enable */
+#define RRFST			0x0400		/* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE			0x0001		/* RX FIFO Not Empty Status */
+#define RUVF			0x0002		/* RX Underflow Status */
+#define ROVF			0x0004		/* RX Overflow Status */
+#define TXF			0x0008		/* TX FIFO Full Status */
+#define TUVF			0x0010		/* TX Underflow Status */
+#define TOVF			0x0020		/* TX Overflow Status */
+#define TXHRE			0x0040		/* TX Hold Register Empty */
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE			0x0000F000	/* Multichannel Window Size Field */
+#define WOFF			0x000003FF	/* /Multichannel Window Offset Field */
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM			0x00000003	/* Multichannel Clock Recovery Mode */
+#define MCDTXPE			0x00000004	/* Multichannel DMA Transmit Packing */
+#define MCDRXPE			0x00000008	/* Multichannel DMA Receive Packing */
+#define MCMEN			0x00000010	/* Multichannel Frame Mode Enable */
+#define FSDR			0x00000080	/* Multichannel Frame Sync to Data Relationship */
+#define MFD			0x0000F000	/* Multichannel Frame Delay */
+
+/*
+ * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
+ */
+
+/* PPI_CONTROL Masks */
+#define PORT_EN			0x00000001	/* PPI Port Enable */
+#define PORT_DIR		0x00000002	/* PPI Port Direction */
+#define XFR_TYPE		0x0000000C	/* PPI Transfer Type */
+#define PORT_CFG		0x00000030	/* PPI Port Configuration */
+#define FLD_SEL			0x00000040	/* PPI Active Field Select */
+#define PACK_EN			0x00000080	/* PPI Packing Mode */
+#define DMA32			0x00000100	/* PPI 32-bit DMA Enable */
+#define SKIP_EN			0x00000200	/* PPI Skip Element Enable */
+#define SKIP_EO			0x00000400	/* PPI Skip Even/Odd Elements */
+#define DLENGTH			0x00003800	/* PPI Data Length */
+#define DLEN_8			0x0		/* PPI Data Length mask for DLEN=8 */
+#define DLEN(x)			(((x-9) & 0x07) << 11)	/* PPI Data Length (only works for x=10-->x=16) */
+#define POL			0x0000C000	/* PPI Signal Polarities */
+
+/* PPI_STATUS Masks */
+#define FLD			0x00000400	/* Field Indicator */
+#define FT_ERR			0x00000800	/* Frame Track Error */
+#define OVR			0x00001000	/* FIFO Overflow Error */
+#define UNDR			0x00002000	/* FIFO Underrun Error */
+#define ERR_DET			0x00004000	/* Error Detected Indicator */
+#define ERR_NCOR		0x00008000	/* Error Not Corrected Indicator */
+
+/*
+ * DMA CONTROLLER MASKS
+ */
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN			0x00000001	/* Channel Enable */
+#define WNR			0x00000002	/* Channel Direction (W/R*) */
+#define WDSIZE_8		0x00000000	/* Word Size 8 bits */
+#define WDSIZE_16		0x00000004	/* Word Size 16 bits */
+#define WDSIZE_32		0x00000008	/* Word Size 32 bits */
+#define DMA2D			0x00000010	/* 2D/1D* Mode */
+#define RESTART			0x00000020	/* Restart */
+#define DI_SEL			0x00000040	/* Data Interrupt Select */
+#define DI_EN			0x00000080	/* Data Interrupt Enable */
+#define NDSIZE			0x00000900	/* Next Descriptor Size */
+#define FLOW			0x00007000	/* Flow Control */
+
+#define DMAEN_P			0		/* Channel Enable */
+#define WNR_P			1		/* Channel Direction (W/R*) */
+#define DMA2D_P			4		/* 2D/1D* Mode */
+#define RESTART_P		5		/* Restart */
+#define DI_SEL_P		6		/* Data Interrupt Select */
+#define DI_EN_P			7		/* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE		0x00000001	/* DMA Done Indicator */
+#define DMA_ERR			0x00000002	/* DMA Error Indicator */
+#define DFETCH			0x00000004	/* Descriptor Fetch Indicator */
+#define DMA_RUN			0x00000008	/* DMA Running Indicator */
+
+#define DMA_DONE_P		0		/* DMA Done Indicator */
+#define DMA_ERR_P		1		/* DMA Error Indicator */
+#define DFETCH_P		2		/* Descriptor Fetch Indicator */
+#define DMA_RUN_P		3		/* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE			0x00000040	/* DMA Channel Type Indicator */
+#define CTYPE_P			6		/* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8			0x00000080	/* DMA 8-bit Operation Indicator */
+#define PCAP16			0x00000100	/* DMA 16-bit Operation Indicator */
+#define PCAP32			0x00000200	/* DMA 32-bit Operation Indicator */
+#define PCAPWR			0x00000400	/* DMA Write Operation Indicator */
+#define PCAPRD			0x00000800	/* DMA Read Operation Indicator */
+#define PMAP			0x00007000	/* DMA Peripheral Map Field */
+
+/*
+ * GENERAL PURPOSE TIMER MASKS
+ */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0			0x0001
+#define TIMEN1			0x0002
+#define TIMEN2			0x0004
+
+#define TIMEN0_P		0x00
+#define TIMEN1_P		0x01
+#define TIMEN2_P		0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0			0x0001
+#define TIMDIS1			0x0002
+#define TIMDIS2			0x0004
+
+#define TIMDIS0_P		0x00
+#define TIMDIS1_P		0x01
+#define TIMDIS2_P		0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0			0x0001
+#define TIMIL1			0x0002
+#define TIMIL2			0x0004
+#define TOVL_ERR0		0x0010
+#define TOVL_ERR1		0x0020
+#define TOVL_ERR2		0x0040
+#define TRUN0			0x1000
+#define TRUN1			0x2000
+#define TRUN2			0x4000
+
+#define TIMIL0_P		0x00
+#define TIMIL1_P		0x01
+#define TIMIL2_P		0x02
+#define TOVL_ERR0_P		0x04
+#define TOVL_ERR1_P		0x05
+#define TOVL_ERR2_P		0x06
+#define TRUN0_P			0x0C
+#define TRUN1_P			0x0D
+#define TRUN2_P			0x0E
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT			0x0001
+#define WDTH_CAP		0x0002
+#define EXT_CLK			0x0003
+#define PULSE_HI		0x0004
+#define PERIOD_CNT		0x0008
+#define IRQ_ENA			0x0010
+#define TIN_SEL			0x0020
+#define OUT_DIS			0x0040
+#define CLK_SEL			0x0080
+#define TOGGLE_HI		0x0100
+#define EMU_RUN			0x0200
+#define ERR_TYP(x)		((x & 0x03) << 14)
+
+#define TMODE_P0		0x00
+#define TMODE_P1		0x01
+#define PULSE_HI_P		0x02
+#define PERIOD_CNT_P		0x03
+#define IRQ_ENA_P		0x04
+#define TIN_SEL_P		0x05
+#define OUT_DIS_P		0x06
+#define CLK_SEL_P		0x07
+#define TOGGLE_HI_P		0x08
+#define EMU_RUN_P		0x09
+#define ERR_TYP_P0		0x0E
+#define ERR_TYP_P1		0x0F
+
+/* 
+ * PROGRAMMABLE FLAG MASKS
+ */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
+#define PF0			0x0001
+#define PF1			0x0002
+#define PF2			0x0004
+#define PF3			0x0008
+#define PF4			0x0010
+#define PF5			0x0020
+#define PF6			0x0040
+#define PF7			0x0080
+#define PF8			0x0100
+#define PF9			0x0200
+#define PF10			0x0400
+#define PF11			0x0800
+#define PF12			0x1000
+#define PF13			0x2000
+#define PF14			0x4000
+#define PF15			0x8000
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
+#define PF0_P			0
+#define PF1_P			1
+#define PF2_P			2
+#define PF3_P			3
+#define PF4_P			4
+#define PF5_P			5
+#define PF6_P			6
+#define PF7_P			7
+#define PF8_P			8
+#define PF9_P			9
+#define PF10_P			10
+#define PF11_P			11
+#define PF12_P			12
+#define PF13_P			13
+#define PF14_P			14
+#define PF15_P			15
+
+/*
+ * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
+ */
+
+/* SPI_CTL Masks */
+#define TIMOD			0x00000003	/* Transfer initiation mode and interrupt generation */
+#define SZ			0x00000004	/* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM			0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE			0x00000010	/* Enable (=1) Slave-Select input for Master. */
+#define EMISO			0x00000020	/* Enable (=1) MISO pin as an output. */
+#define SIZE			0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF			0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA			0x00000400	/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL			0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR			0x00001000	/* Configures SPI as master (=1) or slave (=0) */
+#define WOM			0x00002000	/* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE			0x00004000	/* SPI module enable (=1), disable (=0) */
+
+/* SPI_FLG Masks */
+#define FLS1			0x00000002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2			0x00000004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3			0x00000008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4			0x00000010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5			0x00000020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6			0x00000040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7			0x00000080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1			0x00000200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2			0x00000400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3			0x00000800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4			0x00001000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5			0x00002000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6			0x00004000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7			0x00008000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P			0x00000001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P			0x00000002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P			0x00000003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P			0x00000004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P			0x00000005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P			0x00000006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P			0x00000007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P			0x00000009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P			0x0000000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P			0x0000000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P			0x0000000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P			0x0000000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P			0x0000000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P			0x0000000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF			0x00000001	/* Set (=1) when SPI single-word transfer complete */
+#define MODF			0x00000002	/* Set(=1)in a master device when some other device tries to become master */
+#define TXE			0x00000004	/* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS			0x00000008	/* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY			0x00000010	/* Set (=1) when data is received with RDBR full */
+#define RXS			0x00000020	/* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL			0x00000040	/* When set (=1), corrupt data may have been transmitted */
+
+/*
+ * ASYNCHRONOUS MEMORY CONTROLLER MASKS
+ */
+
+/* AMGCTL Masks */
+#define AMCKEN			0x00000001	/* Enable CLKOUT */
+#define AMBEN_B0		0x00000002	/* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1		0x00000004	/* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2		0x00000006	/* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL		0x00000008	/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P		0x00000000	/* Enable CLKOUT */
+#define AMBEN_P0		0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1		0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2		0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN			0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL		0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1			0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2			0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3			0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4			0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1			0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2			0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3			0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4			0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1			0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2			0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3			0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0			0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1			0x00000100	/* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2			0x00000200	/* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3			0x00000300	/* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4			0x00000400	/* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5			0x00000500	/* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6			0x00000600	/* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7			0x00000700	/* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8			0x00000800	/* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9			0x00000900	/* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10		0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11		0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12		0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13		0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14		0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15		0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1			0x00001000	/* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2			0x00002000	/* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3			0x00003000	/* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4			0x00004000	/* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5			0x00005000	/* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6			0x00006000	/* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7			0x00007000	/* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8			0x00008000	/* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9			0x00009000	/* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10		0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11		0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12		0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13		0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14		0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15		0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN			0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL		0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1			0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2			0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3			0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4			0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1			0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2			0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3			0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4			0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1			0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2			0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3			0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0			0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1			0x01000000	/* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2			0x02000000	/* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3			0x03000000	/* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4			0x04000000	/* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5			0x05000000	/* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6			0x06000000	/* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7			0x07000000	/* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8			0x08000000	/* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9			0x09000000	/* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10		0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11		0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12		0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13		0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14		0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15		0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1			0x10000000	/* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2			0x20000000	/* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3			0x30000000	/* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4			0x40000000	/* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5			0x50000000	/* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6			0x60000000	/* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7			0x70000000	/* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8			0x80000000	/* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9			0x90000000	/* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10		0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11		0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12		0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13		0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14		0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15		0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN			0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL		0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1			0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2			0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3			0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4			0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1			0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2			0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3			0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4			0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1			0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2			0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3			0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0			0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1			0x00000100	/* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2			0x00000200	/* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3			0x00000300	/* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4			0x00000400	/* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5			0x00000500	/* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6			0x00000600	/* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7			0x00000700	/* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8			0x00000800	/* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9			0x00000900	/* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10		0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11		0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12		0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13		0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14		0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15		0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1			0x00001000	/* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2			0x00002000	/* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3			0x00003000	/* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4			0x00004000	/* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5			0x00005000	/* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6			0x00006000	/* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7			0x00007000	/* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8			0x00008000	/* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9			0x00009000	/* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10		0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11		0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12		0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13		0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14		0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15		0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN			0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL		0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1			0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2			0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3			0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4			0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1			0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2			0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3			0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4			0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1			0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2			0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3			0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0			0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1			0x01000000	/* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2			0x02000000	/* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3			0x03000000	/* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4			0x04000000	/* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5			0x05000000	/* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6			0x06000000	/* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7			0x07000000	/* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8			0x08000000	/* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9			0x09000000	/* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10		0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11		0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12		0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13		0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14		0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15		0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1			0x10000000	/* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2			0x20000000	/* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3			0x30000000	/* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4			0x40000000	/* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5			0x50000000	/* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6			0x60000000	/* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7			0x70000000	/* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8			0x80000000	/* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9			0x90000000	/* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10		0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11		0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12		0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13		0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14		0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15		0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
+
+/*
+ * SDRAM CONTROLLER MASKS
+ */
+
+/* SDGCTL Masks */
+#define SCTLE			0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2			0x00000008	/* SDRAM CAS latency = 2 cycles */
+#define CL_3			0x0000000C	/* SDRAM CAS latency = 3 cycles */
+#define PFE			0x00000010	/* Enable SDRAM prefetch */
+#define PFP			0x00000020	/* Prefetch has priority over AMC requests */
+#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle */
+#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles */
+#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles */
+#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles */
+#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles */
+#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles */
+#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles */
+#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles */
+#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles */
+#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles */
+#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles */
+#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles */
+#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles */
+#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles */
+#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles */
+#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle */
+#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles */
+#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles */
+#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles */
+#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles */
+#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles */
+#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles */
+#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle */
+#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles */
+#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles */
+#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles */
+#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles */
+#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles */
+#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles */
+#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle */
+#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles */
+#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles */
+#define PUPSD			0x00200000	/* Power-up start delay */
+#define PSM			0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS			0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS			0x01000000	/* Start SDRAM self-refresh mode */
+#define EBUFE			0x02000000	/* Enable external buffering timing */
+#define FBBRW			0x04000000	/* Fast back-to-back read write enable */
+#define EMREN			0x10000000	/* Extended mode register enable */
+#define TCSR			0x20000000	/* Temp compensated self refresh value 85 deg C */
+#define CDDBG			0x40000000	/* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE			0x00000001	/* Enable SDRAM external bank */
+#define EBSZ_16			0x00000000	/* SDRAM external bank size = 16MB */
+#define EBSZ_32			0x00000002	/* SDRAM external bank size = 32MB */
+#define EBSZ_64			0x00000004	/* SDRAM external bank size = 64MB */
+#define EBSZ_128		0x00000006	/* SDRAM external bank size = 128MB */
+#define EBCAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9			0x00000010	/* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10		0x00000020	/* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11		0x00000030	/* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI			0x00000001	/* SDRAM controller is idle */
+#define SDSRA			0x00000002	/* SDRAM SDRAM self refresh is active */
+#define SDPUA			0x00000004	/* SDRAM power up active */
+#define SDRS			0x00000008	/* SDRAM is in reset state */
+#define SDEASE			0x00000010	/* SDRAM EAB sticky error status - W1C */
+#define BGSTAT			0x00000020	/* Bus granted */
+
+#endif /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h
new file mode 100644
index 0000000..90e50af
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF533.h
@@ -0,0 +1,24 @@
+/*
+ * defBF533.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEFBF533_H
+#define _DEFBF533_H
+
+#include <asm/cpu/defBF532.h>
+
+#endif /* _DEFBF533_H */
diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h
new file mode 100644
index 0000000..a9a1c7c
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF533_extn.h
@@ -0,0 +1,76 @@
+/*
+ * defBF533_extn.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEF_BF533_EXTN_H
+#define _DEF_BF533_EXTN_H
+
+#define OFFSET_( x )		((x) & 0x0000FFFF) /* define macro for offset */
+/* Delay inserted for PLL transition */
+#define DELAY			0x1000
+
+#define L1_ISRAM		0xFFA00000
+#define L1_ISRAM_END		0xFFA10000
+#define DATA_BANKA_SRAM		0xFF800000
+#define DATA_BANKA_SRAM_END	0xFF808000
+#define DATA_BANKB_SRAM		0xFF900000
+#define DATA_BANKB_SRAM_END	0xFF908000
+#define SYSMMR_BASE		0xFFC00000
+#define WDSIZE16		0x00000004
+
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR	0xffe02000
+#define EVT_RESET_ADDR		0xffe02004
+#define EVT_NMI_ADDR		0xffe02008
+#define EVT_EXCEPTION_ADDR	0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR	0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR	0xffe02014
+#define EVT_TIMER_ADDR		0xffe02018
+#define EVT_IVG7_ADDR		0xffe0201c
+#define EVT_IVG8_ADDR		0xffe02020
+#define EVT_IVG9_ADDR		0xffe02024
+#define EVT_IVG10_ADDR		0xffe02028
+#define EVT_IVG11_ADDR		0xffe0202c
+#define EVT_IVG12_ADDR		0xffe02030
+#define EVT_IVG13_ADDR		0xffe02034
+#define EVT_IVG14_ADDR		0xffe02038
+#define EVT_IVG15_ADDR		0xffe0203c
+#define EVT_OVERRIDE_ADDR	0xffe02100
+
+/* IMASK Bit values */
+#define IVG15_POS		0x00008000
+#define IVG14_POS		0x00004000
+#define IVG13_POS		0x00002000
+#define IVG12_POS		0x00001000
+#define IVG11_POS		0x00000800
+#define IVG10_POS		0x00000400
+#define IVG9_POS		0x00000200
+#define IVG8_POS		0x00000100
+#define IVG7_POS		0x00000080
+#define IVGTMR_POS		0x00000040
+#define IVGHW_POS		0x00000020
+
+#define WDOG_TMR_DISABLE	(0xAD << 4)
+#define ICTL_RST		0x00000000
+#define ICTL_NMI		0x00000002
+#define ICTL_GP			0x00000004
+#define ICTL_DISABLE		0x00000003
+
+/* Watch Dog timer values setup */
+#define WATCHDOG_DISABLE	WDOG_TMR_DISABLE | ICTL_DISABLE
+
+#endif	/* _DEF_BF533_EXTN_H */
diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h
new file mode 100644
index 0000000..11a6504
--- /dev/null
+++ b/include/asm-blackfin/cpu/def_LPBlackfin.h
@@ -0,0 +1,445 @@
+/*
+ * def_LPBlackfin.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_LPBLACKFIN_H
+#define _DEF_LPBLACKFIN_H
+
+/* 
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
+ * #endif
+ */
+
+#define MK_BMSK_( x ) (1<<x)	/* Make a bit mask from a bit position */
+
+/*
+ * System Register Bits
+ */
+
+/*
+ * ASTAT register
+ */
+
+/* definitions of ASTAT bit positions */
+#define ASTAT_AZ_P		0x00000000	/* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN_P		0x00000001	/* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_CC_P		0x00000005	/* Condition Code, used for holding comparison results */
+#define ASTAT_AQ_P		0x00000006	/* Quotient Bit */
+#define ASTAT_RND_MOD_P		0x00000008	/* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_AC0_P		0x0000000C	/* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY_P	0x00000002	/* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1_P		0x0000000D	/* Result of last ALU1 operation generated a carry */
+#define ASTAT_AV0_P		0x00000010	/* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV0S_P		0x00000011	/* Sticky version of ASTAT_AV0  */
+#define ASTAT_AV1_P		0x00000012	/* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_AV1S_P		0x00000013	/* Sticky version of ASTAT_AV1  */
+#define ASTAT_V_P		0x00000018	/* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_V_COPY_P		0x00000003	/* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_VS_P		0x00000019	/* Sticky version of ASTAT_V */
+
+/* ** Masks */
+#define ASTAT_AZ		MK_BMSK_(ASTAT_AZ_P)	/* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN		MK_BMSK_(ASTAT_AN_P)	/* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_AC0		MK_BMSK_(ASTAT_AC0_P)	/* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY		MK_BMSK_(ASTAT_AC0_COPY_P)	/* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1		MK_BMSK_(ASTAT_AC1_P)	/* Result of last ALU0 operation generated a carry */
+#define ASTAT_AV0		MK_BMSK_(ASTAT_AV0_P)	/* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV1		MK_BMSK_(ASTAT_AV1_P)	/* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_CC		MK_BMSK_(ASTAT_CC_P)	/* Condition Code, used for holding comparison results */
+#define ASTAT_AQ		MK_BMSK_(ASTAT_AQ_P)	/* Quotient Bit */
+#define ASTAT_RND_MOD		MK_BMSK_(ASTAT_RND_MOD_P)	/* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_V			MK_BMSK_(ASTAT_V_P)	/* Overflow Bit */
+#define ASTAT_V_COPY		MK_BMSK_(ASTAT_V_COPY_P)	/* Overflow Bit */
+
+/*
+ * SEQSTAT register
+ */
+
+/* ** Bit Positions */
+#define SEQSTAT_EXCAUSE0_P	0x00000000	/* Last exception cause bit 0 */
+#define SEQSTAT_EXCAUSE1_P	0x00000001	/* Last exception cause bit 1 */
+#define SEQSTAT_EXCAUSE2_P	0x00000002	/* Last exception cause bit 2 */
+#define SEQSTAT_EXCAUSE3_P	0x00000003	/* Last exception cause bit 3 */
+#define SEQSTAT_EXCAUSE4_P	0x00000004	/* Last exception cause bit 4 */
+#define SEQSTAT_EXCAUSE5_P	0x00000005	/* Last exception cause bit 5 */
+#define SEQSTAT_IDLE_REQ_P	0x0000000C	/* Pending idle mode request, set by IDLE instruction */
+#define SEQSTAT_SFTRESET_P	0x0000000D	/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_HWERRCAUSE0_P	0x0000000E	/* Last hw error cause bit 0 */
+#define SEQSTAT_HWERRCAUSE1_P	0x0000000F	/* Last hw error cause bit 1 */
+#define SEQSTAT_HWERRCAUSE2_P	0x00000010	/* Last hw error cause bit 2 */
+#define SEQSTAT_HWERRCAUSE3_P	0x00000011	/* Last hw error cause bit 3 */
+#define SEQSTAT_HWERRCAUSE4_P	0x00000012	/* Last hw error cause bit 4 */
+#define SEQSTAT_HWERRCAUSE5_P	0x00000013	/* Last hw error cause bit 5 */
+#define SEQSTAT_HWERRCAUSE6_P	0x00000014	/* Last hw error cause bit 6 */
+#define SEQSTAT_HWERRCAUSE7_P	0x00000015	/* Last hw error cause bit 7 */
+
+/* ** Masks */
+/* Exception cause */
+#define SEQSTAT_EXCAUSE		MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
+				MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
+				MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
+				MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
+				MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
+				MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
+				0
+
+/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_SFTRESET	MK_BMSK_(SEQSTAT_SFTRESET_P )
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE	MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
+				MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
+				MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
+				MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
+				MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \
+				0
+
+/*
+ * SYSCFG register
+ */
+
+/* ** Bit Positions */
+#define SYSCFG_SSSTEP_P		0x00000000	/* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN_P		0x00000001	/* Enable cycle counter (=1) */
+#define SYSCFG_SNEN_P		0x00000002	/* Self nesting Interrupt Enable */
+
+/* ** Masks */
+#define SYSCFG_SSSTEP		MK_BMSK_(SYSCFG_SSSTEP_P)	/* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN		MK_BMSK_(SYSCFG_CCEN_P)		/* Enable cycle counter (=1) */
+#define SYSCFG_SNEN		MK_BMSK_(SYSCFG_SNEN_P		/* Self Nesting Interrupt Enable */
+
+/* Backward-compatibility for typos in prior releases */
+#define SYSCFG_SSSSTEP		SYSCFG_SSSTEP
+#define SYSCFG_CCCEN		SYSCFG_CCEN
+
+/*
+ * Core MMR Register Map
+ */
+
+/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
+#define SRAM_BASE_ADDRESS	0xFFE00000	/* SRAM Base Address Register */
+#define DMEM_CONTROL		0xFFE00004	/* Data memory control */
+#define DCPLB_STATUS		0xFFE00008	/* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_STATUS	0xFFE00008	/* "" (older define) */
+#define DCPLB_FAULT_ADDR	0xFFE0000C	/* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0		0xFFE00100	/* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1		0xFFE00104	/* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2		0xFFE00108	/* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3		0xFFE0010C	/* Data Cacheability Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4		0xFFE00110	/* Data Cacheability Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5		0xFFE00114	/* Data Cacheability Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6		0xFFE00118	/* Data Cacheability Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7		0xFFE0011C	/* Data Cacheability Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8		0xFFE00120	/* Data Cacheability Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9		0xFFE00124	/* Data Cacheability Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10		0xFFE00128	/* Data Cacheability Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11		0xFFE0012C	/* Data Cacheability Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12		0xFFE00130	/* Data Cacheability Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13		0xFFE00134	/* Data Cacheability Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14		0xFFE00138	/* Data Cacheability Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15		0xFFE0013C	/* Data Cacheability Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0		0xFFE00200	/* Data Cache 0 Status */
+#define DCPLB_DATA1		0xFFE00204	/* Data Cache 1 Status */
+#define DCPLB_DATA2		0xFFE00208	/* Data Cache 2 Status */
+#define DCPLB_DATA3		0xFFE0020C	/* Data Cache 3 Status */
+#define DCPLB_DATA4		0xFFE00210	/* Data Cache 4 Status */
+#define DCPLB_DATA5		0xFFE00214	/* Data Cache 5 Status */
+#define DCPLB_DATA6		0xFFE00218	/* Data Cache 6 Status */
+#define DCPLB_DATA7		0xFFE0021C	/* Data Cache 7 Status */
+#define DCPLB_DATA8		0xFFE00220	/* Data Cache 8 Status */
+#define DCPLB_DATA9		0xFFE00224	/* Data Cache 9 Status */
+#define DCPLB_DATA10		0xFFE00228	/* Data Cache 10 Status */
+#define DCPLB_DATA11		0xFFE0022C	/* Data Cache 11 Status */
+#define DCPLB_DATA12		0xFFE00230	/* Data Cache 12 Status */
+#define DCPLB_DATA13		0xFFE00234	/* Data Cache 13 Status */
+#define DCPLB_DATA14		0xFFE00238	/* Data Cache 14 Status */
+#define DCPLB_DATA15		0xFFE0023C	/* Data Cache 15 Status */
+#define DTEST_COMMAND		0xFFE00300	/* Data Test Command Register */
+#define DTEST_DATA0		0xFFE00400	/* Data Test Data Register */
+#define DTEST_DATA1		0xFFE00404	/* Data Test Data Register */
+
+/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
+#define IMEM_CONTROL		0xFFE01004	/* Instruction Memory Control */
+#define ICPLB_STATUS		0xFFE01008	/* Instruction Cache miss status */
+#define CODE_FAULT_STATUS	0xFFE01008	/* "" (older define) */
+#define ICPLB_FAULT_ADDR	0xFFE0100C	/* Instruction Cache miss address */
+#define CODE_FAULT_ADDR		0xFFE0100C	/* "" (older define) */
+#define ICPLB_ADDR0		0xFFE01100	/* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1		0xFFE01104	/* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2		0xFFE01108	/* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3		0xFFE0110C	/* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4		0xFFE01110	/* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5		0xFFE01114	/* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6		0xFFE01118	/* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7		0xFFE0111C	/* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8		0xFFE01120	/* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9		0xFFE01124	/* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10		0xFFE01128	/* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11		0xFFE0112C	/* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12		0xFFE01130	/* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13		0xFFE01134	/* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14		0xFFE01138	/* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15		0xFFE0113C	/* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0		0xFFE01200	/* Instruction Cache 0 Status */
+#define ICPLB_DATA1		0xFFE01204	/* Instruction Cache 1 Status */
+#define ICPLB_DATA2		0xFFE01208	/* Instruction Cache 2 Status */
+#define ICPLB_DATA3		0xFFE0120C	/* Instruction Cache 3 Status */
+#define ICPLB_DATA4		0xFFE01210	/* Instruction Cache 4 Status */
+#define ICPLB_DATA5		0xFFE01214	/* Instruction Cache 5 Status */
+#define ICPLB_DATA6		0xFFE01218	/* Instruction Cache 6 Status */
+#define ICPLB_DATA7		0xFFE0121C	/* Instruction Cache 7 Status */
+#define ICPLB_DATA8		0xFFE01220	/* Instruction Cache 8 Status */
+#define ICPLB_DATA9		0xFFE01224	/* Instruction Cache 9 Status */
+#define ICPLB_DATA10		0xFFE01228	/* Instruction Cache 10 Status */
+#define ICPLB_DATA11		0xFFE0122C	/* Instruction Cache 11 Status */
+#define ICPLB_DATA12		0xFFE01230	/* Instruction Cache 12 Status */
+#define ICPLB_DATA13		0xFFE01234	/* Instruction Cache 13 Status */
+#define ICPLB_DATA14		0xFFE01238	/* Instruction Cache 14 Status */
+#define ICPLB_DATA15		0xFFE0123C	/* Instruction Cache 15 Status */
+#define ITEST_COMMAND		0xFFE01300	/* Instruction Test Command Register */
+#define ITEST_DATA0		0xFFE01400	/* Instruction Test Data Register */
+#define ITEST_DATA1		0xFFE01404	/* Instruction Test Data Register */
+
+/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
+#define EVT0			0xFFE02000	/* Event Vector 0 ESR Address */
+#define EVT1			0xFFE02004	/* Event Vector 1 ESR Address */
+#define EVT2			0xFFE02008	/* Event Vector 2 ESR Address */
+#define EVT3			0xFFE0200C	/* Event Vector 3 ESR Address */
+#define EVT4			0xFFE02010	/* Event Vector 4 ESR Address */
+#define EVT5			0xFFE02014	/* Event Vector 5 ESR Address */
+#define EVT6			0xFFE02018	/* Event Vector 6 ESR Address */
+#define EVT7			0xFFE0201C	/* Event Vector 7 ESR Address */
+#define EVT8			0xFFE02020	/* Event Vector 8 ESR Address */
+#define EVT9			0xFFE02024	/* Event Vector 9 ESR Address */
+#define EVT10			0xFFE02028	/* Event Vector 10 ESR Address */
+#define EVT11			0xFFE0202C	/* Event Vector 11 ESR Address */
+#define EVT12			0xFFE02030	/* Event Vector 12 ESR Address */
+#define EVT13			0xFFE02034	/* Event Vector 13 ESR Address */
+#define EVT14			0xFFE02038	/* Event Vector 14 ESR Address */
+#define EVT15			0xFFE0203C	/* Event Vector 15 ESR Address */
+#define IMASK			0xFFE02104	/* Interrupt Mask Register */
+#define IPEND			0xFFE02108	/* Interrupt Pending Register */
+#define ILAT			0xFFE0210C	/* Interrupt Latch Register */
+#define IPRIO			0xFFE02110	/* Core Interrupt Priority Register */
+
+/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
+#define TCNTL			0xFFE03000	/* Core Timer Control Register */
+#define TPERIOD			0xFFE03004	/* Core Timer Period Register */
+#define TSCALE			0xFFE03008	/* Core Timer Scale Register */
+#define TCOUNT			0xFFE0300C	/* Core Timer Count Register */
+
+/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
+#define DSPID			0xFFE05000	/* DSP Processor ID Register for MP implementations */
+#define DBGSTAT			0xFFE05008	/* Debug Status Register */
+
+/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
+#define TBUFCTL			0xFFE06000	/* Trace Buffer Control Register */
+#define TBUFSTAT		0xFFE06004	/* Trace Buffer Status Register */
+#define TBUF			0xFFE06100	/* Trace Buffer */
+
+/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
+#define WPIACTL			0xFFE07000	/* Watchpoint Instruction Address Control Register */
+#define WPIA0			0xFFE07040	/* Watchpoint Instruction Address Register 0 */
+#define WPIA1			0xFFE07044	/* Watchpoint Instruction Address Register 1 */
+#define WPIA2			0xFFE07048	/* Watchpoint Instruction Address Register 2 */
+#define WPIA3			0xFFE0704C	/* Watchpoint Instruction Address Register 3 */
+#define WPIA4			0xFFE07050	/* Watchpoint Instruction Address Register 4 */
+#define WPIA5			0xFFE07054	/* Watchpoint Instruction Address Register 5 */
+#define WPIACNT0		0xFFE07080	/* Watchpoint Instruction Address Count Register 0 */
+#define WPIACNT1		0xFFE07084	/* Watchpoint Instruction Address Count Register 1 */
+#define WPIACNT2		0xFFE07088	/* Watchpoint Instruction Address Count Register 2 */
+#define WPIACNT3		0xFFE0708C	/* Watchpoint Instruction Address Count Register 3 */
+#define WPIACNT4		0xFFE07090	/* Watchpoint Instruction Address Count Register 4 */
+#define WPIACNT5		0xFFE07094	/* Watchpoint Instruction Address Count Register 5 */
+#define WPDACTL			0xFFE07100	/* Watchpoint Data Address Control Register */
+#define WPDA0			0xFFE07140	/* Watchpoint Data Address Register 0 */
+#define WPDA1			0xFFE07144	/* Watchpoint Data Address Register 1 */
+#define WPDACNT0		0xFFE07180	/* Watchpoint Data Address Count Value Register 0 */
+#define WPDACNT1		0xFFE07184	/* Watchpoint Data Address Count Value Register 1 */
+#define WPSTAT			0xFFE07200	/* Watchpoint Status Register */
+
+/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
+#define PFCTL			0xFFE08000	/* Performance Monitor Control Register */
+#define PFCNTR0			0xFFE08100	/* Performance Monitor Counter Register 0 */
+#define PFCNTR1			0xFFE08104	/* Performance Monitor Counter Register 1 */
+
+/*
+ * Core MMR Register Bits
+ */
+
+/*
+ * EVT registers (ILAT, IMASK, and IPEND).
+ */
+
+/* ** Bit Positions */
+#define EVT_EMU_P		0x00000000	/* Emulator interrupt bit position */
+#define EVT_RST_P		0x00000001	/* Reset interrupt bit position */
+#define EVT_NMI_P		0x00000002	/* Non Maskable interrupt bit position */
+#define EVT_EVX_P		0x00000003	/* Exception bit position */
+#define EVT_IRPTEN_P		0x00000004	/* Global interrupt enable bit position */
+#define EVT_IVHW_P		0x00000005	/* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P		0x00000006	/* Timer interrupt bit position */
+#define EVT_IVG7_P		0x00000007	/* IVG7 interrupt bit position */
+#define EVT_IVG8_P		0x00000008	/* IVG8 interrupt bit position */
+#define EVT_IVG9_P		0x00000009	/* IVG9 interrupt bit position */
+#define EVT_IVG10_P		0x0000000a	/* IVG10 interrupt bit position */
+#define EVT_IVG11_P		0x0000000b	/* IVG11 interrupt bit position */
+#define EVT_IVG12_P		0x0000000c	/* IVG12 interrupt bit position */
+#define EVT_IVG13_P		0x0000000d	/* IVG13 interrupt bit position */
+#define EVT_IVG14_P		0x0000000e	/* IVG14 interrupt bit position */
+#define EVT_IVG15_P		0x0000000f	/* IVG15 interrupt bit position */
+
+/* ** Masks */
+#define EVT_EMU			MK_BMSK_(EVT_EMU_P   )	/* Emulator interrupt mask */
+#define EVT_RST			MK_BMSK_(EVT_RST_P   )	/* Reset interrupt mask */
+#define EVT_NMI			MK_BMSK_(EVT_NMI_P   )	/* Non Maskable interrupt mask */
+#define EVT_EVX			MK_BMSK_(EVT_EVX_P   )	/* Exception mask */
+#define EVT_IRPTEN		MK_BMSK_(EVT_IRPTEN_P)	/* Global interrupt enable mask */
+#define EVT_IVHW		MK_BMSK_(EVT_IVHW_P  )	/* Hardware Error interrupt mask */
+#define EVT_IVTMR		MK_BMSK_(EVT_IVTMR_P )	/* Timer interrupt mask */
+#define EVT_IVG7		MK_BMSK_(EVT_IVG7_P  )	/* IVG7 interrupt mask */
+#define EVT_IVG8		MK_BMSK_(EVT_IVG8_P  )	/* IVG8 interrupt mask */
+#define EVT_IVG9		MK_BMSK_(EVT_IVG9_P  )	/* IVG9 interrupt mask */
+#define EVT_IVG10		MK_BMSK_(EVT_IVG10_P )	/* IVG10 interrupt mask */
+#define EVT_IVG11		MK_BMSK_(EVT_IVG11_P )	/* IVG11 interrupt mask */
+#define EVT_IVG12		MK_BMSK_(EVT_IVG12_P )	/* IVG12 interrupt mask */
+#define EVT_IVG13		MK_BMSK_(EVT_IVG13_P )	/* IVG13 interrupt mask */
+#define EVT_IVG14		MK_BMSK_(EVT_IVG14_P )	/* IVG14 interrupt mask */
+#define EVT_IVG15		MK_BMSK_(EVT_IVG15_P )	/* IVG15 interrupt mask */
+
+/*
+ * DMEM_CONTROL Register
+ */
+
+/* ** Bit Positions */
+#define ENDM_P			0x00	/* (doesn't really exist) Enable Data Memory L1 */
+#define DMCTL_ENDM_P		0x00	/* "" (older define) */
+#define DMC0_P			0x01	/* Data Memory Configuration, 00 - A SRAM, B SRAM */
+#define DMCTL_DMC0_P		0x01	/* "" (older define) */
+#define DMC1_P			0x02	/* Data Memory Configuration, 10 - A SRAM, B SRAM */
+#define DMCTL_DMC1_P		0x02	/* "" (older define) */
+#define DMC2_P			0x03	/* Data Memory Configuration, 11 - A CACHE, B CACHE */
+#define DMCTL_DMC2_P		0x03	/* "" (older define) */
+#define DCBS_P			0x04	/* L1 Data Cache Bank Select */
+#define PORT_PREF0_P		0x12	/* DAG0 Port Preference */
+#define PORT_PREF1_P		0x13	/* DAG1 Port Preference */
+
+/* ** Masks */
+#define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
+#define ENDCPLB			0x00000002	/* Enable DCPLB */
+#define ASRAM_BSRAM		0x00000000	
+#define ACACHE_BSRAM		0x00000008
+#define ACACHE_BCACHE		0x0000000C  
+#define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
+#define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
+#define PORT_PREF1		0x00002000	/* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* ** Bit Positions */
+#define ENIM_P			0x00	/* Enable L1 Code Memory */
+#define IMCTL_ENIM_P		0x00	/* "" (older define) */
+#define ENICPLB_P		0x01	/* Enable ICPLB */
+#define IMCTL_ENICPLB_P		0x01	/* "" (older define) */
+#define IMC_P			0x02	/* Enable */
+#define IMCTL_IMC_P		0x02	/* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0_P			0x03	/* Lock Way 0 */
+#define ILOC1_P			0x04	/* Lock Way 1 */
+#define ILOC2_P			0x05	/* Lock Way 2 */
+#define ILOC3_P			0x06	/* Lock Way 3 */
+#define LRUPRIORST_P		0x0D	/* Least Recently Used Replacement Priority */
+
+/* ** Masks */
+#define ENIM			0x00000001	/* Enable L1 Code Memory */
+#define ENICPLB			0x00000002	/* Enable ICPLB */
+#define IMC			0x00000004	/* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0			0x00000008	/* Lock Way 0 */
+#define ILOC1			0x00000010	/* Lock Way 1 */
+#define ILOC2			0x00000020	/* Lock Way 2 */
+#define ILOC3			0x00000040	/* Lock Way 3 */
+#define LRUPRIORST		0x00002000	/* Least Recently Used Replacement Priority */
+
+/* TCNTL Masks */
+#define TMPWR			0x00000001	/* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN			0x00000002	/* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD		0x00000004	/* Timer auto reload */
+#define TINT			0x00000008	/* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* TCNTL Bit Positions */
+#define TMPWR_P			0x00000000	/* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN_P			0x00000001	/* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD_P		0x00000002	/* Timer auto reload */
+#define TINT_P			0x00000003	/* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/* ** Bit Positions */
+#define CPLB_VALID_P		0x00000000	/* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P		0x00000001	/* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P		0x00000002	/* 0=no read access, 1=read access allowed (user mode) */
+
+/* ** Masks */
+#define CPLB_VALID		0x00000001	/* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK		0x00000002	/* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD		0x00000004	/* 0=no read access, 1=read access allowed (user mode) */
+#define PAGE_SIZE_1KB		0x00000000	/* 1 KB page size */
+#define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
+#define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
+#define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
+#define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
+#define CPLB_L1_CHBL		0x00001000	/* 0=non-cacheable in L1, 1=cacheable in L1 */
+
+/* ICPLB_DATA only */
+#define CPLB_LRUPRIO		0x00000100	/* 0=can be replaced by any line, 1=priority for non-replacement */
+
+/* DCPLB_DATA only */
+#define CPLB_USER_WR		0x00000008	/* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR		0x00000010	/* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY		0x00000080	/* 1=dirty, 0=clean */
+#define CPLB_L1_AOW		0x00008000	/* 0=do not allocate cache lines on write-through writes */
+						/* 1= allocate cache lines on write-through writes. */
+#define CPLB_WT			0x00004000	/* 0=write-back, 1=write-through */
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/* ** Masks */
+#define TEST_READ		0x00000000	/* Read Access */
+#define TEST_WRITE		0x00000002	/* Write Access */
+#define TEST_TAG		0x00000000	/* Access TAG */
+#define TEST_DATA		0x00000004	/* Access DATA */
+#define TEST_DW0		0x00000000	/* Select Double Word 0 */
+#define TEST_DW1		0x00000008	/* Select Double Word 1 */
+#define TEST_DW2		0x00000010	/* Select Double Word 2 */
+#define TEST_DW3		0x00000018	/* Select Double Word 3 */
+#define TEST_MB0		0x00000000	/* Select Mini-Bank 0 */
+#define TEST_MB1		0x00010000	/* Select Mini-Bank 1 */
+#define TEST_MB2		0x00020000	/* Select Mini-Bank 2 */
+#define TEST_MB3		0x00030000	/* Select Mini-Bank 3 */
+#define TEST_SET(x)		((x << 5) & 0x03E0)	/* Set Index 0->31 */
+#define TEST_WAY0		0x00000000	/* Access Way0 */
+#define TEST_WAY1		0x04000000	/* Access Way1 */
+
+/* ** ITEST_COMMAND only */
+#define TEST_WAY2		0x08000000	/* Access Way2 */
+#define TEST_WAY3		0x0C000000	/* Access Way3 */
+
+/* ** DTEST_COMMAND only */
+#define TEST_BNKSELA		0x00000000	/* Access SuperBank A */
+#define TEST_BNKSELB		0x00800000	/* Access SuperBank B */
+
+#endif	/* _DEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
new file mode 100644
index 0000000..108c279
--- /dev/null
+++ b/include/asm-blackfin/current.h
@@ -0,0 +1,40 @@
+/*
+ * U-boot - current.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_CURRENT_H
+#define _BLACKFIN_CURRENT_H
+/*
+ *	current.h
+ *	(C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
+ *
+ *	rather than dedicate a register (as the m68k source does), we
+ *	just keep a global,  we should probably just change it all to be
+ *	current and lose _current_task.
+ */
+
+extern struct task_struct *_current_task;
+#define get_current()	_current_task
+#define current 	_current_task
+
+#endif
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
new file mode 100644
index 0000000..dbb7388
--- /dev/null
+++ b/include/asm-blackfin/delay.h
@@ -0,0 +1,55 @@
+/*
+ * U-boot - delay.h Routines for introducing delays
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_DELAY_H
+#define _BLACKFIN_DELAY_H
+
+/*
+ * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
+ * Copyright (C) 1994 Hamish Macdonald
+ *
+ * Delay routines, using a pre-computed "loops_per_second" value.
+ */
+
+extern __inline__ void __delay(unsigned long loops)
+{
+	__asm__ __volatile__("1:\t%0 += -1;\n\t"
+				"cc = %0 == 0;\n\t"
+				"if ! cc jump 1b;\n":"=d"(loops)
+				:"0"(loops));
+}
+
+/*
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+extern __inline__ void udelay(unsigned long usecs)
+{
+	__delay(usecs);
+}
+
+#endif
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
new file mode 100644
index 0000000..607a5b8
--- /dev/null
+++ b/include/asm-blackfin/entry.h
@@ -0,0 +1,385 @@
+/*
+ * U-boot - entry.h Routines for context saving and restoring
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_ENTRY_H
+#define __BLACKFIN_ENTRY_H
+
+#include <linux/config.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ */
+
+/*
+ * Register %p2 is now set to the current task throughout
+ * the whole kernel.
+ */
+
+#ifdef __ASSEMBLY__
+
+#define	LFLUSH_I_AND_D	0x00000808
+#define	LSIGTRAP	5
+
+/* process bits for task_struct.flags */
+#define	PF_TRACESYS_OFF	3
+#define	PF_TRACESYS_BIT	5
+#define	PF_PTRACED_OFF	3
+#define	PF_PTRACED_BIT	4
+#define	PF_DTRACE_OFF	1
+#define	PF_DTRACE_BIT	5
+
+#define NEW_PT_REGS
+
+#if defined(NEW_PT_REGS)
+
+#define SAVE_ALL_INT		save_context_no_interrupts
+#define SAVE_ALL_SYS		save_context_no_interrupts
+#define SAVE_CONTEXT		save_context_with_interrupts
+
+#define RESTORE_ALL		restore_context_no_interrupts
+#define RESTORE_ALL_SYS		restore_context_no_interrupts
+#define RESTORE_CONTEXT		restore_context_with_interrupts
+
+#else
+
+#define SAVE_ALL_INT		save_all_int
+#define SAVE_ALL_SYS		save_all_sys
+#define SAVE_CONTEXT		save_context
+#define RESTORE_ALL		restore_context
+#define RESTORE_CONTEXT		restore_context
+
+#endif
+
+/*
+ * Code to save processor context.
+ * We even save the register which are preserved by a function call
+ * - r4, r5, r6, r7, p3, p4, p5
+ */
+.macro save_context_with_interrupts
+	[--sp] = R0;
+	[--sp] = ( R7:0, P5:0 );
+	[--sp] = fp;
+	[--sp] = usp;
+
+	[--sp] = i0;
+	[--sp] = i1;
+	[--sp] = i2;
+	[--sp] = i3;
+
+	[--sp] = m0;
+	[--sp] = m1;
+	[--sp] = m2;
+	[--sp] = m3;
+
+	[--sp] = l0;
+	[--sp] = l1;
+	[--sp] = l2;
+	[--sp] = l3;
+
+	[--sp] = b0;
+	[--sp] = b1;
+	[--sp] = b2;
+	[--sp] = b3;
+	[--sp] = a0.x;
+	[--sp] = a0.w;
+	[--sp] = a1.x;
+	[--sp] = a1.w;
+
+	[--sp] = LC0;
+	[--sp] = LC1;
+	[--sp] = LT0;
+	[--sp] = LT1;
+	[--sp] = LB0;
+	[--sp] = LB1;
+
+	[--sp] = ASTAT;
+
+	[--sp] = r0;	/* Skip reserved */
+	[--sp] = RETS;
+	[--sp] = RETI;
+	[--sp] = RETX;
+	[--sp] = RETN;
+	[--sp] = RETE;
+	[--sp] = SEQSTAT;
+	[--sp] = SYSCFG;
+	[--sp] = r0;	/* Skip IPEND as well. */
+.endm
+
+.macro save_context_no_interrupts
+	[--sp] = R0;
+	[--sp] = ( R7:0, P5:0 );
+	[--sp] = fp;
+	[--sp] = usp;
+
+	[--sp] = i0;
+	[--sp] = i1;
+	[--sp] = i2;
+	[--sp] = i3;
+
+	[--sp] = m0;
+	[--sp] = m1;
+	[--sp] = m2;
+	[--sp] = m3;
+
+	[--sp] = l0;
+	[--sp] = l1;
+	[--sp] = l2;
+	[--sp] = l3;
+
+	[--sp] = b0;
+	[--sp] = b1;
+	[--sp] = b2;
+	[--sp] = b3;
+	[--sp] = a0.x;
+	[--sp] = a0.w;
+	[--sp] = a1.x;
+	[--sp] = a1.w;
+
+	[--sp] = LC0;
+	[--sp] = LC1;
+	[--sp] = LT0;
+	[--sp] = LT1;
+	[--sp] = LB0;
+	[--sp] = LB1;
+
+	[--sp] = ASTAT;
+
+	[--sp] = r0;	/* Skip reserved */
+	[--sp] = RETS;
+	r0 = RETI;
+	[--sp] = r0;
+	[--sp] = RETX;
+	[--sp] = RETN;
+	[--sp] = RETE;
+	[--sp] = SEQSTAT;
+	[--sp] = SYSCFG;
+	[--sp] = r0;	/* Skip IPEND as well. */
+.endm
+
+.macro restore_context_no_interrupts
+	sp += 4;
+	SYSCFG = [sp++];
+	SEQSTAT = [sp++];
+	RETE = [sp++];
+	RETN = [sp++];
+	RETX = [sp++];
+	r0 = [sp++];
+	RETI = r0;
+	RETS = [sp++];
+
+	sp += 4;
+
+	ASTAT = [sp++];
+
+	LB1 = [sp++];
+	LB0 = [sp++];
+	LT1 = [sp++];
+	LT0 = [sp++];
+	LC1 = [sp++];
+	LC0 = [sp++];
+
+	a1.w = [sp++];
+	a1.x = [sp++];
+	a0.w = [sp++];
+	a0.x = [sp++];
+	b3 = [sp++];
+	b2 = [sp++];
+	b1 = [sp++];
+	b0 = [sp++];
+
+	l3 = [sp++];
+	l2 = [sp++];
+	l1 = [sp++];
+	l0 = [sp++];
+
+	m3 = [sp++];
+	m2 = [sp++];
+	m1 = [sp++];
+	m0 = [sp++];
+
+	i3 = [sp++];
+	i2 = [sp++];
+	i1 = [sp++];
+	i0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+
+	( R7 : 0, P5 : 0) = [ SP ++ ];
+	sp += 4;
+.endm
+
+.macro restore_context_with_interrupts
+	sp += 4;
+	SYSCFG = [sp++];
+	SEQSTAT = [sp++];
+	RETE = [sp++];
+	RETN = [sp++];
+	RETX = [sp++];
+	RETI = [sp++];
+	RETS = [sp++];
+
+	sp += 4;
+
+	ASTAT = [sp++];
+
+	LB1 = [sp++];
+	LB0 = [sp++];
+	LT1 = [sp++];
+	LT0 = [sp++];
+	LC1 = [sp++];
+	LC0 = [sp++];
+
+	a1.w = [sp++];
+	a1.x = [sp++];
+	a0.w = [sp++];
+	a0.x = [sp++];
+	b3 = [sp++];
+	b2 = [sp++];
+	b1 = [sp++];
+	b0 = [sp++];
+
+	l3 = [sp++];
+	l2 = [sp++];
+	l1 = [sp++];
+	l0 = [sp++];
+
+	m3 = [sp++];
+	m2 = [sp++];
+	m1 = [sp++];
+	m0 = [sp++];
+
+	i3 = [sp++];
+	i2 = [sp++];
+	i1 = [sp++];
+	i0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+
+	( R7 : 0, P5 : 0) = [ SP ++ ];
+	sp += 4;
+.endm
+
+#if !defined(NEW_PT_REGS)
+/*
+ * a -1 in the orig_r0 field signifies
+ * that the stack frame is NOT for syscall
+ */
+.macro	save_all_int
+/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */
+	[--sp] = r0;
+	r0.l = 0x30;		/* Errata for BF533 */
+	r0.h = 0x0;
+	syscfg = r0;		/* disable single step flag in SYSCFG */
+	r0 = [sp++];
+	[--sp] = syscfg;	/* store SYSCFG */
+
+	[--sp] = r0;	/* Reserved for IPEND */
+	[--sp] = fp;
+	[--sp] = usp;
+	[--sp] = r0;
+
+	[--sp] = r0;
+	r0 = [sp + 8];
+	[--sp] = a0.x;
+	[--sp] = a1.x;
+	[--sp] = a0.w;
+	[--sp] = a1.w;
+	[--sp] = rets;
+	[--sp] = astat;
+	[--sp] = seqstat;
+	[--sp] = retx;	/* current pc when exception happens */
+	[--sp] = ( r7:5, p5:0 );
+	[--sp] = r1;
+	[--sp] = r2;
+	[--sp] = r4;
+	[--sp] = r3;
+.endm
+
+.macro	save_all_sys
+	[--sp] = r0;
+	[--sp] = r0;
+	[--sp] = a0.x;
+	[--sp] = a1.x;
+	[--sp] = a0.w;
+	[--sp] = a1.w;
+	[--sp] = rets;
+	[--sp] = astat;
+	[--sp] = seqstat;
+	[--sp] = retx;	/* current pc when exception happens */
+	[--sp] = ( r7:5, p5:0 );
+	[--sp] = r1;
+	[--sp] = r2;
+	[--sp] = r4;
+	[--sp] = r3;
+.endm
+
+.macro	restore_all
+	r3 = [sp++];
+	r4 = [sp++];
+	r2 = [sp++];
+	r1 = [sp++];
+	( r7:5, p5:0 ) = [sp++];
+	retx = [sp++];
+	seqstat = [sp++];
+	astat = [sp++];
+	rets = [sp++];
+	a1.w = [sp++];
+	a0.w = [sp++];
+	a1.x = [sp++];
+	a0.x = [sp++];
+	sp += 4;	/* orig r0 */
+	r0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+	sp +=4;		/* Skip the IPEND */
+
+	syscfg = [sp++];
+
+.endm
+
+#endif
+
+#define STR(X) 			STR1(X)
+#define STR1(X) 		#X
+
+#if defined(NEW_PT_REGS)
+
+#define PT_OFF_ORIG_R0		208
+#define PT_OFF_SR		8
+
+#else
+
+#define PT_OFF_ORIG_R0		0x54
+#define PT_OFF_SR		0x38	/* seqstat in pt_regs */
+
+#endif
+#endif
+
+#endif
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
new file mode 100644
index 0000000..713bba0
--- /dev/null
+++ b/include/asm-blackfin/errno.h
@@ -0,0 +1,156 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_ERRNO_H
+#define _BLACKFIN_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Arg list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
new file mode 100644
index 0000000..56a12f0
--- /dev/null
+++ b/include/asm-blackfin/global_data.h
@@ -0,0 +1,64 @@
+/*
+ * U-boot - global_data.h Declarations for global data of u-boot
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/irq.h>
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+typedef struct global_data {
+	bd_t *bd;
+	unsigned long flags;
+	unsigned long board_type;
+	unsigned long baudrate;
+	unsigned long have_console;	/* serial_init() was called */
+	unsigned long ram_size;		/* RAM size */
+	unsigned long reloc_off;	/* Relocation Offset */
+	unsigned long env_addr;		/* Address  of Environment struct */
+	unsigned long env_valid;	/* Checksum of Environment valid? */
+	void **jt;			/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001	/* Code was relocated to RAM     */
+#define	GD_FLG_DEVINIT	0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT	0x00004	/* Silent mode                   */
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P5")
+
+#endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
new file mode 100644
index 0000000..1ee050e
--- /dev/null
+++ b/include/asm-blackfin/hw_irq.h
@@ -0,0 +1,37 @@
+/*
+ * U-boot - hw_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h
+ * BlackFin (ADI) assembler restricted values by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc <mattw@lineo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_EZKIT533
+#include <asm/board/bf533_irq.h>
+#endif
+#ifdef CONFIG_STAMP
+#include <asm/board/bf533_irq.h>
+#endif
diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h
new file mode 100644
index 0000000..0b0572f
--- /dev/null
+++ b/include/asm-blackfin/io-kernel.h
@@ -0,0 +1,135 @@
+/*
+ * U-boot - io-kernel.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
+ * two accesses to memory, which may be undesireable for some devices.
+ */
+#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
+#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
+#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
+#define inb(addr)	cf_inb((volatile unsigned char*)(addr))
+#define inw(addr)	readw(addr)
+#define inl(addr)	readl(addr)
+#define outb(x,addr)	cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
+#define outw(x,addr)	((void) writew(x,addr))
+#define outl(x,addr)	((void) writel(x,addr))
+#define inb_p(addr)	inb(addr)
+#define inw_p(addr)	inw(addr)
+#define inl_p(addr)	inl(addr)
+#define outb_p(x,addr)	outb(x,addr)
+#define outw_p(x,addr)	outw(x,addr)
+#define outl_p(x,addr)	outl(x,addr)
+#define insb(port, addr, count)	memcpy((void*)addr, (void*)port, count)
+#define insw(port, addr, count)	cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
+#define insl(port, addr, count)	memcpy((void*)addr, (void*)port, (4*count))
+#define outsb(port, addr, count)	memcpy((void*)port, (void*)addr, count)
+#define outsw(port,addr,count)		cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
+#define outsl(port, addr, count)	memcpy((void*)port, (void*)addr, (4*count))
+#define IO_SPACE_LIMIT	0xffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING		0
+#define IOMAP_NOCACHE_SER		1
+#define IOMAP_NOCACHE_NONSER		2
+#define IOMAP_WRITETHROUGH		3
+
+#ifndef __ASSEMBLY__
+extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+extern void iounmap(void *addr);
+
+/* Nothing to do */
+
+extern void blkfin_inv_cache_all(void);
+
+#endif
+
+#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size) do { } while (0)
+#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+
+/* Pages to physical address... */
+#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
+#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
+
+#define mm_ptov(vaddr)		((void *) (vaddr))
+#define mm_vtop(vaddr)		((unsigned long) (vaddr))
+#define phys_to_virt(vaddr)	((void *) (vaddr))
+#define virt_to_phys(vaddr)	((unsigned long) (vaddr))
+
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+#endif
+
+#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
new file mode 100644
index 0000000..e5b388e
--- /dev/null
+++ b/include/asm-blackfin/io.h
@@ -0,0 +1,122 @@
+/*
+ * U-boot - io.h IO routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/* function prototypes for CF support */
+extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
+extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
+extern unsigned char cf_inb(volatile unsigned char *addr);
+extern void cf_outb(unsigned char val, volatile unsigned char* addr);
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+
+
+#define readb(addr)		({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
+#define readw(addr)		({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
+#define readl(addr)		({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
+
+#define writeb(b,addr)		{((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");}
+#define writew(b,addr)		{((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");}
+#define writel(b,addr)		{((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");}
+
+#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
+
+#define inb_p(addr)		readb((addr) + BF533_PCIIO_BASE)
+#define inb(addr)		cf_inb((volatile unsigned char*)(addr))
+
+#define outb(x,addr)		cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
+#define outb_p(x,addr)		outb(x, (addr) + BF533_PCIIO_BASE)
+
+#define inw(addr)		readw((addr) + BF533_PCIIO_BASE)
+#define inl(addr)		readl((addr) + BF533_PCIIO_BASE)
+
+#define outw(x,addr)		writew(x, (addr) + BF533_PCIIO_BASE)
+#define outl(x,addr)		writel(x, (addr) + BF533_PCIIO_BASE)
+
+#define insb(port, addr, count)	memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count)
+#define insw(port, addr, count)	cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
+#define insl(port, addr, count)	memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count))
+
+#define outsb(port,addr,count)	memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count)
+#define outsw(port,addr,count)	cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
+#define outsl(port,addr,count)	memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count))
+
+#define IO_SPACE_LIMIT		0xffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING	0
+#define IOMAP_NOCACHE_SER	1
+#define IOMAP_NOCACHE_NONSER	2
+#define IOMAP_WRITETHROUGH	3
+
+extern void *__ioremap(unsigned long physaddr, unsigned long size,
+		       int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+
+extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_nocache(unsigned long physaddr,
+				    unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_writethrough(unsigned long physaddr,
+					 unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *ioremap_fullcache(unsigned long physaddr,
+				      unsigned long size)
+{
+	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+extern void iounmap(void *addr);
+
+extern void blkfin_inv_cache_all(void);
+#define dma_cache_inv(_start,_size)		do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size)		do { } while (0)
+#define dma_cache_wback_inv(_start,_size)	do { blkfin_inv_cache_all();} while (0)
+
+#endif
+#endif
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
new file mode 100644
index 0000000..5fbc5a3
--- /dev/null
+++ b/include/asm-blackfin/irq.h
@@ -0,0 +1,142 @@
+/*
+ * U-boot - irq.h Interrupt related header file
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file was based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ *
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IRQ_H_
+#define _BLACKFIN_IRQ_H_
+
+#include <linux/config.h>
+#include <asm/cpu/bf533_irq.h>
+
+/*
+ *   On the Blackfin, the interrupt structure allows remmapping of the hardware
+ *   levels.
+ * - I'm going to assume that the H/W level is going to stay at the default
+ *   settings. If someone wants to go through and abstart this out, feel free
+ *   to mod the interrupt numbering scheme.
+ * - I'm abstracting the interrupts so that uClinux does not know anything
+ *   about the H/W levels. If you want to change the H/W AND keep the abstracted
+ *   levels that uClinux sees, you should be able to do most of it here.
+ * - I've left the "abstract" numbering sparce in case someone wants to pull the
+ *   interrupts apart (just the TX/RX for the various devices)
+ */
+
+#define	NR_IRQS		SYS_IRQS
+/*
+ * "Generic" interrupt sources
+ */
+#define IRQ_SCHED_TIMER	(8)	/* interrupt source for scheduling timer */
+
+static __inline__ int irq_cannonicalize(int irq)
+{
+	return irq;
+}
+
+/*
+ * Machine specific interrupt sources.
+ *
+ * Adding an interrupt service routine for a source with this bit
+ * set indicates a special machine specific interrupt source.
+ * The machine specific files define these sources.
+ *
+ * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
+ * introduce unnecessary overhead.
+ *
+ * All interrupt handling is actually machine specific so it is better
+ * to use function pointers, as used by the Sparc port, and select the
+ * interrupt handling functions when initializing the kernel. This way
+ * we save some unnecessary overhead at run-time.
+ * 01/11/97 - Jes
+ */
+
+extern void (*mach_enable_irq) (unsigned int);
+extern void (*mach_disable_irq) (unsigned int);
+extern int sys_request_irq(unsigned int,
+			void (*)(int, void *, struct pt_regs *),
+			unsigned long, const char *, void *);
+extern void sys_free_irq(unsigned int, void *);
+
+/*
+ * various flags for request_irq() - the Amiga now uses the standard
+ * mechanism like all other architectures - SA_INTERRUPT and SA_SHIRQ
+ * are your friends.
+ */
+#define IRQ_FLG_LOCK	(0x0001)	/* handler is not replaceable   */
+#define IRQ_FLG_REPLACE	(0x0002)	/* replace existing handler     */
+#define IRQ_FLG_FAST	(0x0004)
+#define IRQ_FLG_SLOW	(0x0008)
+#define IRQ_FLG_STD	(0x8000)	/* internally used              */
+
+/*
+ * This structure is used to chain together the ISRs for a particular
+ * interrupt source (if it supports chaining).
+ */
+typedef struct irq_node {
+	void (*handler) (int, void *, struct pt_regs *);
+	unsigned long flags;
+	void *dev_id;
+	const char *devname;
+	struct irq_node *next;
+} irq_node_t;
+
+/*
+ * This structure has only 4 elements for speed reasons
+ */
+typedef struct irq_handler {
+	void (*handler) (int, void *, struct pt_regs *);
+	unsigned long flags;
+	void *dev_id;
+	const char *devname;
+} irq_handler_t;
+
+/* count of spurious interrupts */
+extern volatile unsigned int num_spurious;
+
+/*
+ * This function returns a new irq_node_t
+ */
+extern irq_node_t *new_irq_node(void);
+
+/*
+ * Some drivers want these entry points
+ */
+#define enable_irq(x)	(mach_enable_irq  ? (*mach_enable_irq)(x)  : 0)
+#define disable_irq(x)	(mach_disable_irq ? (*mach_disable_irq)(x) : 0)
+
+#define enable_irq_nosync(x)	enable_irq(x)
+#define disable_irq_nosync(x)	disable_irq(x)
+
+#endif
diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
new file mode 100644
index 0000000..18f0c36
--- /dev/null
+++ b/include/asm-blackfin/linkage.h
@@ -0,0 +1,60 @@
+/*
+ * U-boot - linkage.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <linux/config.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE		extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#define asmlinkage CPP_ASMLINKAGE
+
+#define SYMBOL_NAME_STR(X)	#X
+#define SYMBOL_NAME(X)		X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X)	X##:
+#else
+#define SYMBOL_NAME_LABEL(X)	X:
+#endif
+
+#define __ALIGN .align		4
+#define __ALIGN_STR		".align 4"
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN			__ALIGN
+#define ALIGN_STR		__ALIGN_STR
+
+#define ENTRY(name) \
+	.globl SYMBOL_NAME(name); \
+	ALIGN; \
+	SYMBOL_NAME_LABEL(name)
+#endif
+
+#endif
diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h
new file mode 100644
index 0000000..0a43ba1
--- /dev/null
+++ b/include/asm-blackfin/machdep.h
@@ -0,0 +1,89 @@
+/*
+ * U-boot - machdep.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_MACHDEP_H
+#define _BLACKFIN_MACHDEP_H
+
+/* Machine dependent initial routines:
+ *
+ * Based on include/asm-m68knommu/machdep.h
+ * For blackfin, just now we only have bfin, so they'd point to the default bfin
+ *
+ */
+
+struct pt_regs;
+struct kbd_repeat;
+struct mktime;
+struct hwclk_time;
+struct gendisk;
+struct buffer_head;
+
+extern void (*mach_sched_init) (void (*handler)	(int, void *, struct pt_regs *));
+
+/* machine dependent keyboard functions */
+extern int (*mach_keyb_init) (void);
+extern int (*mach_kbdrate) (struct kbd_repeat *);
+extern void (*mach_kbd_leds) (unsigned int);
+
+/* machine dependent irq functions */
+extern void (*mach_init_IRQ) (void);
+extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *);
+extern int (*mach_request_irq) (unsigned int irq,
+				void (*handler) (int, void *,
+						 struct pt_regs *),
+				unsigned long flags, const char *devname,
+				void *dev_id);
+extern void (*mach_free_irq) (unsigned int irq, void *dev_id);
+extern void (*mach_get_model) (char *model);
+extern int (*mach_get_hardware_list) (char *buffer);
+extern int (*mach_get_irq_list) (char *buf);
+extern void (*mach_process_int) (int irq, struct pt_regs * fp);
+
+/* machine dependent timer functions */
+extern unsigned long (*mach_gettimeoffset) (void);
+extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour,
+			    int *min, int *sec);
+extern int (*mach_hwclk) (int, struct hwclk_time *);
+extern int (*mach_set_clock_mmss) (unsigned long);
+extern void (*mach_reset) (void);
+extern void (*mach_halt) (void);
+extern void (*mach_power_off) (void);
+extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
+extern void (*mach_hd_setup) (char *, int *);
+extern long mach_max_dma_address;
+extern void (*mach_floppy_setup) (char *, int *);
+extern void (*mach_floppy_eject) (void);
+extern void (*mach_heartbeat) (int);
+extern void (*mach_l2_flush) (int);
+extern int mach_sysrq_key;
+extern int mach_sysrq_shift_state;
+extern int mach_sysrq_shift_mask;
+extern char *mach_sysrq_xlate;
+
+#ifdef CONFIG_UCLINUX
+extern void config_BSP(char *command, int len);
+extern void (*mach_tick) (void);
+#endif
+
+#endif
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
new file mode 100644
index 0000000..1a13d90
--- /dev/null
+++ b/include/asm-blackfin/mem_init.h
@@ -0,0 +1,287 @@
+/*
+ * U-boot - mem_init.h Header file for memory initialization
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if ( CONFIG_MEM_MT48LC16M16A2TG_75  ||  CONFIG_MEM_MT48LC64M4A2FB_7E )
+	#if ( CONFIG_SCLK_HZ > 119402985 )
+		#define SDRAM_tRP	TRP_2
+		#define SDRAM_tRP_num	2
+		#define SDRAM_tRAS	TRAS_7
+		#define SDRAM_tRAS_num	7
+		#define SDRAM_tRCD	TRCD_2
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
+		#define SDRAM_tRP	TRP_2
+		#define SDRAM_tRP_num	2
+		#define SDRAM_tRAS	TRAS_6
+		#define SDRAM_tRAS_num	6
+		#define SDRAM_tRCD	TRCD_2
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ >  89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
+		#define SDRAM_tRP	TRP_2
+		#define SDRAM_tRP_num	2
+		#define SDRAM_tRAS	TRAS_5
+		#define SDRAM_tRAS_num	5
+		#define SDRAM_tRCD	TRCD_2
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ >  74626866 ) && ( CONFIG_SCLK_HZ <=  89552239 )
+		#define SDRAM_tRP	TRP_2
+		#define SDRAM_tRP_num	2
+		#define SDRAM_tRAS	TRAS_4
+		#define SDRAM_tRAS_num	4
+		#define SDRAM_tRCD	TRCD_2
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ >  66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
+		#define SDRAM_tRP	TRP_2
+		#define SDRAM_tRP_num	2
+		#define SDRAM_tRAS	TRAS_3
+		#define SDRAM_tRAS_num	3
+		#define SDRAM_tRCD	TRCD_2
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
+		#define SDRAM_tRP	TRP_1
+		#define SDRAM_tRP_num	1
+		#define SDRAM_tRAS	TRAS_4
+		#define SDRAM_tRAS_num	3
+		#define SDRAM_tRCD	TRCD_1
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ >  44776119 ) && ( CONFIG_SCLK_HZ <=  59701493 )
+		#define SDRAM_tRP	TRP_1
+		#define SDRAM_tRP_num	1
+		#define SDRAM_tRAS	TRAS_3
+		#define SDRAM_tRAS_num	3
+		#define SDRAM_tRCD	TRCD_1
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ >  29850746 ) && ( CONFIG_SCLK_HZ <=  44776119 )
+		#define SDRAM_tRP	TRP_1
+		#define SDRAM_tRP_num	1
+		#define SDRAM_tRAS	TRAS_2
+		#define SDRAM_tRAS_num	2
+		#define SDRAM_tRCD	TRCD_1
+		#define SDRAM_tWR	TWR_2
+	#endif
+	#if ( CONFIG_SCLK_HZ <=  29850746 )
+		#define SDRAM_tRP	TRP_1
+		#define SDRAM_tRP_num	1
+		#define SDRAM_tRAS	TRAS_1
+		#define SDRAM_tRAS_num	1
+		#define SDRAM_tRCD	TRCD_1
+		#define SDRAM_tWR	TWR_2
+	#endif
+#endif
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_CL	CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_CL	CL_2
+#endif
+
+#if ( CONFIG_MEM_SIZE == 128 )
+	#define SDRAM_SIZE	EBSZ_128
+#endif
+#if ( CONFIG_MEM_SIZE == 64 )
+	#define SDRAM_SIZE	EBSZ_64
+#endif
+#if (  CONFIG_MEM_SIZE == 32 )
+	#define SDRAM_SIZE	EBSZ_32
+#endif
+#if ( CONFIG_MEM_SIZE == 16 )
+	#define SDRAM_SIZE	EBSZ_16
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 11 )
+	#define SDRAM_WIDTH	EBCAW_11
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 10 )
+	#define SDRAM_WIDTH	EBCAW_10
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 9 )
+	#define SDRAM_WIDTH	EBCAW_9
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 8 )
+	#define SDRAM_WIDTH	EBCAW_8
+#endif
+
+#define mem_SDBCTL	SDRAM_WIDTH | SDRAM_SIZE | EBE
+
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC	((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL	( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
+
+#define flash_EBIU_AMBCTL_WAT	( ( CONFIG_FLASH_SPEED_BWAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_RAT	( ( CONFIG_FLASH_SPEED_BRAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_HT	( ( CONFIG_FLASH_SPEED_BHT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) )
+#define flash_EBIU_AMBCTL_ST	( ( CONFIG_FLASH_SPEED_BST  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_TT	( ( CONFIG_FLASH_SPEED_BTT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3 )
+	#define flash_EBIU_AMBCTL0_TT	B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3 )
+	#define flash_EBIU_AMBCTL0_TT	B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2 )
+	#define flash_EBIU_AMBCTL0_TT	B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2 )
+	#define flash_EBIU_AMBCTL0_TT	B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3 )
+	#define flash_EBIU_AMBCTL0_ST	B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3 )
+	#define flash_EBIU_AMBCTL0_ST	B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2 )
+	#define flash_EBIU_AMBCTL0_ST	B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2 )
+	#define flash_EBIU_AMBCTL0_ST	B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2 )
+	#define flash_EBIU_AMBCTL0_HT	B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2 )
+	#define flash_EBIU_AMBCTL0_HT	B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1 )
+	#define flash_EBIU_AMBCTL0_HT	B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT == 0)
+	#define flash_EBIU_AMBCTL0_HT	B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT != 0)
+	#define flash_EBIU_AMBCTL0_HT	B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+	#define flash_EBIU_AMBCTL0_WAT	B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+	#define flash_EBIU_AMBCTL0_RAT	B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0	flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
new file mode 100644
index 0000000..406ece5
--- /dev/null
+++ b/include/asm-blackfin/page.h
@@ -0,0 +1,128 @@
+/*
+ * U-boot -  page.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_PAGE_H
+#define _BLACKFIN_PAGE_H
+
+#include <linux/config.h>
+
+/* PAGE_SHIFT determines the page size */
+
+#define PAGE_SHIFT			(12)
+#define PAGE_SIZE			(4096)
+#define PAGE_MASK			(~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+#include <asm/setup.h>
+
+#if PAGE_SHIFT < 13
+#define					KTHREAD_SIZE (8192)
+#else
+#define					KTHREAD_SIZE PAGE_SIZE
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define get_user_page(vaddr)		__get_free_page(GFP_KERNEL)
+#define free_user_page(page, addr)	free_page(addr)
+
+#define clear_page(page)		memset((page), 0, PAGE_SIZE)
+#define copy_page(to,from)		memcpy((to), (from), PAGE_SIZE)
+
+#define clear_user_page(page, vaddr)	clear_page(page)
+#define copy_user_page(to, from, vaddr)	copy_page(to, from)
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct {
+	unsigned long pte;
+} pte_t;
+typedef struct {
+	unsigned long pmd[16];
+} pmd_t;
+typedef struct {
+	unsigned long pgd;
+} pgd_t;
+typedef struct {
+	unsigned long pgprot;
+} pgprot_t;
+
+#define pte_val(x)			((x).pte)
+#define pmd_val(x)			((&x)->pmd[0])
+#define pgd_val(x)			((x).pgd)
+#define pgprot_val(x)			((x).pgprot)
+
+#define __pte(x)			((pte_t) { (x) } )
+#define __pmd(x)			((pmd_t) { (x) } )
+#define __pgd(x)			((pgd_t) { (x) } )
+#define __pgprot(x)			((pgprot_t) { (x) } )
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)		(((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
+/* Pure 2^n version of get_order */
+extern __inline__ int get_order(unsigned long size)
+{
+	int order;
+
+	size = (size - 1) >> (PAGE_SHIFT - 1);
+	order = -1;
+	do {
+		size >>= 1;
+		order++;
+	} while (size);
+	return order;
+}
+
+#endif	/* !__ASSEMBLY__ */
+
+#include <asm/page_offset.h>
+
+#define PAGE_OFFSET			(PAGE_OFFSET_RAW)
+
+#ifndef __ASSEMBLY__
+
+#define __pa(vaddr)			virt_to_phys((void *)vaddr)
+#define __va(paddr)			phys_to_virt((unsigned long)paddr)
+
+#define MAP_NR(addr)			(((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
+#define virt_to_page(addr)		(mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
+#define VALID_PAGE(page)		((page - mem_map) < max_mapnr)
+
+#define BUG() do	{ \
+	 \
+	while (1);	/* dead-loop */ \
+} while (0)
+
+#define PAGE_BUG(page) do	{ \
+	BUG(); \
+} while (0)
+
+#endif
+
+#endif
+
+#endif
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
new file mode 100644
index 0000000..45e34b5
--- /dev/null
+++ b/include/asm-blackfin/page_offset.h
@@ -0,0 +1,35 @@
+/*
+ * U-boot - page_offset.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* 
+ * Changes made by Akbar Hussain April 10, 2001
+ */
+
+#include <linux/config.h>
+
+/* This handles the memory map.. */
+
+#ifdef CONFIG_BLACKFIN
+#define PAGE_OFFSET_RAW		0x00000000
+#endif
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
new file mode 100644
index 0000000..f1f2b5f
--- /dev/null
+++ b/include/asm-blackfin/posix_types.h
@@ -0,0 +1,90 @@
+/*
+ * U-boot - posix_types.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
+#define __ARCH_BLACKFIN_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int val[2];
+#else				/* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int __val[2];
+#endif				/* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef	__FD_CLR
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef	__FD_ISSET
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif	/* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
new file mode 100644
index 0000000..19bd720
--- /dev/null
+++ b/include/asm-blackfin/processor.h
@@ -0,0 +1,174 @@
+/*
+ * U-boot - processor.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * include/asm-m68k/processor.h
+ * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
+ * Copyright (C) 1995 Hamish Macdonald
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_BLACKFIN_PROCESSOR_H
+#define __ASM_BLACKFIN_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr()	({ __label__ _l; _l: &&_l;})
+
+#include <linux/config.h>
+#include <asm/segment.h>
+#include <asm/ptrace.h>
+#include <asm/current.h>
+
+extern inline unsigned long rdusp(void)
+{
+	unsigned long usp;
+
+	__asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
+	return usp;
+}
+
+extern inline void wrusp(unsigned long usp)
+{
+	__asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
+}
+
+/*
+ * User space process size: 3.75GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#define TASK_SIZE		(0xF0000000UL)
+
+/*
+ * Bus types
+ */
+#define EISA_bus		0
+#define MCA_bus			0
+
+/*  There is no pc register avaliable for BLACKFIN, so we are going to get
+ *  it indirectly
+ */
+
+#if 0
+inline unsigned long obtain_pc_indirectly(void)
+{
+	unsigned long pc;
+	__asm__ __volatile__("%0 = rets;\n":"=d"(pc));
+	return (pc - 4);	/* call pcrel24 is 4 bytes long  */
+}
+#endif
+
+/*
+ * if you change this structure, you must change the code and offsets
+ * in m68k/machasm.S
+ */
+
+struct thread_struct {
+	unsigned long ksp;	/* kernel stack pointer */
+	unsigned long usp;	/* user stack pointer */
+	unsigned short seqstat;	/* saved status register */
+	unsigned long esp0;	/* points to SR of stack frame pt_regs */
+	unsigned long pc;	/* instruction pointer */
+};
+
+#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
+
+#define INIT_THREAD  { \
+	sizeof(init_stack) + (unsigned long) init_stack, 0, \
+	PS_S, 0\
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ *
+ * pass the data segment into user programs if it exists,
+ * it can't hurt anything as far as I can tell
+ */
+#define start_thread(_regs, _pc, _usp)           \
+do {                                             \
+	set_fs(USER_DS); /* reads from user space */ \
+	(_regs)->pc = (_pc);                         \
+	if (current->mm)                             \
+		(_regs)->r5 = current->mm->start_data;   \
+	(_regs)->seqstat &= ~0x0c00;                      \
+	wrusp(_usp);                                 \
+	/* Adde by HuTao, May 26, 2003 3:39PM */\
+	if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\
+		(_regs)->ipend = 0x0;\
+} while(0)
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+
+extern int kernel_thread(int (*fn) (void *), void *arg,
+			 unsigned long flags);
+
+#define copy_segments(tsk, mm)		do { } while (0)
+#define release_segments(mm)		do { } while (0)
+#define forget_segments()		do { } while (0)
+
+/*
+ * Free current thread data structures etc..
+ */
+static inline void exit_thread(void)
+{
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+	extern void scheduling_functions_start_here(void);
+	extern void scheduling_functions_end_here(void);
+	return 0;
+}
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define	KSTK_EIP(tsk)	\
+	({			\
+	unsigned long eip = 0;	 \
+	if ((tsk)->thread.esp0 > PAGE_SIZE && \
+		MAP_NR((tsk)->thread.esp0) < max_mapnr) \
+		eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
+	eip; })
+#define	KSTK_ESP(tsk)	((tsk) == current ? rdusp() : (tsk)->thread.usp)
+#define THREAD_SIZE	(2*PAGE_SIZE)
+
+/* Allocation and freeing of basic task resources. */
+#define alloc_task_struct() \
+	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define free_task_struct(p)	free_pages((unsigned long)(p),1)
+#define get_task_struct(tsk)	atomic_inc(&mem_map[MAP_NR(tsk)].count)
+
+#define init_task		(init_task_union.task)
+#define init_stack		(init_task_union.stack)
+
+#endif
diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
new file mode 100644
index 0000000..afd5777
--- /dev/null
+++ b/include/asm-blackfin/ptrace.h
@@ -0,0 +1,269 @@
+/*
+ * U-boot - ptrace.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_PTRACE_H
+#define _BLACKFIN_PTRACE_H
+
+#define NEW_PT_REGS
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 7 are data registers R0-R7
+ *       8 - 15 are address registers P0-P7
+ *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
+ *      32 - 33 A registers A0 & A1
+ *      34 -    status register
+ *
+ * We follows above, except:
+ *      32-33 --- Low 32-bit of A0&1
+ *      34-35 --- High 8-bit of A0&1
+ */
+
+#if defined(NEW_PT_REGS)
+
+#define PT_IPEND	0
+#define PT_SYSCFG	(PT_IPEND+4)
+#define PT_SEQSTAT	(PT_SYSCFG+4)
+#define PT_RETE		(PT_SEQSTAT+4)
+#define PT_RETN		(PT_RETE+4)
+#define PT_RETX		(PT_RETN+4)
+#define PT_RETI		(PT_RETX+4)
+#define PT_PC		PT_RETI
+#define PT_RETS		(PT_RETI+4)
+#define PT_RESERVED	(PT_RETS+4)
+#define PT_ASTAT	(PT_RESERVED+4)
+#define PT_LB1		(PT_ASTAT+4)
+#define PT_LB0		(PT_LB1+4)
+#define PT_LT1		(PT_LB0+4)
+#define PT_LT0		(PT_LT1+4)
+#define PT_LC1		(PT_LT0+4)
+#define PT_LC0		(PT_LC1+4)
+#define PT_A1W		(PT_LC0+4)
+#define PT_A1X		(PT_A1W+4)
+#define PT_A0W		(PT_A1X+4)
+#define PT_A0X		(PT_A0W+4)
+#define PT_B3		(PT_A0X+4)
+#define PT_B2		(PT_B3+4)
+#define PT_B1		(PT_B2+4)
+#define PT_B0		(PT_B1+4)
+#define PT_L3		(PT_B0+4)
+#define PT_L2		(PT_L3+4)
+#define PT_L1		(PT_L2+4)
+#define PT_L0		(PT_L1+4)
+#define PT_M3		(PT_L0+4)
+#define PT_M2		(PT_M3+4)
+#define PT_M1		(PT_M2+4)
+#define PT_M0		(PT_M1+4)
+#define PT_I3		(PT_M0+4)
+#define PT_I2		(PT_I3+4)
+#define PT_I1		(PT_I2+4)
+#define PT_I0		(PT_I1+4)
+#define PT_USP		(PT_I0+4)
+#define PT_FP		(PT_USP+4)
+#define PT_P5		(PT_FP+4)
+#define PT_P4		(PT_P5+4)
+#define PT_P3		(PT_P4+4)
+#define PT_P2		(PT_P3+4)
+#define PT_P1		(PT_P2+4)
+#define PT_P0		(PT_P1+4)
+#define PT_R7		(PT_P0+4)
+#define PT_R6		(PT_R7+4)
+#define PT_R5		(PT_R6+4)
+#define PT_R4		(PT_R5+4)
+#define PT_R3		(PT_R4+4)
+#define PT_R2		(PT_R3+4)
+#define PT_R1		(PT_R2+4)
+#define PT_R0		(PT_R1+4)
+#define PT_ORIG_R0	(PT_R0+4)
+#define PT_SR		PT_SEQSTAT
+
+#else
+/*
+ * Here utilize blackfin : dpregs = [pregs + imm16s4]
+ *                     [pregs + imm16s4] = dpregs
+ * to access defferent saved reg in stack
+ */
+#define PT_R3		0
+#define PT_R4		4
+#define PT_R2		8
+#define PT_R1		12
+#define PT_P5		16
+#define PT_P4		20
+#define PT_P3		24
+#define PT_P2		28
+#define PT_P1		32
+#define PT_P0		36
+#define PT_R7		40
+#define PT_R6		44
+#define PT_R5		48
+#define PT_PC		52
+#define PT_SEQSTAT	56	/* so-called SR reg */
+#define PT_SR		PT_SEQSTAT
+#define PT_ASTAT	60
+#define PT_RETS		64
+#define PT_A1w		68
+#define PT_A0w		72
+#define PT_A1x		76
+#define PT_A0x		80
+#define PT_ORIG_R0	84
+#define PT_R0		88
+#define PT_USP		92
+#define PT_FP		96
+#define PT_SP		100
+
+/* Added by HuTao, May26 2003 3:18PM */
+#define PT_IPEND	100
+
+/* Add SYSCFG register for single stepping support */
+#define PT_SYSCFG	104
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+#if defined(NEW_PT_REGS)
+/* this struct defines the way the registers are stored on the
+ * stack during a system call.
+ */
+struct pt_regs {
+	long ipend;
+	long syscfg;
+	long seqstat;
+	long rete;
+	long retn;
+	long retx;
+	long pc;
+	long rets;
+	long reserved;
+	long astat;
+	long lb1;
+	long lb0;
+	long lt1;
+	long lt0;
+	long lc1;
+	long lc0;
+	long a1w;
+	long a1x;
+	long a0w;
+	long a0x;
+	long b3;
+	long b2;
+	long b1;
+	long b0;
+	long l3;
+	long l2;
+	long l1;
+	long l0;
+	long m3;
+	long m2;
+	long m1;
+	long m0;
+	long i3;
+	long i2;
+	long i1;
+	long i0;
+	long usp;
+	long fp;
+	long p5;
+	long p4;
+	long p3;
+	long p2;
+	long p1;
+	long p0;
+	long r7;
+	long r6;
+	long r5;
+	long r4;
+	long r3;
+	long r2;
+	long r1;
+	long r0;
+	long orig_r0;
+};
+
+#else
+/* now we don't know what regs the system call will use	*/
+struct pt_regs {
+	long r3;
+	long r4;
+	long r2;
+	long r1;
+	long p5;
+	long p4;
+	long p3;
+	long p2;
+	long p1;
+	long p0;
+	long r7;
+	long r6;
+	long r5;
+	unsigned long pc;
+	unsigned long seqstat;
+	unsigned long astat;
+	unsigned long rets;
+	long a1w;
+	long a0w;
+	long a1x;
+	long a0x;
+	long orig_r0;
+	long r0;
+	long usp;
+	long fp;
+/*
+ * Added for supervisor/user mode switch.
+ *
+ * HuTao May26 03 3:23PM
+ */
+	long ipend;
+	long syscfg;
+};
+
+#endif
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS		12
+#define PTRACE_SETREGS		13	/* ptrace signal */
+
+#ifdef __KERNEL__
+
+#ifndef PS_S
+#define PS_S			(0x0c00)
+
+/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
+ *        00: user
+ *        01: supervisor
+ *        1x: debug
+ */
+
+#define PS_M			(0x1000)	/* I am not sure why this is required here Akbar */
+#endif
+
+#define user_mode(regs)			(!((regs)->seqstat & PS_S))
+#define instruction_pointer(regs)	((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#endif
+#endif
+#endif
diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
new file mode 100644
index 0000000..9e6d817
--- /dev/null
+++ b/include/asm-blackfin/segment.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - segment.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SEGMENT_H
+#define _BLACKFIN_SEGMENT_H
+
+/* define constants */
+typedef unsigned long mm_segment_t;	/* domain register */
+
+#define KERNEL_CS		0x0
+#define KERNEL_DS		0x0
+#define __KERNEL_CS		0x0
+#define __KERNEL_DS		0x0
+
+#define USER_CS			0x1
+#define USER_DS			0x1
+#define __USER_CS		0x1
+#define __USER_DS		0x1
+
+#define get_ds()		(KERNEL_DS)
+#define get_fs()		(__USER_DS)
+#define segment_eq(a,b)		((a) == (b))
+#define set_fs(val)
+
+#endif
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
new file mode 100644
index 0000000..6ce9688
--- /dev/null
+++ b/include/asm-blackfin/setup.h
@@ -0,0 +1,86 @@
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * asm/setup.h -- Definition of the Linux/Blackfin setup information
+ * Copyright Lineo, Inc 2001 Tony Kou
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SETUP_H
+#define _BLACKFIN_SETUP_H
+
+#include <linux/config.h>
+
+/*
+ * Linux/Blackfin Architectures
+ */
+
+#define MACH_BFIN	1
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+extern unsigned long blackfin_machtype;
+#endif
+
+#if defined(CONFIG_BFIN)
+#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN)
+#endif
+
+#ifndef MACH_TYPE
+#define MACH_TYPE (blackfin_machtype)
+#endif
+
+#endif
+
+/*
+ * CPU, FPU and MMU types
+ *
+ * Note: we don't need now:
+ *
+ */
+
+#ifndef __ASSEMBLY__
+extern unsigned long blackfin_cputype;
+#ifdef CONFIG_VME
+extern unsigned long vme_brdtype;
+#endif
+
+/*
+ *  Miscellaneous
+ */
+
+#define NUM_MEMINFO	4
+#define CL_SIZE		256
+
+extern int blackfin_num_memory;	/* # of memory blocks found (and used) */
+extern int blackfin_realnum_memory;	/* real # of memory blocks found */
+extern struct mem_info blackfin_memory[NUM_MEMINFO];	/* memory description */
+
+struct mem_info {
+	unsigned long addr;	/* physical address of memory chunk */
+	unsigned long size;	/* length of memory chunk (in bytes) */
+};
+#endif
+
+#endif
diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h
new file mode 100644
index 0000000..fbef186
--- /dev/null
+++ b/include/asm-blackfin/shared_resources.h
@@ -0,0 +1,33 @@
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SHARED_RESOURCES_H_
+#define _SHARED_RESOURCES_H_
+
+void swap_to(int device_id);
+
+#define FLASH 	 0
+#define ETHERNET 1
+
+#endif /* _SHARED_RESOURCES_H_ */
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
new file mode 100644
index 0000000..ffd81d6
--- /dev/null
+++ b/include/asm-blackfin/string.h
@@ -0,0 +1,79 @@
+/*
+ * U-boot - string.h String functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Changed by Lineo Inc. May 2001 */
+
+#ifndef _BLACKFINNOMMU_STRING_H_
+#define _BLACKFINNOMMU_STRING_H_
+
+#ifdef __KERNEL__		/* only set these up for kernel code */
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/cpu/defBF533.h>
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
+#define __HAVE_ARCH_MEMCPY
+
+extern char *strcpy(char *dest, const char *src);
+extern char *strncpy(char *dest, const char *src, size_t n);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, size_t count);
+extern void * memcpy(void * dest,const void *src,size_t count);
+extern void *memset(void *s, int c, size_t count);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+
+#else				/* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY	1
+#define __HAVE_ARCH_STRNCPY	1
+#define __HAVE_ARCH_STRCAT	1
+#define __HAVE_ARCH_STRNCAT	1
+#define __HAVE_ARCH_STRCMP	1
+#define __HAVE_ARCH_STRNCMP	1
+#define __HAVE_ARCH_STRNICMP	1
+#define __HAVE_ARCH_STRCHR	1
+#define __HAVE_ARCH_STRRCHR	1
+#define __HAVE_ARCH_STRSTR	1
+#define __HAVE_ARCH_STRLEN	1
+#define __HAVE_ARCH_STRNLEN	1
+#define __HAVE_ARCH_MEMSET	1
+#define __HAVE_ARCH_MEMCPY	1
+#define __HAVE_ARCH_MEMMOVE	1
+#define __HAVE_ARCH_MEMSCAN	1
+#define __HAVE_ARCH_MEMCMP	1
+#define __HAVE_ARCH_MEMCHR	1
+#define __HAVE_ARCH_STRTOK	1
+
+#endif				/* KERNEL */
+
+#endif				/* _BLACKFIN_STRING_H_ */
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
new file mode 100644
index 0000000..0e53adf
--- /dev/null
+++ b/include/asm-blackfin/system.h
@@ -0,0 +1,182 @@
+/*
+ * U-boot - system.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SYSTEM_H
+#define _BLACKFIN_SYSTEM_H
+
+#include <linux/config.h>	/* get configuration macros */
+#include <asm/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/segment.h>
+#include <asm/entry.h>
+
+#define prepare_to_switch()	do { } while(0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.  This
+ * also clears the TS-flag if the task we switched to has used the
+ * math co-processor latest.
+ *
+ * 05/25/01 - Tony Kou (tonyko@lineo.ca)
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
+ */
+
+asmlinkage void resume(void);
+
+#define switch_to(prev,next,last)	{					\
+	void *_last;								\
+	__asm__ __volatile__(							\
+  			"r0 = %1;\n\t"						\
+			"r1 = %2;\n\t"						\
+			"call resume;\n\t" 					\
+			"%0 = r0;\n\t"						\
+			: "=d" (_last)						\
+			: "d" (prev),						\
+			"d" (next)						\
+			: "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
+			(last) = _last;						\
+}
+
+/* Force kerenl switch to user mode -- Steven Chen */
+#define switch_to_user_mode()	{						\
+	__asm__ __volatile__(							\
+			"call kernel_to_user_mode;\n\t"				\
+			::							\
+			: "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
+}
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define __sti()	{			\
+	__asm__ __volatile__ (		\
+		"r3 = %0;"		\
+		"sti r3;"		\
+		::"m"(irq_flags):"R3");	\
+}
+
+#define __cli()	{			\
+	__asm__ __volatile__ (		\
+		"cli r3;"		\
+		:::"R3");		\
+}
+
+#define __save_flags(x)	{		\
+	__asm__ __volatile__ (		\
+		"cli r3;"		\
+		"%0 = r3;"		\
+		"sti r3;"		\
+		::"m"(x):"R3");		\
+}
+
+#define __save_and_cli(x)	{	\
+	__asm__ __volatile__ (          \
+		"cli r3;"		\
+		"%0 = r3;"		\
+		::"m"(x):"R3");		\
+}
+
+#define __restore_flags(x) {		\
+	__asm__ __volatile__ (		\
+		"r3 = %0;"		\
+		"sti r3;"		\
+		::"m"(x):"R3");		\
+}
+
+/* For spinlocks etc */
+#define local_irq_save(x)	__save_and_cli(x)
+#define local_irq_restore(x)	__restore_flags(x)
+#define local_irq_disable()	__cli()
+#define local_irq_enable()	__sti()
+
+#define cli()			__cli()
+#define sti()			__sti()
+#define save_flags(x)		__save_flags(x)
+#define restore_flags(x)	__restore_flags(x)
+#define save_and_cli(x)		__save_and_cli(x)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t"::)
+#define mb()			asm volatile (""   : : :"memory")
+#define rmb()			asm volatile (""   : : :"memory")
+#define wmb()			asm volatile (""   : : :"memory")
+#define set_rmb(var, value)	do { xchg(&var, value); } while (0)
+#define set_mb(var, value)	set_rmb(var, value)
+#define set_wmb(var, value)	do { var = value; wmb(); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()		mb()
+#define smp_rmb()		rmb()
+#define smp_wmb()		wmb()
+#else
+#define smp_mb()		barrier()
+#define smp_rmb()		barrier()
+#define smp_wmb()		barrier()
+#endif
+
+#define xchg(ptr,x)		((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr)		(xchg((ptr),1))
+
+struct __xchg_dummy {
+	unsigned long a[100];
+};
+#define __xg(x)			((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+				   int size)
+{
+	unsigned long tmp;
+	unsigned long flags = 0;
+
+	save_and_cli(flags);
+
+	switch (size) {
+	case 1:
+	      __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+		break;
+	case 2:
+	      __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+		break;
+	case 4:
+	      __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+		break;
+	}
+	restore_flags(flags);
+	return tmp;
+}
+
+/* Depend on whether Blackfin has hard reset function */
+/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */
+#define HARD_RESET_NOW() ({})
+
+#endif	/* _BLACKFIN_SYSTEM_H */
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
new file mode 100644
index 0000000..29e6eba
--- /dev/null
+++ b/include/asm-blackfin/traps.h
@@ -0,0 +1,86 @@
+/*
+ * U-boot - traps.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/include/asm/traps.h
+ * Copyright (C) 1993        Hamish Macdonald
+ * Lineo, Inc    Jul 2001    Tony Kou
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+  */
+
+#ifndef _BLACKFIN_TRAPS_H
+#define _BLACKFIN_TRAPS_H
+
+#ifndef __ASSEMBLY__
+typedef void (*e_vector) (void);
+extern e_vector vectors[];
+#endif
+
+#define VEC_SYS		(0)
+#define VEC_EXCPT01	(1)
+#define VEC_EXCPT02	(2)
+#define VEC_EXCPT03	(3)
+#define VEC_EXCPT04	(4)
+#define VEC_EXCPT05	(5)
+#define VEC_EXCPT06	(6)
+#define VEC_EXCPT07	(7)
+#define VEC_EXCPT08	(8)
+#define VEC_EXCPT09	(9)
+#define VEC_EXCPT10	(10)
+#define VEC_EXCPT11	(11)
+#define VEC_EXCPT12	(12)
+#define VEC_EXCPT13	(13)
+#define VEC_EXCPT14	(14)
+#define VEC_EXCPT15	(15)
+#define VEC_STEP	(16)
+#define VEC_OVFLOW	(17)
+#define VEC_UNDEF_I	(33)
+#define VEC_ILGAL_I	(34)
+#define VEC_CPLB_VL	(35)
+#define VEC_MISALI_D	(36)
+#define VEC_UNCOV	(37)
+#define VEC_CPLB_M	(38)
+#define VEC_CPLB_MHIT	(39)
+#define VEC_WATCH	(40)
+#define VEC_ISTRU_VL	(41)
+#define VEC_MISALI_I	(42)
+#define VEC_CPLB_I_VL	(43)
+#define VEC_CPLB_I_M	(44)
+#define VEC_CPLB_I_MHIT	(45)
+#define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
+
+#define VECOFF(vec)	((vec)<<2)
+
+#ifndef __ASSEMBLY__
+
+/* Status register bits */
+#define PS_T  (0x8000)
+#define PS_S  (0x0c00)		/*  Supervisor mode = 0b01      */
+#define PS_D  (0x0c00)		/*  Debug mode = 0b1x           */
+#define PS_M  (0x1000)
+#define PS_C  (0x0001)
+
+#endif
+#endif
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
new file mode 100644
index 0000000..942ed27
--- /dev/null
+++ b/include/asm-blackfin/types.h
@@ -0,0 +1,83 @@
+/*
+ * U-boot - types.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_TYPES_H
+#define _BLACKFIN_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+/* HK0617   -- Changes to unsigned long temporarily */
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+#endif
+
+#endif
diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h
new file mode 100644
index 0000000..ec39338
--- /dev/null
+++ b/include/asm-blackfin/u-boot.h
@@ -0,0 +1,47 @@
+/*
+ * U-boot - u-boot.h Structure declarations for board specific data
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+typedef struct bd_info {
+	int bi_baudrate;		/* serial console baudrate */
+	unsigned long bi_ip_addr;	/* IP Address */
+	unsigned char bi_enetaddr[6];	/* Ethernet adress */
+	unsigned long bi_arch_number;	/* unique id for this board */
+	unsigned long bi_boot_params;	/* where this board expects params */
+	unsigned long bi_memstart;	/* start of DRAM memory */
+	unsigned long bi_memsize;	/* size  of DRAM memory in bytes */
+	unsigned long bi_flashstart;	/* start of FLASH memory */
+	unsigned long bi_flashsize;	/* size  of FLASH memory */
+	unsigned long bi_flashoffset;	/* reserved area for startup monitor */
+} bd_t;
+
+#define bi_env_data bi_env->data
+#define bi_env_crc  bi_env->crc
+
+#endif	/* _U_BOOT_H_ */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
new file mode 100644
index 0000000..84b4b4e
--- /dev/null
+++ b/include/asm-blackfin/uaccess.h
@@ -0,0 +1,207 @@
+/*
+ * U-boot - uaccess.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on 
+ * Based on: include/asm-m68knommu/uaccess.h
+ * Changes made by Lineo Inc.    May 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_UACCESS_H
+#define __BLACKFIN_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <asm/segment.h>
+#include <asm/errno.h>
+
+#define VERIFY_READ	0
+#define VERIFY_WRITE	1
+
+/* We let the MMU do all checking */
+static inline int access_ok(int type, const void *addr, unsigned long size)
+{
+	return ((unsigned long) addr < 0x10f00000);	/* need final decision - Tony */
+}
+
+static inline int verify_area(int type, const void *addr,
+			      unsigned long size)
+{
+	return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+	unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define put_user(x, ptr)				\
+({							\
+    int __pu_err = 0;					\
+    typeof(*(ptr)) __pu_val = (x);			\
+    switch (sizeof (*(ptr))) {				\
+    case 1:						\
+	__put_user_asm(__pu_err, __pu_val, ptr, B);	\
+	break;						\
+    case 2:						\
+	__put_user_asm(__pu_err, __pu_val, ptr, W);	\
+	break;						\
+    case 4:						\
+	__put_user_asm(__pu_err, __pu_val, ptr,  );	\
+	break;						\
+    default:						\
+	__pu_err = __put_user_bad();			\
+	break;						\
+    }							\
+    __pu_err;						\
+})
+/*
+ * [pregs] = dregs  ==> 32bits
+ * H[pregs] = dregs  ==> 16bits
+ * B[pregs] = dregs  ==> 8 bits
+ */
+
+#define __put_user(x, ptr) put_user(x, ptr)
+
+static inline int bad_user_access_length(void)
+{
+	panic("bad_user_access_length");
+	return -1;
+}
+
+#define __put_user_bad() (bad_user_access_length(), (-EFAULT))
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define __put_user_asm(err,x,ptr,bhw)					\
+	__asm__ (#bhw"[%1] = %0;\n\t"					\
+		:	/* no outputs */				\
+		:"d" (x),"a" (__ptr(ptr)) : "memory")
+
+#define get_user(x, ptr)						\
+({									\
+	int __gu_err = 0;						\
+	typeof(*(ptr)) __gu_val = 0;					\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		__get_user_asm(__gu_err, __gu_val, ptr, B, "=d",(Z));	\
+		break;							\
+	case 2:								\
+		__get_user_asm(__gu_err, __gu_val, ptr, W, "=r",(Z));	\
+		break;							\
+	case 4:								\
+		__get_user_asm(__gu_err, __gu_val, ptr,  , "=r",);	\
+		break;							\
+	default:							\
+		__gu_val = 0;						\
+		__gu_err = __get_user_bad();				\
+		break;							\
+	}								\
+	(x) = __gu_val;							\
+	__gu_err;							\
+})
+
+/* dregs = [pregs] ==> 32bits
+ * H[pregs]   ==> 16bits
+ * B[pregs]   ==> 8 bits
+ */
+
+#define __get_user(x, ptr)	get_user(x, ptr)
+#define __get_user_bad()	(bad_user_access_length(), (-EFAULT))
+
+#define __get_user_asm(err,x,ptr,bhw,reg,option)		\
+	__asm__ ("%0 =" #bhw "[%1]"#option";\n\t"		\
+		: "=d" (x)					\
+		: "a" (__ptr(ptr)))
+
+#define copy_from_user(to, from, n)	(memcpy(to, from, n), 0)
+#define copy_to_user(to, from, n)	(memcpy(to, from, n), 0)
+
+#define __copy_from_user(to, from, n)	copy_from_user(to, from, n)
+#define __copy_to_user(to, from, n)	copy_to_user(to, from, n)
+
+#define copy_to_user_ret(to,from,n,retval)	({ if (copy_to_user(to,from,n)) return retval; })
+#define copy_from_user_ret(to,from,n,retval)	({ if (copy_from_user(to,from,n)) return retval; })
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+
+static inline long strncpy_from_user(char *dst, const char *src,
+				     long count)
+{
+	char *tmp;
+	strncpy(dst, src, count);
+	for (tmp = dst; *tmp && count > 0; tmp++, count--);
+	return (tmp - dst);	/* DAVIDM should we count a NUL ?  check getname */
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+static inline long strnlen_user(const char *src, long n)
+{
+	return (strlen(src) + 1);	/* DAVIDM make safer */
+}
+
+#define strlen_user(str) strnlen_user(str, 32767)
+
+/*
+ * Zero Userspace
+ */
+
+static inline unsigned long clear_user(void *to, unsigned long n)
+{
+	memset(to, 0, n);
+	return (0);
+}
+
+#endif
diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h
new file mode 100644
index 0000000..769f5a0
--- /dev/null
+++ b/include/asm-blackfin/virtconvert.h
@@ -0,0 +1,47 @@
+/*
+ * U-boot - virtconvert.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_VIRT_CONVERT__
+#define __BLACKFIN_VIRT_CONVERT__
+
+/*
+ * Macros used for converting between virtual and physical mappings.
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+#define mm_vtop(vaddr)		((unsigned long) vaddr)
+#define mm_ptov(vaddr)		((unsigned long) vaddr)
+#define phys_to_virt(vaddr)	((unsigned long) vaddr)
+#define virt_to_phys(vaddr)	((unsigned long) vaddr)
+
+#define virt_to_bus		virt_to_phys
+#define bus_to_virt		phys_to_virt
+
+#endif
+#endif
diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h
new file mode 100644
index 0000000..a52af4e
--- /dev/null
+++ b/include/configs/ezkit533.h
@@ -0,0 +1,188 @@
+#ifndef __CONFIG_EZKIT533_H__
+#define __CONFIG_EZKIT533_H__
+
+#define CFG_LONGHELP		1
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_STAMP		1
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20310300
+#if 0
+#define	CONFIG_MII
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_RTC_BF533	1
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz                            */
+#define CONFIG_CLKIN_HZ          27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
+/*                                                  1=CLKIN/2    */
+#define CONFIG_CLKIN_HALF               0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
+/*                                               1=bypass PLL    */
+#define CONFIG_PLL_BYPASS               0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
+/* Values can range from 1-64                                    */
+#define CONFIG_VCO_MULT			22
+/* CONFIG_CCLK_DIV controls what the core clock divider is       */
+/* Values can be 1, 2, 4, or 8 ONLY                              */
+#define CONFIG_CCLK_DIV			1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15                                    */
+#define CONFIG_SCLK_DIV			5
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ           ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ           (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ          CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ          CONFIG_CLKIN_HZ
+#endif
+
+#define CONFIG_MEM_SIZE                 32             /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH              9             /* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC16M16A2TG_75    1
+
+#define CONFIG_LOADS_ECHO	1
+
+
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL	| \
+					 CFG_CMD_PING	| \
+					 CFG_CMD_ELF	| \
+					 CFG_CMD_I2C	| \
+					 CFG_CMD_JFFS2	| \
+					 CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"	
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x01F00000	/* 1 ... 31 MB in DRAM */
+#define	CFG_LOAD_ADDR		0x01000000	/* default load address */
+#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x02000000
+#define CFG_FLASH_BASE		0x20000000
+
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE	0x4000
+#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CFG_FLASH0_BASE		0x20000000
+#define CFG_FLASH1_BASE		0x20200000
+#define CFG_FLASH2_BASE		0x20280000
+#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20020000
+#define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS  1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR                 11
+
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+
+#define POLL_MODE		1
+#define FLASH_TOT_SECT		40
+#define FLASH_SIZE		0x220000
+#define CFG_FLASH_SIZE		0x220000
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define	CONFIG_MISC_INIT_R
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL				PF0
+#define PF_SDA				PF1
+
+#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)			if(bit) { \
+							*pFIO_FLAG_S = PF_SDA; \
+							asm("ssync;"); \
+						} \
+					else    { \
+							*pFIO_FLAG_C = PF_SDA; \
+							asm("ssync;"); \
+						}
+#define I2C_SCL(bit)			if(bit) { \
+							*pFIO_FLAG_S = PF_SCL; \
+							asm("ssync;"); \
+						} \
+					else    { \
+							*pFIO_FLAG_C = PF_SCL; \
+							asm("ssync;"); \
+						}
+#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED			50000
+#define CFG_I2C_SLAVE			0xFE
+
+
+#define __ADSPLPBLACKFIN__	1
+#define __ADSPBF533__		1
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL              (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |    \
+                                ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL              (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |   \
+                                B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+#define AMGCTLVAL               0xFF
+#define AMBCTL0VAL              0x7BB07BB0
+#define AMBCTL1VAL              0xFFC27BB0
+
+#define CONFIG_VDSP		1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP		0x8
+#define SHT_STRTAB_VDSP		0x1
+#define ELFSHDRSIZE_VDSP	0x2C
+#define VDSP_ENTRY_ADDR		0xFFA00000
+#endif
+
+#endif
diff --git a/include/configs/stamp.h b/include/configs/stamp.h
new file mode 100644
index 0000000..1402a41
--- /dev/null
+++ b/include/configs/stamp.h
@@ -0,0 +1,340 @@
+/*
+ * U-boot - stamp.h  Configuration file for STAMP board
+ *			having BF533 processor
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_STAMP_H__
+#define __CONFIG_STAMP_H__
+
+/*
+ * Board settings
+ *
+ */
+
+#define __ADSPLPBLACKFIN__		1
+#define __ADSPBF533__			1
+#define CONFIG_STAMP			1
+#define CONFIG_RTC_BF533		1
+
+/* FLASH/ETHERNET uses the same address range */
+#define SHARED_RESOURCES 		1
+
+#define CONFIG_VDSP			1
+
+/*
+ * Clock settings
+ *
+ */
+
+/* CONFIG_CLKIN_HZ is any value in Hz                            */
+#define CONFIG_CLKIN_HZ			11059200
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
+/*                                                  1=CLKIN/2    */
+#define CONFIG_CLKIN_HALF		0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
+/*                                               1=bypass PLL    */
+#define CONFIG_PLL_BYPASS       	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
+/* Values can range from 1-64                                    */
+#define CONFIG_VCO_MULT			45
+/* CONFIG_CCLK_DIV controls what the core clock divider is       */
+/* Values can be 1, 2, 4, or 8 ONLY                              */
+#define CONFIG_CCLK_DIV			1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15                                    */
+#define CONFIG_SCLK_DIV			6
+
+/*
+ * Network Settings
+ */
+/* network support */
+#define CONFIG_IPADDR           192.168.0.15
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_GATEWAYIP        192.168.0.1
+#define CONFIG_SERVERIP         192.168.0.2
+#define CONFIG_HOSTNAME         STAMP
+#define CONFIG_ROOTPATH			/checkout/uClinux-dist/romfs
+
+/* To remove hardcoding and enable MAC storage in EEPROM  */
+/* #define CONFIG_ETHADDR               02:80:ad:20:31:b8 */
+
+/*
+ * Command settings
+ *
+ */
+
+#define CFG_LONGHELP			1
+
+#define CONFIG_BOOTDELAY		5
+#define CONFIG_BOOT_RETRY_TIME		-1	/* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND 		"run ramboot"
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
+
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL	| \
+					 CFG_CMD_PING	| \
+					 CFG_CMD_ELF	| \
+					 CFG_CMD_I2C	| \
+					 CFG_CMD_CACHE	| \
+					 CFG_CMD_JFFS2  | \
+					 CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"	
+
+#define CONFIG_EXTRA_ENV_SETTINGS												\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "									\
+	"nfsroot=$(serverip):$(rootpath)\0"											\
+	"addip=setenv bootargs $(bootargs) "										\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"							\
+	":$(hostname):eth0:off\0"													\
+    "ramboot=tftpboot 0x1000000 linux;"											\
+	"run ramargs;run addip;bootelf\0"											\
+	"nfsboot=tftpboot 0x1000000 linux;"											\
+	"run nfsargs;run addip;bootelf\0"											\
+	"flashboot=bootm 0x20100000\0"												\
+	""
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Console settings
+ *
+ */
+
+#define CONFIG_BAUDRATE			57600
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_PROMPT			"stamp>"	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE			1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE			256	/* Console I/O Buffer Size */
+#endif
+#define	CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define	CFG_MAXARGS			16	/* max number of command args */
+#define CFG_BARGSIZE			CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_LOADS_ECHO		1
+
+/*
+ * Network settings
+ *
+ */
+
+#define CONFIG_DRIVER_SMC91111		1
+#define CONFIG_SMC91111_BASE		0x20300300
+/* To remove hardcoding and enable MAC storage in EEPROM */
+/* #define HARDCODE_MAC			1 */
+
+/*
+ * Flash settings
+ *
+ */
+
+#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define	CFG_FLASH_CFI_AMD_RESET
+
+#define CFG_ENV_IS_IN_FLASH		1
+
+#define CFG_FLASH_BASE			0x20000000
+#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT		67		/* max number of sectors on one chip */
+
+#define CFG_ENV_ADDR			0x20020000
+#define	CFG_ENV_SIZE			0x10000
+#define CFG_ENV_SECT_SIZE 		0x10000	/* Total Size of Environment Sector */
+
+#define CFG_FLASH_ERASE_TOUT		30000	/* Timeout for Chip Erase (in ms) */
+#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT		1	/* Timeout for Flash Write (in ms) */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS  1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 		11
+
+/* 
+ * following timeouts shall be used once the 
+ * Flash real protection is enabled
+ */
+#define CFG_FLASH_LOCK_TOUT		5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT		10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL				PF3
+#define PF_SDA				PF2
+
+#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)			if(bit) { \
+							*pFIO_FLAG_S = PF_SDA; \
+							asm("ssync;"); \
+						} \
+					else    { \
+							*pFIO_FLAG_C = PF_SDA; \
+							asm("ssync;"); \
+						}
+#define I2C_SCL(bit)			if(bit) { \
+							*pFIO_FLAG_S = PF_SCL; \
+							asm("ssync;"); \
+						} \
+					else    { \
+							*pFIO_FLAG_C = PF_SCL; \
+							asm("ssync;"); \
+						}
+#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED			50000
+#define CFG_I2C_SLAVE			0xFE
+
+/*
+ * Compact Flash settings
+ */
+
+/* Enabled below option for CF support */
+/* #define CONFIG_STAMP_CF		1 */
+
+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+
+#define CONFIG_MISC_INIT_R		1
+#define CONFIG_DOS_PARTITION		1
+
+/*
+ * IDE/ATA stuff
+ */
+#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED			/* no led for ide supported */
+#undef  CONFIG_IDE_RESET		/* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS	1		/* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE		(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR		0x20200000
+#define CFG_ATA_IDE0_OFFSET		0x0000
+
+#define CFG_ATA_DATA_OFFSET		0x0020  /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET		0x0020  /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET		0x0007  /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE			2
+#endif
+
+/*
+ * SDRAM settings
+ *
+ */
+
+#define CONFIG_MEM_SIZE			128             /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH     	11             /* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC64M4A2FB_7E	1
+
+#define CFG_MEMTEST_START		0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END			0x07EFFFFF	/* 1 ... 127 MB in DRAM */
+#define	CFG_LOAD_ADDR			0x01000000	/* default load address */
+
+#define	CFG_SDRAM_BASE			0x00000000
+#define CFG_MAX_RAM_SIZE		0x08000000
+
+#define	CFG_MONITOR_LEN			(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+
+
+
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ			( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ			(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ			( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ			( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ			CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ			CONFIG_CLKIN_HZ
+#endif
+
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_HZ				1000		/* 1ms time tick */ 
+
+#define	CFG_MALLOC_LEN			(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_BASE			(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE		0x4000
+#define CFG_GBL_DATA_ADDR		(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE		(CFG_GBL_DATA_ADDR  - 4)
+
+#define CFG_LARGE_IMAGE_LEN	0x4000000	/* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SHOW_BOOT_PROGRESS	1	/* Show boot progress on LEDs */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE        	(128*1024)      /* regular stack */
+
+
+/*
+ * FLASH organization and environment definitions
+ */
+#define	CFG_BOOTMAPSZ			(8 << 20)	/* Initial Memory map for Linux */
+
+/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
+/*#define AMGCTLVAL             (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL              (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |    \
+                                B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL              (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |      \
+                                B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+*/
+#define AMGCTLVAL               0xFF
+#define AMBCTL0VAL              0xBBC3BBC3
+#define AMBCTL1VAL              0x99B39983
+#define CF_AMBCTL1VAL           0x99B3ffc2
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP		0x8
+#define SHT_STRTAB_VDSP		0x1
+#define ELFSHDRSIZE_VDSP	0x2C
+#define VDSP_ENTRY_ADDR		0xFFA00000
+#endif
+
+
+#endif
diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile
new file mode 100644
index 0000000..bc280d0
--- /dev/null
+++ b/lib_blackfin/Makefile
@@ -0,0 +1,47 @@
+#
+# U-boot Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(ARCH).a
+
+AOBJS	=
+
+COBJS	= board.o bf533_linux.o bf533_string.o cache.o muldi3.o
+OBJS	= $(AOBJS) $(COBJS)
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c
new file mode 100644
index 0000000..6f29795
--- /dev/null
+++ b/lib_blackfin/bf533_linux.c
@@ -0,0 +1,91 @@
+/*
+ * U-boot - bf533_linux.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Dummy functions, currently not in Use */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <zlib.h>
+#include <asm/byteorder.h>
+
+#define	LINUX_MAX_ENVS		256
+#define	LINUX_MAX_ARGS		256
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
+#else
+#define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+#define CMD_LINE_ADDR 0xFF900000  /* L1 scratchpad */
+
+#ifdef SHARED_RESOURCES
+        extern void swap_to(int device_id);
+#endif
+
+static char *make_command_line(void);
+
+extern image_header_t header;
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
+		    ulong addr, ulong * len_ptr, int verify)
+{
+	int (*appl)(char *cmdline);
+	char *cmdline;
+
+#ifdef SHARED_RESOURCES
+	swap_to(FLASH);
+#endif
+
+	appl = (int (*)(char *))ntohl(header.ih_ep);
+	printf("Starting Kernel at = %x\n", appl);
+	cmdline = make_command_line();
+	if(icache_status()){
+		flush_instruction_cache();
+		icache_disable();
+		}
+	if(dcache_status()){
+		flush_data_cache();
+		dcache_disable();
+		}
+	(*appl)(cmdline);
+}
+
+char *make_command_line(void)
+{
+    char *dest = (char *) CMD_LINE_ADDR;
+    char *bootargs;
+
+    if ( (bootargs = getenv("bootargs")) == NULL )
+	return NULL;
+
+    strncpy(dest, bootargs, 0x1000);
+    dest[0xfff] = 0;
+    return dest;
+}
diff --git a/lib_blackfin/bf533_string.c b/lib_blackfin/bf533_string.c
new file mode 100644
index 0000000..cfa515a
--- /dev/null
+++ b/lib_blackfin/bf533_string.c
@@ -0,0 +1,185 @@
+/*
+ * U-boot - bf533_string.c Contains library routines.
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/cpu/defBF533.h>
+
+void *dma_memcpy(void *,const void *,size_t);
+
+char *strcpy(char *dest, const char *src)
+{
+	char *xdest = dest;
+	char temp = 0;
+
+	__asm__ __volatile__
+		("1:\t%2 = B [%1++] (Z);\n\t"
+		"B [%0++] = %2;\n\t"
+		"CC = %2;\n\t"
+		"if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
+		:"0"(dest), "1"(src), "2"(temp):"memory");
+
+	return xdest;
+}
+
+char *strncpy(char *dest, const char *src, size_t n)
+{
+	char *xdest = dest;
+	char temp = 0;
+
+	if (n == 0)
+		return xdest;
+
+	__asm__ __volatile__
+		("1:\t%3 = B [%1++] (Z);\n\t"
+		"B [%0++] = %3;\n\t"
+		"CC = %3;\n\t"
+		"if ! cc jump 2f;\n\t"
+		"%2 += -1;\n\t"
+		"CC = %2 == 0;\n\t"
+		"if ! cc jump 1b (bp);\n"
+		"2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
+		:"0"(dest), "1"(src), "2"(n), "3"(temp)
+		:"memory");
+
+	return xdest;
+}
+
+int strcmp(const char *cs, const char *ct)
+{
+	char __res1, __res2;
+
+	__asm__
+		("1:\t%2 = B[%0++] (Z);\n\t"	/* get *cs */
+		"%3 = B[%1++] (Z);\n\t"		/* get *ct */
+		"CC = %2 == %3;\n\t"		/* compare a byte */
+		"if ! cc jump 2f;\n\t"		/* not equal, break out */
+		"CC = %2;\n\t"			/* at end of cs? */
+		"if cc jump 1b (bp);\n\t"	/* no, keep going */
+		"jump.s 3f;\n"			/* strings are equal */
+		"2:\t%2 = %2 - %3;\n"		/* *cs - *ct */
+		"3:\n":	"=a"(cs), "=a"(ct), "=d"(__res1),
+		"=d"(__res2)
+		: "0"(cs), "1"(ct));
+
+	return __res1;
+}
+
+int strncmp(const char *cs, const char *ct, size_t count)
+{
+	char __res1, __res2;
+
+	if (!count)
+		return 0;
+
+	__asm__
+		("1:\t%3 = B[%0++] (Z);\n\t"	/* get *cs */
+		"%4 = B[%1++] (Z);\n\t"		/* get *ct */
+		"CC = %3 == %4;\n\t"		/* compare a byte */
+		"if ! cc jump 3f;\n\t"		/* not equal, break out */
+		"CC = %3;\n\t"			/* at end of cs? */
+		"if ! cc jump 4f;\n\t"		/* yes, all done */
+		"%2 += -1;\n\t"			/* no, adjust count */
+		"CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"	/* more to do, keep going */
+		"2:\t%3 = 0;\n\t"		/* strings are equal */
+		"jump.s    4f;\n" "3:\t%3 = %3 - %4;\n"	/* *cs - *ct */
+ 		"4:":	"=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
+		"=d"(__res2)
+		: "0"(cs), "1"(ct), "2"(count));
+
+	return __res1;
+}
+
+/*
+ * memcpy - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * You should not use this function to access IO space, use memcpy_toio()
+ * or memcpy_fromio() instead.
+ */
+void * memcpy(void * dest,const void *src,size_t count)
+{
+	char *tmp = (char *) dest, *s = (char *) src;
+	
+/* Turn off the cache, if destination in the L1 memory */
+	if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
+		|| (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
+	    || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
+			if(icache_status()){
+					blackfin_icache_flush_range(src, src+count);
+					icache_disable();
+			}
+			if(dcache_status()){
+					blackfin_dcache_flush_range(src, src+count);
+					dcache_disable();
+			}
+			dma_memcpy(dest,src,count);
+	}else{
+		while(count--)
+			*tmp++ = *s++;
+	}
+	return dest;
+}
+
+void *dma_memcpy(void * dest,const void *src,size_t count)
+{
+	
+		*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
+
+		/* Copy sram functions from sdram to sram */
+		/* Setup destination start address */
+		*pMDMA_D0_START_ADDR = (volatile void **)dest;
+		/* Setup destination xcount */
+		*pMDMA_D0_X_COUNT = count ;
+		/* Setup destination xmodify */
+		*pMDMA_D0_X_MODIFY = 1;
+
+		/* Setup Source start address */
+		*pMDMA_S0_START_ADDR = (volatile void **)src;
+		/* Setup Source xcount */
+		*pMDMA_S0_X_COUNT = count;
+		/* Setup Source xmodify */
+		*pMDMA_S0_X_MODIFY = 1;
+
+		/* Enable source DMA */
+		*pMDMA_S0_CONFIG = (DMAEN);
+		asm("ssync;");
+
+		*pMDMA_D0_CONFIG = ( WNR | DMAEN);
+		
+		while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){
+			*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+		}
+		*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+
+		dest += count;
+		src  += count;
+		return dest;
+}
diff --git a/lib_blackfin/blackfin_board.h b/lib_blackfin/blackfin_board.h
new file mode 100644
index 0000000..35a513f
--- /dev/null
+++ b/lib_blackfin/blackfin_board.h
@@ -0,0 +1,62 @@
+/*
+ * U-boot - blackfin_board.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_BOARD_H__
+#define __BLACKFIN_BOARD_H__
+
+extern void timer_init(void);
+extern void init_IRQ(void);
+extern void rtc_init(void);
+
+extern ulong uboot_end_data;
+extern ulong uboot_end;
+
+ulong monitor_flash_len;
+
+
+#define VERSION_STRING_SIZE  150 /* including 40 bytes buffer to change any string */ 
+#define VERSION_STRING_FORMAT "%s (%s - %s)\n"
+#define VERSION_STRING		U_BOOT_VERSION, __DATE__, __TIME__
+
+char version_string[VERSION_STRING_SIZE];
+
+int *g_addr;
+static ulong mem_malloc_start;
+static ulong mem_malloc_end;
+static ulong mem_malloc_brk;
+extern char _sram_in_sdram_start[];
+extern char _sram_inst_size[];
+#ifdef DEBUG
+static void display_global_data(void);
+#endif
+
+/* definitions used to check the SMC card availability */
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+#define UPPER_BYTE_MASK	0xFF00
+#define SMC_IDENT	0x3300
+
+#endif
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
new file mode 100644
index 0000000..7bf63eb
--- /dev/null
+++ b/lib_blackfin/board.c
@@ -0,0 +1,282 @@
+/*
+ * U-boot - board.c First C file to be called contains init routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+#include <environment.h>
+#include "blackfin_board.h"
+#include "../drivers/smc91111.h"
+
+extern flash_info_t flash_info[];
+
+
+static void mem_malloc_init(void)
+{
+	mem_malloc_start = CFG_MALLOC_BASE;
+	mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
+	mem_malloc_brk = mem_malloc_start;
+	memset((void *) mem_malloc_start, 0,
+	mem_malloc_end - mem_malloc_start);
+}
+
+void *sbrk(ptrdiff_t increment)
+{
+	ulong old = mem_malloc_brk;
+	ulong new = old + increment;
+
+	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
+		return (NULL);
+	}
+	mem_malloc_brk = new;
+
+	return ((void *) old);
+}
+
+static int display_banner(void)
+{
+	sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING);
+	printf("%s\n", version_string);
+	return (0);
+}
+
+static void display_flash_config(ulong size)
+{
+	puts("FLASH:  ");
+	print_size(size, "\n");
+	return;
+}
+
+static int init_baudrate(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uchar tmp[64];
+	int i = getenv_r("baudrate", tmp, sizeof(tmp));
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+		? (int) simple_strtoul(tmp, NULL, 10)
+		: CONFIG_BAUDRATE;
+	return (0);
+}
+
+#ifdef DEBUG
+static void display_global_data(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd;
+	bd = gd->bd;
+	printf("--flags:%x\n", gd->flags);
+	printf("--board_type:%x\n", gd->board_type);
+	printf("--baudrate:%x\n", gd->baudrate);
+	printf("--have_console:%x\n", gd->have_console);
+	printf("--ram_size:%x\n", gd->ram_size);
+	printf("--reloc_off:%x\n", gd->reloc_off);
+	printf("--env_addr:%x\n", gd->env_addr);
+	printf("--env_valid:%x\n", gd->env_valid);
+	printf("--bd:%x %x\n", gd->bd, bd);
+	printf("---bi_baudrate:%x\n", bd->bi_baudrate);
+	printf("---bi_ip_addr:%x\n", bd->bi_ip_addr);
+	printf("---bi_enetaddr:%x %x %x %x %x %x\n",
+				bd->bi_enetaddr[0],
+				bd->bi_enetaddr[1],
+				bd->bi_enetaddr[2],
+				bd->bi_enetaddr[3],
+				bd->bi_enetaddr[4],
+				bd->bi_enetaddr[5]);
+	printf("---bi_arch_number:%x\n", bd->bi_arch_number);
+	printf("---bi_boot_params:%x\n", bd->bi_boot_params);
+	printf("---bi_memstart:%x\n", bd->bi_memstart);
+	printf("---bi_memsize:%x\n", bd->bi_memsize);
+	printf("---bi_flashstart:%x\n", bd->bi_flashstart);
+	printf("---bi_flashsize:%x\n", bd->bi_flashsize);
+	printf("---bi_flashoffset:%x\n", bd->bi_flashoffset);
+	printf("--jt:%x *:%x\n", gd->jt, *(gd->jt));
+}
+#endif
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependend #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+
+void board_init_f(ulong bootflag)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong addr;
+	bd_t *bd;
+
+	gd = (gd_t *) (CFG_GBL_DATA_ADDR);
+	memset((void *) gd, 0, sizeof(gd_t));
+
+	/* Board data initialization */
+	addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t));
+
+	/* Align to 4 byte boundary */
+        addr &= ~(4 - 1);
+	bd = (bd_t*)addr;
+	gd->bd = bd;
+	memset((void *) bd, 0, sizeof(bd_t));
+
+	/* Initialize */
+	init_IRQ();
+	env_init();		/* initialize environment */
+	init_baudrate();	/* initialze baudrate settings */
+	serial_init();		/* serial communications setup */
+	console_init_f();
+	display_banner();	/* say that we are here */
+	checkboard();
+#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+	rtc_init();
+#endif
+	timer_init();
+	printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \
+	CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000);
+	printf("SDRAM: ");
+	print_size(initdram(0), "\n");
+	board_init_r((gd_t *) gd, 0x20000010);
+}
+
+void board_init_r(gd_t * id, ulong dest_addr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong size;
+	extern void malloc_bin_reloc(void);
+	char *s, *e;
+	bd_t *bd;
+	int i;
+	gd = id;
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+	bd = gd->bd;
+
+#if	CONFIG_STAMP
+	/* There are some other pointer constants we must deal with */
+	/* configure available FLASH banks */
+	size = flash_init();
+	display_flash_config(size);
+	flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
+	bd->bi_flashstart = CFG_FLASH_BASE;
+	bd->bi_flashsize = size;
+	bd->bi_flashoffset = 0;
+#else
+	bd->bi_flashstart = 0;
+	bd->bi_flashsize = 0;
+	bd->bi_flashoffset = 0;
+#endif
+	/* initialize malloc() area */
+	mem_malloc_init();
+	malloc_bin_reloc();
+
+	/* relocate environment function pointers etc. */
+	env_relocate();
+
+	/* board MAC address */
+	s = getenv("ethaddr");
+	for (i = 0; i < 6; ++i) {
+		bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+
+	/* IP Address */
+	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	/* Initialize devices */
+	devices_init();
+	jumptable_init();
+
+	/* Initialize the console (after the relocation and devices init) */
+	console_init_r();
+
+	/* Initialize from environment */
+	if ((s = getenv("loadaddr")) != NULL) {
+		load_addr = simple_strtoul(s, NULL, 16);
+	}
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	if ((s = getenv("bootfile")) != NULL) {
+		copy_filename(BootFile, s, sizeof(BootFile));
+	}
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#ifdef CONFIG_DRIVER_SMC91111
+#ifdef SHARED_RESOURCES
+	/* Switch to Ethernet */
+	swap_to(ETHERNET);
+#endif
+	if  ( (SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT ) {
+		printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS);
+	} else {
+		printf("Net:   SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
+	}
+
+#ifdef SHARED_RESOURCES
+	swap_to(FLASH);
+#endif
+#endif
+#ifdef CONFIG_SOFT_I2C
+	init_func_i2c();
+#endif
+
+#ifdef DEBUG
+	display_global_data(void);
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;) {
+		main_loop();
+	}
+}
+
+#ifdef CONFIG_SOFT_I2C
+static int init_func_i2c (void)
+{
+	puts ("I2C:   ");
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	puts ("ready\n");
+	return (0);
+}
+#endif
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;);
+}
diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
new file mode 100644
index 0000000..4213b86
--- /dev/null
+++ b/lib_blackfin/cache.c
@@ -0,0 +1,41 @@
+/*
+ * U-boot - cache.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* for now: just dummy functions to satisfy the linker */
+extern void blackfin_icache_range(unsigned long *,unsigned long *);
+extern void blackfin_dcache_range(unsigned long *,unsigned long *);
+void flush_cache(unsigned long dummy1, unsigned long dummy2)
+{
+	if(icache_status()){
+		blackfin_icache_flush_range(dummy1,dummy1+dummy2);
+		}
+	if(dcache_status()){
+		blackfin_dcache_flush_range(dummy1,dummy1+dummy2);
+		}
+	return;
+}
+
diff --git a/lib_blackfin/muldi3.c b/lib_blackfin/muldi3.c
new file mode 100644
index 0000000..a562242
--- /dev/null
+++ b/lib_blackfin/muldi3.c
@@ -0,0 +1,92 @@
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+do {									\
+	USItype __x0, __x1, __x2, __x3;					\
+	USItype __ul, __vl, __uh, __vh;					\
+									\
+	__ul = __ll_lowpart (u);					\
+	__uh = __ll_highpart (u);					\
+	__vl = __ll_lowpart (v);					\
+	__vh = __ll_highpart (v);					\
+									\
+	__x0 = (USItype) __ul * __vl;					\
+	__x1 = (USItype) __ul * __vh;					\
+	__x2 = (USItype) __uh * __vl;					\
+	__x3 = (USItype) __uh * __vh;					\
+									\
+	__x1 += __ll_highpart (__x0);/* this can't give carry */	\
+	__x1 += __x2;	/* but this indeed can */			\
+	if (__x1 < __x2)	/* did we get it? */			\
+		__x3 += __ll_B;	/* yes, add it in the proper pos. */	\
+									\
+	(w1) = __x3 + __ll_highpart (__x1);				\
+	(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);	\
+} while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v)						\
+	({DIunion __w;							\
+	umul_ppmm (__w.s.high, __w.s.low, u, v);			\
+	__w.ll; })
+#endif
+
+typedef unsigned int USItype    __attribute__ ((mode (SI)));
+typedef int SItype     __attribute__ ((mode (SI)));
+typedef int DItype     __attribute__ ((mode (DI)));
+typedef	int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype low, high;};
+typedef union
+{
+	struct DIstruct s;
+	DItype ll;
+} DIunion;
+
+DItype __muldi3 (DItype u, DItype v)
+{
+	DIunion w;
+	DIunion uu, vv;
+ 
+	uu.ll = u,
+	vv.ll = v;
+	/*  panic("kernel panic for __muldi3"); */
+	w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+	+ (USItype) uu.s.high * (USItype) vv.s.low);
+ 
+	return w.ll;
+}
diff --git a/rtc/bf533_rtc.c b/rtc/bf533_rtc.c
new file mode 100644
index 0000000..09b8f21
--- /dev/null
+++ b/rtc/bf533_rtc.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux 
+ *
+ * Copyright (C) 2003 Motorola Corporation.  All rights reserved.
+ * 				Richard Xiao (A2590C@email.mot.com)
+ *
+ * Copyright (C) 1996 Paul Gortmaker
+ *
+ *
+ *	Based on other minimal char device drivers, like Alan's
+ *	watchdog, Ted's random, etc. etc.
+ *
+ *	1.07	Paul Gortmaker.
+ *	1.08	Miquel van Smoorenburg: disallow certain things on the
+ *		DEC Alpha as the CMOS clock is also used for other things.
+ *	1.09	Nikita Schmidt: epoch support and some Alpha cleanup.
+ *	1.09a	Pete Zaitcev: Sun SPARC
+ *	1.09b	Jeff Garzik: Modularize, init cleanup
+ *	1.09c	Jeff Garzik: SMP cleanup
+ *	1.10    Paul Barton-Davis: add support for async I/O
+ *	1.10a	Andrea Arcangeli: Alpha updates
+ *	1.10b	Andrew Morton: SMP lock fix
+ *	1.10c	Cesar Barros: SMP locking fixes and cleanup
+ *	1.10d	Paul Gortmaker: delete paranoia check in rtc_exit
+ *	1.10e   LG Soft India: Register access is different in BF533. 	
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#include <asm/blackfin.h>
+#include <asm/cpu/bf533_rtc.h>
+
+void rtc_reset(void)
+{
+	return;			/* nothing to do */
+}
+
+/* Wait for pending writes to complete */
+void wait_for_complete(void)
+{
+	while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) {
+		printf("");
+	}
+	*(volatile unsigned short *) RTC_ISTAT = 0x8000;
+}
+
+/* Enable the RTC prescaler enable register */
+void rtc_init()
+{
+	*(volatile unsigned short *) RTC_PREN = 0x1;
+	wait_for_complete();
+}
+
+/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers 
+ * based on this value.
+ */
+void rtc_set (struct rtc_time *tmp)
+{
+	unsigned long n_days_1970 = 0;
+	unsigned long n_secs_rem  = 0;
+	unsigned long n_hrs	  = 0;
+	unsigned long n_mins	  = 0;
+	unsigned long n_secs	  = 0;
+	unsigned long time_in_secs;
+
+	if(tmp == NULL) {
+		printf("Error setting the date/time \n");
+		return;
+	}
+
+	time_in_secs = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	/* Compute no. of days since 1970 */
+	n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY));
+
+	/* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
+	n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY));
+	n_hrs 	= n_secs_rem / (NUM_SECS_IN_HOUR);
+	n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
+	n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
+	n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
+	
+	/* Store the new time in the RTC_STAT register */
+	*(volatile unsigned long *) RTC_STAT =
+		((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
+		(n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
+
+	wait_for_complete();
+}
+
+/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
+void rtc_get (struct rtc_time *tmp)
+{
+	unsigned long cur_rtc_stat = 0;
+	unsigned long time_in_sec;
+	unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0; 
+
+	if(tmp == NULL) {
+		printf("Error getting the date/time \n");
+		return;
+	}
+
+	/* Read the RTC_STAT register */
+	cur_rtc_stat = *(volatile unsigned long *) RTC_STAT;
+	
+	/* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */
+	tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f;
+	tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f;
+	tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f;
+	tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff;
+
+	/* Calculate the total number of seconds since Jan 1970 */
+	time_in_sec 	= 	(tm_sec) + 
+					MIN_TO_SECS(tm_min) + 
+						HRS_TO_SECS(tm_hour) + 
+							DAYS_TO_SECS(tm_day);
+	to_tm(time_in_sec,tmp);	
+}
+#endif	/* CONFIG_RTC_BF533 && CFG_CMD_DATE */