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| author | Ed Swarthout <ed.swarthout@freescale.com> | 2006-12-07 10:34:14 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-03-22 11:02:34 -0500 |
| commit | 2ccceacc04b009d923afb7c26189ba2f8a2a5d46 (patch) | |
| tree | c001af651649cf4aed537d41bccdea98c9f2de76 | |
| parent | aea17f99278818caa327ad0e511b48d1761fb10c (diff) | |
| download | u-boot-imx-2ccceacc04b009d923afb7c26189ba2f8a2a5d46.zip u-boot-imx-2ccceacc04b009d923afb7c26189ba2f8a2a5d46.tar.gz u-boot-imx-2ccceacc04b009d923afb7c26189ba2f8a2a5d46.tar.bz2 | |
Add support for 8641 Rev 2 silicon.
Without this patch, I am unable to get to the prompt on rev 2 silicon.
Only set ddrioovcr for rev1.
Signed-off-by: Ed Swarthout<ed.swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
| -rw-r--r-- | cpu/mpc86xx/spd_sdram.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index b18e822..ac9ff81 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -284,9 +284,9 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. Rev1 only */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { gur->ddrioovcr = (0 | 0x80000000 /* Enable */ | 0x10000000 /* VSEL to 1.8V */ |