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| author | Timur Tabi <timur@freescale.com> | 2008-04-04 11:15:58 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-04-18 17:43:09 -0500 |
| commit | 88353a985109562a639b2f8a0c90d77011bfe374 (patch) | |
| tree | a6c7c35746ed291c3a003eed91c2525619e03266 | |
| parent | 5e3dca577b7c1bf58bd2b48449b18b7e7dcd8e04 (diff) | |
| download | u-boot-imx-88353a985109562a639b2f8a0c90d77011bfe374.zip u-boot-imx-88353a985109562a639b2f8a0c90d77011bfe374.tar.gz u-boot-imx-88353a985109562a639b2f8a0c90d77011bfe374.tar.bz2 | |
Fix calculation of I2C clock for some 85xx chips
Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and
some use CCB/3. There is no pattern that can be used to determine which
chips use which frequency, so the only way to determine is to look up the
actual SOC designation and use the right value for that SOC.
Update immap_85xx.h to include the GUTS PORDEVSR2 register.
Signed-off-by: Timur Tabi <timur@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/speed.c | 31 | ||||
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 4 |
2 files changed, 33 insertions, 2 deletions
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index d90d397..699441b4 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -65,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo) int get_clocks (void) { sys_info_t sys_info; +#ifdef CONFIG_MPC8544 + volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR; +#endif #if defined(CONFIG_CPM2) volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint sccr, dfbrg; @@ -78,8 +81,34 @@ int get_clocks (void) gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; gd->mem_clk = sys_info.freqDDRBus; + + /* + * The base clock for I2C depends on the actual SOC. Unfortunately, + * there is no pattern that can be used to determine the frequency, so + * the only choice is to look up the actual SOC number and use the value + * for that SOC. This information is taken from application note + * AN2919. + */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) gd->i2c1_clk = sys_info.freqSystemBus; - gd->i2c2_clk = sys_info.freqSystemBus; +#elif defined(CONFIG_MPC8544) + /* + * On the 8544, the I2C clock is the same as the SEC clock. This can be + * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See + * 4.4.3.3 of the 8544 RM. Note that this might actually work for all + * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the + * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. + */ + if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) + gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#else + /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#endif + gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 01cb2d7..dc6e278 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1570,7 +1570,9 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - char res1[12]; + uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 + char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; uint gpiocr; /* 0xe0030 - GPIO control register */ |