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| author | Alejandro Sierra <b18039@freescale.com> | 2012-08-15 11:04:52 -0500 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2012-08-20 15:24:00 +0800 |
| commit | 82f13452791cf4077e2f88adf347f61cffc3afc5 (patch) | |
| tree | 80bb08882c6ecd0d0dbfa2c0ed21b175ad08ad3e | |
| parent | dedfb0b085e54f284d86d632974ab43e699a4efd (diff) | |
| download | u-boot-imx-82f13452791cf4077e2f88adf347f61cffc3afc5.zip u-boot-imx-82f13452791cf4077e2f88adf347f61cffc3afc5.tar.gz u-boot-imx-82f13452791cf4077e2f88adf347f61cffc3afc5.tar.bz2 | |
ENGR00220486 Modify ODT values for Solo AI
Modify ODT values for Solo AI. Some Solo boards did not passed the "mtest"
from uboot using the previous configuration.
Old configuration:
MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
New configuration:
MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index 6977691..498e147 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -148,8 +148,8 @@ MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031) MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030) MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) -MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) -MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) +MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) +MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d) MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x004, 0x00011006) MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) @@ -411,8 +411,8 @@ MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030) MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003) MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) -MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) -MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) +MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) +MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) /* Calibration values based on ARD and 528MHz */ MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0358) |