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authorMinghuan Lian <Minghuan.Lian@freescale.com>2015-03-27 13:24:39 +0800
committerYork Sun <yorksun@freescale.com>2015-05-04 09:24:23 -0700
commit1d0b59a9b049443397f484ad03b88c6314bc7ebb (patch)
tree3aa8fc04de6bfd03c81ee07ee443bec9be07995d /.mailmap
parent5066e62847bddf6030262ade2aa3e7bcdc930037 (diff)
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fsl/pci: Set CFG_READY for PCIe v3.0 and later
Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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