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  1. 05 Feb, 2019 1 commit
  3. 24 Jan, 2019 1 commit
  5. 23 Nov, 2018 1 commit
  7. 31 Oct, 2018 1 commit
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  11. 20 Sep, 2018 1 commit
    • IGEP0046DL/Q Boot Algorithm: · e202c713
      Jose Miquel Sanabria authored 
      Added video args for kernel support when trying to use a display
Changed a bit the boot algorith so that bootdir is by default empty and mmcpart is by default 1
this will change when booting a firmware because uEnv.txt is now responsible for indicating that zimage
and dtb are in p2 (mmcpart=2) of folder /boot/ (bootdir)
Signed-off-by: Jose Miquel Sanabria's avatarJose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
  13. 24 Jul, 2018 1 commit
  15. 23 Jul, 2018 2 commits
  17. 16 Jul, 2018 1 commit
  19. 06 Jul, 2018 1 commit
  21. 05 Jul, 2018 1 commit
  23. 28 Jun, 2018 1 commit
  25. 19 Jun, 2018 1 commit
  27. 12 Jun, 2018 2 commits
  29. 24 May, 2018 1 commit
  31. 09 May, 2018 1 commit
  33. 15 Feb, 2018 1 commit
  35. 07 Feb, 2018 1 commit
  37. 05 Feb, 2018 1 commit
  39. 26 Jan, 2018 4 commits
  41. 23 Jan, 2018 2 commits
  43. 15 Jan, 2018 1 commit
  45. 12 Jan, 2018 1 commit
  47. 14 Sep, 2017 1 commit
  49. 07 Sep, 2017 1 commit
    • MA-9554[Android_6DL_SD]RTC: Sometimes the RTC reset to the initial time 1970… · c250b072
      Zhang Bo authored 
      MA-9554[Android_6DL_SD]RTC: Sometimes the RTC reset to the initial time 1970 after softare reboot the first time. 40%

RTC timer is default disabled after power off and bootup again. it will be
enabled in kernel rtc driver init. But rtc time is shorter than system clock,
so rtc time cannot update to system clock in rtc_hctosys(), and the sysfs
file /sys/class/rtc/rtc0/hctosys cat result is 0. Android AlarmManagerService
cannot work normally when hctosys is 0.
Enable RTC in u-boot so the time in RTC timer is longer than system clock.

Change-Id: Ie8b1c1b36e5ab48031efe44dd06468ac35ca3d3b
Signed-off-by: 's avatarZhang Bo <bo.zhang@nxp.com>
  51. 25 Jul, 2017 1 commit
    • MLK-16069 imx6slevk: Workaround to limit the u-boot in low 512MB memory · 92216844
      Ye Li authored 
      On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing.
And due to MMDC limitation, the script we get from IC team is only doing
CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might
cause CS0 can NOT be accessed any longer.

Because of this HW issue, we found the high 512MB memory needs more time to
be stable. Since the u-boot relocates itself to highest address after booting,
so this will cause issue.
To work around it, we just limit the u-boot running at low 512MB memory.
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
(cherry picked from commit 5fc93379)
  53. 19 Jul, 2017 1 commit
  55. 12 Jul, 2017 1 commit
    • MLK-15341 mx6qpsabresd: add PHY AR8031 hw reset · 721193c1
      Fugang Duan authored 
      Currently mx6qpsabresd board file only add PHY AR8031 gpio reset
in non-DM driver, then net DM driver PHY cannot work after stress
reboot test. So also add gpio reset for DM driver.

RGMII and PHY work at VDDIO 1.8V has better timing and to align
the IO voltage with kernel, also set the IO voltage to 1.8V.

Since i.MX6QP tx_clk can loop from SOC internal, no need to set
PHY output 125Mhz clock that can save power.
Signed-off-by: 's avatarFugang Duan <fugang.duan@nxp.com>
Reviewed-by: 's avatarYe Li <ye.li@nxp.com>
  57. 11 Jul, 2017 1 commit
  59. 10 Jul, 2017 5 commits