1. 14 Sep, 2017 1 commit
  2. 07 Sep, 2017 1 commit
    • MA-9554[Android_6DL_SD]RTC: Sometimes the RTC reset to the initial time 1970… · c250b072
      Zhang Bo authored
      MA-9554[Android_6DL_SD]RTC: Sometimes the RTC reset to the initial time 1970 after softare reboot the first time. 40%
      RTC timer is default disabled after power off and bootup again. it will be
      enabled in kernel rtc driver init. But rtc time is shorter than system clock,
      so rtc time cannot update to system clock in rtc_hctosys(), and the sysfs
      file /sys/class/rtc/rtc0/hctosys cat result is 0. Android AlarmManagerService
      cannot work normally when hctosys is 0.
      Enable RTC in u-boot so the time in RTC timer is longer than system clock.
      Change-Id: Ie8b1c1b36e5ab48031efe44dd06468ac35ca3d3b
      Signed-off-by: 's avatarZhang Bo <bo.zhang@nxp.com>
  3. 25 Jul, 2017 1 commit
    • MLK-16069 imx6slevk: Workaround to limit the u-boot in low 512MB memory · 92216844
      Ye Li authored
      On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing.
      And due to MMDC limitation, the script we get from IC team is only doing
      CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might
      cause CS0 can NOT be accessed any longer.
      Because of this HW issue, we found the high 512MB memory needs more time to
      be stable. Since the u-boot relocates itself to highest address after booting,
      so this will cause issue.
      To work around it, we just limit the u-boot running at low 512MB memory.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 5fc93379)
  4. 19 Jul, 2017 1 commit
  5. 12 Jul, 2017 1 commit
    • MLK-15341 mx6qpsabresd: add PHY AR8031 hw reset · 721193c1
      Fugang Duan authored
      Currently mx6qpsabresd board file only add PHY AR8031 gpio reset
      in non-DM driver, then net DM driver PHY cannot work after stress
      reboot test. So also add gpio reset for DM driver.
      RGMII and PHY work at VDDIO 1.8V has better timing and to align
      the IO voltage with kernel, also set the IO voltage to 1.8V.
      Since i.MX6QP tx_clk can loop from SOC internal, no need to set
      PHY output 125Mhz clock that can save power.
      Signed-off-by: 's avatarFugang Duan <fugang.duan@nxp.com>
      Reviewed-by: 's avatarYe Li <ye.li@nxp.com>
  6. 11 Jul, 2017 1 commit
  7. 10 Jul, 2017 6 commits
    • MA-9857 [Android] uboot change CONFIG_NAND_BOOT · 37116ed5
      zhang sanshan authored
      NAND macro has been changed to CONFIG_NAND_BOOT in uboot2017.
      Change-Id: I61dd03c0eed8a65100212607447a41bde431cc04
      Signed-off-by: 's avatarzhang sanshan <sanshan.zhang@nxp.com>
    • MA-9789 [fastboot]System doesn't enter fastboot mode automatically while there… · 259db9dc
      zhang sanshan authored
      MA-9789 [fastboot]System doesn't enter fastboot mode automatically while there is no valid gpt partition
      add command "fastboot 0"
      Change-Id: Ibad6dcab5213d815ac968034aeef5ff5a0be3b1b
      Signed-off-by: 's avatarzhang sanshan <sanshan.zhang@nxp.com>
    • MA-9409-3 Add base board support for android and android things. · 2c119607
      zhang sanshan authored
      * add board support for android and android things.
        mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
        reorganize the Kconfig, and fix the redefine issue.
      * add android configure into configure-while
      * add a common file mx_android_common.h
        it will be included by android and android things.
        defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
      * move partition_table_valid into f_fastboot.c.
        it's a common code.
      * add invalidate_dcache_range in fixed order.
        It will have salt invalid issue if we do not add it in order
      * add display for pico-7d.
      Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
      Signed-off-by: 's avatarzhang sanshan <sanshan.zhang@nxp.com>
    • MA-9409-2 fix some issue for android and android things · ff92794f
      zhang sanshan authored
      * Add CONFIG_SYSTEM_RAMDISK_SUPPORT to support system's ramdisk
      * Normal boot: cmdline to bypass ramdisk in boot.img,
        but use Recovery boot: Use the ramdisk in boot.img
      * commandline is larger than 512, system can't bootup sometime for commandline issue.
      * support fastboot getvar.
      * Support "fastboot erase" command for emmc device.
        TODO: uboot community have api to operate flash, we can unify this part
      * support "fastboot flash" even on damaged gpt
      Change-Id: I080c25d6569d6cab56ff025601cd3b8df21cf3dd
    • MA-9409-1 enable avb on android things. · 1c79796a
      zhang sanshan authored
      Fix issue for API changed from v2017.
      porting below patch from v2016.
      commit 44834fd1
      Change-Id: Ifaf0b86dd29648f9150646f00f54502676df9013
      Signed-off-by: 's avatarzhang sanshan <sanshan.zhang@nxp.com>
    • MA-9702-2 [Android] Enable booti for android arm64. · 893ec780
      sanshan zhang authored
      boot_addr_start for booti should be the addr of Image rather than
      boot.img, so need read Image into hdr->kernel_addr.
      change the offset for bootloader.
      booti do not call android_image_get_kernel to init android env.
      booti can't load boot.img, so it can't init android env.
      init android env through android_image_get_kernel.
      Change-Id: Ifb990ee9c5710ce7bd5fa9a0d4221dcb0e52d341
      Signed-off-by: 's avatarsanshan zhang <sanshan.zhang@nxp.com>
  8. 21 Jun, 2017 5 commits
  9. 20 Jun, 2017 5 commits
  10. 12 Jun, 2017 2 commits
    • MLK-14533 mx7ulp_evk: Change APLL and its PFD0 frequencies · db3ece42
      Ye Li authored
      To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since
      the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is
      201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources
      from APLL PFDs are higher than this max rate.
      The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must
      change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.
      Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12),
      with settings:
      PFD0 FRAC:  32
      APLL MULT:  22
      APLL NUM:   2
      APLL DENOM: 5
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
      Tested-by: 's avatarFancy Fang <chen.fang@nxp.com>
      (cherry picked from commit 91be2789)
      (cherry picked from commit 40fd4ea8)
    • MLK-15044 DTS: mx6ul/ullevk: Add OTG ID pin mux · 07504924
      Ye Li authored
      The OTG ID pin mux setting is missed in DTS, so the OTG can't work
      as host mode.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
      Reviewed-by: 's avatarPeng Fan <peng.fan@nxp.com>
      (cherry picked from commit b2332450)
  11. 24 May, 2017 2 commits
    • MLK-14930-2 dwc_ahsata: Fix memory issue in reset_sata · b83dba66
      Ye Li authored
      The reset_sata should reset the sata device info and free the probe_ent
      memory. Otherwise, it will cause memory leak if we init the sata again.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 39c9261fd057b0fa98f9dfdee7d368aa029ff736)
    • MLK-14930-1 cmd: sata: Fix sata init and stop issue · 2bfe8677
      Ye Li authored
      When sata stop is executed, the sata_curr_device is not reset to -1, so
      any following sata commands will not initialize the sata again and cause
      Additional, in sata init implementation, the sata_curr_device should be updated,
      otherwise sata will be initialized again when doing other sata commands like
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit e2a66807f3573e8344dcd285dcb7d53f0e5fcf8e)
  12. 22 May, 2017 2 commits
  13. 16 May, 2017 1 commit
    • MLK-14915 mx6ul_arm2/mx6ull_arm2: Fix ENET PHY reset issue · 950b322f
      Ye Li authored
      There are two pins used for ENET PHY reset, need to assert them before init the PHY.
      Current DM driver does not have such operation, need board level codes to handle.
      This patch moves the PHY reset operation into setup_fec, which is common for DM driver
      and non-DM driver.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
  14. 15 May, 2017 2 commits
    • MLK-14890 i2c: Enable I2C force idle bus · 25515dfb
      Ye Li authored
      This patch enables the I2C force idle bus for all i.MX6 and i.MX7 boards to avoid
      i2c bus problem during reboot. To use it, we must add some i2c properties in DTB file
      and the GPIO pinctrl for i2c.
      For mx6qsabreauto, mx6slevk, mx6sxsabresd and mx6sxscm, these boards call the
      setup_i2c. To remove conflict, change to use "setup_i2c" only for non-DM i2c driver.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
    • MLK-14891 mx6slevk/mx6sll_arm2: Fix SPINOR CS GPIO using · 09f2bc9e
      Ye Li authored
      Needs to request the GPIO pin before assigning to GPIO to SPI driver
      which will directly setting it to output without request it.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
  15. 12 May, 2017 2 commits
  16. 11 May, 2017 5 commits
    • ARM: fixed relocation using proper alignment · b505caa5
      Manfred Schlaegl authored
      Using u-boot-2017.05 on i.MX6UL we ran into following problem:
      Initially U-Boot could be started normally.
      If we added one random command in configuration, the newly generated
      image hung at startup (last output was DRAM:  256 MiB).
      We tracked this down to a data abort within relocation (relocated_code).
      relocated_code in arch/arm/lib/relocate.S copies 8 bytes per loop
      iteration until the source pointer is equal to __image_copy_end.
      In a good case __image_copy_end was aligned to 8 bytes, so the loop
      stopped as suggested, but in an errornous case __image_copy_end was
      not aligned to 8 bytes, so the loop ran out of bounds and caused a
      data abort exception.
      This patches solves the issue by aligning __image_copy_end to 8 byte
      using the linker script related to arm.
      From Community: http://patchwork.ozlabs.org/patch/760592/Signed-off-by: 's avatarPeng Fan <peng.fan@nxp.com>
    • MLK-14864: regulator: pfuze100: unsigned compared against 0 · 95b2ee32
      Peng Fan authored
      Fix coverity:392391 392382 392385 Unsigned compared against 0
      Signed-off-by: 's avatarPeng Fan <peng.fan@nxp.com>
    • MLK-14862 net: eth-uclass: add return value check · 3f805226
      Peng Fan authored
      Add return value check
      Coverity 392391
      Signed-off-by: 's avatarPeng Fan <peng.fan@nxp.com>
    • MLK-14840: pinctrl: imx: fix resource leak · aad973c1
      Peng Fan authored
      The device managed API actually not free the memory, so need
      to use devm_kfree to free the memory to avoid leakage.
      Coverity: 392384 resource leak
      Signed-off-by: 's avatarPeng Fan <peng.fan@nxp.com>
    • MLK-14878 qspi: Fix issue when enabling DDR mode · 16270556
      Ye Li authored
      There are two problems in enabling DDR mode in this new driver:
      1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
         won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
         cause explicit problem.
      2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
         like DDR_EN are cleared during these operations.  When we using DDR mode QSPI boot, the TDH bit
         is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
         So these operations will fail.
         The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
         after using DDR mode QSPI boot on 6UL/ULL EVK boards.
      Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
  17. 10 May, 2017 2 commits