Commit e6f2e902 by Marian Balakowicz

Added support for TQM834x boards.

parent 3df5bea0
......@@ -114,7 +114,7 @@ LIST_8260=" \
#########################################################################
LIST_83xx=" \
MPC8349ADS \
MPC8349ADS TQM834x\
"
......
......@@ -1241,6 +1241,9 @@ TASREG_config : unconfig
MPC8349ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
TQM834x_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx tqm834x
#########################################################################
## MPC85xx Systems
#########################################################################
......
#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################
#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x80000000
/*
* Copyright 2004 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
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PROVIDE (erotext = .);
.reloc :
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
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CONSTRUCTORS
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_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
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.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
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.bss :
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*(.sbss) *(.scommon)
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*(COMMON)
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PROVIDE (end = .);
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ENTRY(_start)
......@@ -84,7 +84,7 @@ static int image_info (unsigned long addr);
#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
#include <flash.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[]; /* info for FLASH chips */
static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif
......@@ -1082,7 +1082,7 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
if (info->flash_id == FLASH_UNKNOWN)
goto next_bank;
for (j=0; j<CFG_MAX_FLASH_SECT; ++j) {
for (j=0; j<info->sector_count; ++j) {
if (!(hdr=(image_header_t *)info->start[j]) ||
(ntohl(hdr->ih_magic) != IH_MAGIC))
......
......@@ -404,7 +404,11 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
{
flash_info_t *info;
ulong bank;
#ifdef CFG_MAX_FLASH_BANKS_DETECT
int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
#endif
int erased = 0;
int planned;
int rcode = 0;
......@@ -617,7 +621,11 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
{
flash_info_t *info;
ulong bank;
#ifdef CFG_MAX_FLASH_BANKS_DETECT
int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
#endif
int protected, i;
int planned;
int rcode;
......
......@@ -316,7 +316,7 @@ static int part_validate_nor(struct mtdids *id, struct part_info *part)
{
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
/* info for FLASH chips */
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern flash_info_t flash_info[];
flash_info_t *flash;
int offset_aligned;
u32 end_offset;
......@@ -711,7 +711,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
if (type == MTD_DEV_TYPE_NOR) {
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
if (num < CFG_MAX_FLASH_BANKS) {
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern flash_info_t flash_info[];
*size = flash_info[num].size;
return 0;
}
......
......@@ -91,7 +91,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Look for any and all PHYs. Valid addresses are 0..31.
*/
if (argc >= 3) {
start = addr; end = addr + 1;
start = addrlo; end = addrhi + 1;
} else {
start = 0; end = 32;
}
......
......@@ -28,7 +28,7 @@
#if !defined(CFG_NO_FLASH)
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
......
......@@ -50,7 +50,7 @@ int checkcpu(void)
return -1;
}
puts("CPU: MPC83xx, ");
puts("CPU: MPC83xx, ");
switch(pvr) {
case PVR_8349_REV10:
break;
......
......@@ -41,7 +41,7 @@
#include <i2c.h>
#include <asm/i2c.h>
#ifdef CONFIG_MPC8349ADS
#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
#endif
......@@ -109,7 +109,9 @@ i2c_wait (int write)
return 0;
} while (get_timer (timeval) < I2C_TIMEOUT);
debug("i2c_wait: timed out\n");
return -1;
}
static __inline__ int
......
......@@ -35,7 +35,7 @@
#include <common.h>
#include <pci.h>
#ifdef CONFIG_MPC8349ADS
#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
#include <asm/i2c.h>
#endif
......@@ -114,7 +114,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
/*
* Assign PIB PMC slot to desired PCI bus
*/
#ifdef CONFIG_MPC8349ADS
#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
#endif
......
......@@ -118,41 +118,50 @@ int get_clocks (void)
return -1;
#ifndef CFG_HRCW_HIGH
# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
# error "CFG_HRCW_HIGH must be defined in board config file"
#endif /* CFG_HCWD_HIGH */
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
# ifndef CONFIG_83XX_CLKIN
# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
# endif /* CONFIG_83XX_CLKIN */
# ifdef CONFIG_83XX_PCICLK
# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
# endif /* CONFIG_83XX_PCICLK */
/* PCI Host Mode */
/* PCI Host Mode */
if (!(im->reset.rcwh & RCWH_PCIHOST)) {
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
/* FIXME: findout if there is a way to issue some warning */
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
* the im->reset.rcwhr PCI Host Mode is disabled
* FIXME: findout if there is a way to issue some warning */
return -2;
}
if (im->clk.spmr & SPMR_CKID) {
pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
/* PCI Clock is half CONFIG_83XX_CLKIN */
pci_sync_in = CONFIG_83XX_CLKIN / 2;
}
else {
pci_sync_in = CONFIG_83XX_CLKIN;
}
#else
#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
# ifdef CONFIG_83XX_CLKIN
# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
# endif /* CONFIG_83XX_CLKIN */
# ifndef CONFIG_83XX_PCICLK
# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
# endif /* CONFIG_83XX_PCICLK */
/* PCI Agent Mode */
/* PCI Agent Mode */
if (im->reset.rcwh & RCWH_PCIHOST) {
/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
* the im->reset.rcwhr PCI Host Mode is enabled */
return -3;
}
pci_sync_in = CONFIG_83XX_PCICLK;
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */
......@@ -343,79 +352,14 @@ int print_clock_conf (void)
printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000);
printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
#if 0
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
ulong sccr, dfbrg;
ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
corecnf_t *cp;
sccr = immap->im_clkrst.car_sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
scmr = immap->im_clkrst.car_scmr;
corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
cp = &corecnf_tab[corecnf];
puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
switch (cp->b2c_mult) {
case _byp:
puts ("BYPASS");
break;
debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
case _off:
puts ("OFF");
break;
case _unk:
puts ("UNKNOWN");
break;
default:
printf ("%d%sx",
cp->b2c_mult / 2,
(cp->b2c_mult % 2) ? ".5" : "");
break;
}
printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
cp->vco_div, cp->freq_60x, cp->freq_core);
printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
"plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
pllmf);
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
gd->vco_out, gd->scc_clk, gd->brg_clk);
printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
if (sccr & SCCR_PCI_MODE) {
uint pci_div;
pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
}
putc ('\n');
#endif
return 0;
}
......@@ -166,9 +166,15 @@ typedef union {
#define NUM_ERASE_REGIONS 4
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
#else
static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
......@@ -184,7 +190,7 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, u
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
static ulong flash_get_size (ulong base, int banknum);
ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt);
......@@ -371,7 +377,7 @@ unsigned long flash_init (void)
static flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
flash_info_t * info = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
......@@ -1007,7 +1013,7 @@ static int flash_detect_cfi (flash_info_t * info)
* The following code cannot be run from FLASH!
*
*/
static ulong flash_get_size (ulong base, int banknum)
ulong flash_get_size (ulong base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
int i, j;
......
......@@ -44,7 +44,7 @@ struct cramfs_super super;
/* CPU address space offset calculation macro, struct part_info offset is
* device address space offset, so we need to shift it by a device start address. */
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern flash_info_t flash_info[];
#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
static int cramfs_read_super (struct part_info *info)
......
......@@ -263,7 +263,7 @@ static inline void *get_fl_mem_nor(u32 off)
u32 addr = off;
struct mtdids *id = current_part->dev->id;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern flash_info_t flash_info[];
flash_info_t *flash = &flash_info[id->num];
addr += flash->start[0];
......
......@@ -87,7 +87,7 @@ typedef struct i2c
#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
#endif
#ifdef CONFIG_MPC8349ADS
#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
/*
* MPC8349 have two i2c bus
*/
......
......@@ -613,9 +613,9 @@ typedef struct gpio8349 {
typedef struct ddr_cs_bnds{
u32 csbnds;
#define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT 16
#define CSBNDS_SA_SHIFT 8
#define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT 0
#define CSBNDS_EA_SHIFT 24
u8 res0[4];
} ddr_cs_bnds_t;
......@@ -652,6 +652,8 @@ typedef struct ddr8349{
#define TIMING_CFG1_ACTTOACT_SHIFT 4
#define TIMING_CFG1_WRTORD 0x00000007
#define TIMING_CFG1_WRTORD_SHIFT 0
#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO 0x0F000000
......@@ -659,6 +661,7 @@ typedef struct ddr8349{
#define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
u32 sdram_cfg; /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN 0x80000000
......@@ -672,6 +675,7 @@ typedef struct ddr8349{
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
u8 res2[4];
u32 sdram_mode; /**< SDRAM Mode Configuration */
......@@ -679,6 +683,25 @@ typedef struct ddr8349{
#define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0
#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
#define DDR_MODE_WEAK 0x0002 /* weak drivers */
#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
#define DDR_MODE_MODEREG 0x0000 /* select mode register */
u8 res3[8];
u32 sdram_interval; /**< SDRAM Interval Configuration */
......@@ -688,6 +711,9 @@ typedef struct ddr8349{
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
u8 res9[8];
u32 sdram_clk_cntl;
#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
u8 res4[0xCCC];
u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
......
......@@ -98,19 +98,27 @@
#define BR6 0x5030
#define BR7 0x5038
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_DECC 0x00000600
#define BR_DECC_SHIFT 9
#define BR_WP 0x00000100
#define BR_WP_SHIFT 8
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
#define BR_PS_16 0x00001000 /* Port Size 16 bit */
#define BR_PS_32 0x00001800 /* Port Size 32 bit */
#define BR_DECC 0x00000600
#define BR_DECC_SHIFT 9
#define BR_WP 0x00000100
#define BR_WP_SHIFT 8
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#define OR0 0x5004
#define OR1 0x500C
......@@ -121,26 +129,43 @@
#define OR6 0x5034
#define OR7 0x503C
#define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15
#define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800
#define OR_GPCM_CSNT_SHIFT 11
#define OR_GPCM_ACS 0x00000600
#define OR_GPCM_ACS_SHIFT 9
#define OR_GPCM_XACS 0x00000100
#define OR_GPCM_XACS_SHIFT 8
#define OR_GPCM_SCY 0x000000F0
#define OR_GPCM_SCY_SHIFT 4
#define OR_GPCM_SETA 0x00000008
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
#define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15
#define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800
#define OR_GPCM_CSNT_SHIFT 11
#define OR_GPCM_ACS 0x00000600
#define OR_GPCM_ACS_SHIFT 9
#define OR_GPCM_ACS_0b10 0x00000400
#define OR_GPCM_ACS_0b11 0x00000600
#define OR_GPCM_XACS 0x00000100
#define OR_GPCM_XACS_SHIFT 8
#define OR_GPCM_SCY 0x000000F0
#define OR_GPCM_SCY_SHIFT 4
#define OR_GPCM_SCY_1 0x00000010
#define OR_GPCM_SCY_2 0x00000020
#define OR_GPCM_SCY_3 0x00000030
#define OR_GPCM_SCY_4 0x00000040
#define OR_GPCM_SCY_5 0x00000050
#define OR_GPCM_SCY_6 0x00000060
#define OR_GPCM_SCY_7 0x00000070
#define OR_GPCM_SCY_8 0x00000080
#define OR_GPCM_SCY_9 0x00000090
#define OR_GPCM_SCY_10 0x000000a0
#define OR_GPCM_SCY_11 0x000000b0
#define OR_GPCM_SCY_12 0x000000c0
#define OR_GPCM_SCY_13 0x000000d0
#define OR_GPCM_SCY_14 0x000000e0
#define OR_GPCM_SCY_15 0x000000f0
#define OR_GPCM_SETA 0x00000008
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
#define OR_UPM_AM 0xFFFF8000
#define OR_UPM_AM_SHIFT 15
......
......@@ -58,7 +58,7 @@ static char default_filename[DEFAULT_NAME_LEN];
static char *tftp_filename;
#ifdef CFG_DIRECT_FLASH_TFTP
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern flash_info_t flash_info[];
#endif
static __inline__ void
......