Commit d6c556b7 by Jose Miquel Sanabria

IGEP0146: Add Support for Peripherials

SD I2C eMMC Tuned DRAM E²PROM Ethernet Fix using Hysteresis in MUX along with other pad control options Signed-off-by: Jose Miquel Sanabria's avatarJose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
parent fe1ef8a9
......@@ -9,17 +9,8 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "igep0046"
choice
prompt "Carrier Board"
default BASE0040
optional
config BASE0040
bool "Carrier board base0040"
help
This is the igep base0040 carrier board.
endchoice
bool "base0040"
config WITH_SPL_SUPPORT
bool "Build i.MX6 with SPL support"
......
......@@ -9,4 +9,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "igep0146"
config BASE0040
bool "base0040"
endif
IGEP0046 BOARD
IGEP0146 BOARD
M: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
S: Maintained
F: board/isee/igep0146/igep0146.c
F: include/configs/igep0146.h
F: board/isee/igep0146/mx6ul_igep0146_1x512.cfg
F: configs/mx6ul_igep0146_512M_defconfig
......@@ -6,4 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += igep0146_eeprom.o
obj-y += igep0146.o
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* New DDR type MT41K64M16TW-107 */
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4 0x020c4068 0xffffffff // CCM_CCGR0
DATA 4 0x020c406c 0xffffffff // CCM_CCGR1
DATA 4 0x020c4070 0xffffffff // CCM_CCGR2
DATA 4 0x020c4074 0xffffffff // CCM_CCGR3
DATA 4 0x020c4078 0xffffffff // CCM_CCGR4
DATA 4 0x020c407c 0xffffffff // CCM_CCGR5
DATA 4 0x020c4080 0xffffffff // CCM_CCGR6
//=============================================================================
// IOMUX IMX6UL - MCIMX6G3CV
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020E04B4 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020E04AC 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4 0x020E027C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
//ADDRESS:
DATA 4 0x020E0250 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B
DATA 4 0x020E024C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
DATA 4 0x020E0490 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4 0x020E0288 0x000C0030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020E0270 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
DATA 4 0x020E0260 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
DATA 4 0x020E0264 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
DATA 4 0x020E04A0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020E0494 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020E0280 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
DATA 4 0x020E0284 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
//Data:
DATA 4 0x020E04B0 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020E0498 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020E04A4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020E0244 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020E0248 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K64M16TW-107
// Clock Freq.: 933 MHz IMX6UL ensures data capture margin up to 400 Mhz
// Density per CS in Gb: 1 Gb
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 13
// Column address: 10
// Data bus width 16
//=============================================================================
DATA 4 0x021B001C 0x00008000 // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup. REVISAR
//=============================================================================
DATA 4 0x021B0800 0xA1390003 // MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
DATA 4 0x021B080C 0x00000000 // MMDC_MPWLDECTRL0
// Read DQS Gating calibration
DATA 4 0x021B083C 0x415C015C // MMDC_MPDGCTRL0
// Read Calibration
DATA 4 0x021B0848 0x40404040 // MMDC_MPRDDLCTL 0x40404244
// Write Calibration
DATA 4 0x021B0850 0x40404040 // MMDC_MPWRDLCTL 0x40405A58
// Read Data bit delay
DATA 4 0x021B081C 0x33333333 // MMDC_MPRDDQBY0DL
DATA 4 0x021B0820 0x33333333 // MMDC_MPRDDQBY1DL
DATA 4 0x021B082C 0xf3333333 // MMDC_MPWRDQBY0DL
DATA 4 0x021B0830 0xf3333333 // MMDC_MPWRDQBY1DL
// Control Duty Cicle DQS of and primary clock CK0
DATA 4 0x021B08C0 0x24922492 // MMDC_MPDCCR 0x00921012 24922492 0x00921012
// Complete Calibration by Forced Measurement
DATA 4 0x021B08b8 0x00008000 // MMDC_MPMUR0
//=============================================================================
// Calibration setup end
//=============================================================================
// MMCD Init
DATA 4 0x021B0004 0x00020036 // MMDC_MDPDC
DATA 4 0x021B0008 0x1B333030 // MMDC_MDOTC
DATA 4 0x021B000C 0x676B52F3 // MMDC_MDCFG0
DATA 4 0x021B0010 0xB66D0B63 // MMDC_MDCFG1
DATA 4 0x021B0014 0x01FF00DB // MMDC_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021B0018 0x00201740 // MMDC_MDMISC
DATA 4 0x021B001C 0x00000800 // MMDC_MDSCR
DATA 4 0x021B002C 0x000026D2 // MMDC_MDRWD
DATA 4 0x021B0030 0x006B1023 // MMDC_MDOR
DATA 4 0x021B0040 0x0000004F // MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
DATA 4 0x021B0000 0x82180000 // MMDC_MDCTL
// ????
DATA 4 0x021B0890 0x00400000 // MMDC_MPPDCMPR2 DDR2 Only ???
// Mode Register writes
// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
DATA 4 0x021B001C 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021B001C 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021B001C 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021B001C 0x15208030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021B001C 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
DATA 4 0x021B0020 0x00000800 // MMDC0_MDREF
DATA 4 0x021B0818 0x00000227 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021B0004 0x0002552D // MMDC0_MDPDC
DATA 4 0x021B0404 0x00011006 // MMDC0_MAPSR
DATA 4 0x021B001C 0x00000000 // MMDC0_MDSCR
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* DDR type MT41K256M16TW-107 */
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020e04b4 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE -- tipo DDR3 (0x000C0000)
DATA 4 0x020e04ac 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE -- Pull keeper enable / disbale (enable = 0x00001000)
//CLOCK:
DATA 4 0x020e027c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 -- (R0/6)
//ADDRESS:
DATA 4 0x020e0250 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DATA 4 0x020e024c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DATA 4 0x020e0490 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4 0x020e0288 0x000C0030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET -- DRAM_RST: DDR3 SEL + pull down 100k (0x000C0030)
DATA 4 0x020e0270 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4 0x020e0260 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
DATA 4 0x020e0264 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
DATA 4 0x020e04a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020e0494 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020e0280 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
DATA 4 0x020e0284 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
//Data:
DATA 4 0x020e04b0 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020e0498 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020e04a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020e0244 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020e0248 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K256M16TW-107
// Clock Freq.: 400MHz
// Density per CS in Gb: 4
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 15
// Column address: 10
// Data bus width 16
//=============================================================================
DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup.
//=============================================================================
DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
DATA 4 0x021b080c 0x00000000
//Read DQS Gating calibration
DATA 4 0x021b083c 0x014C0150 // 0x415C015C MPDGCTRL0 PHY0
//Read calibration
DATA 4 0x021b0848 0x4040464E // 0x40404244 MPRDDLCTL PHY0
//Write calibration
DATA 4 0x021b0850 0x4040564E // 0x40405A58 MPWRDLCTL PHY0
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
DATA 4 0x021b081c 0x33333333 // MMDC_MPRDDQBY0DL
DATA 4 0x021b0820 0x33333333 // MMDC_MPRDDQBY1DL
//write data bit delay:
DATA 4 0x021b082c 0xF3333333 // MMDC_MPWRDQBY0DL
DATA 4 0x021b0830 0xF3333333 // MMDC_MPWRDQBY1DL
//DQS&CLK Duty Cycle
DATA 4 0x021b08c0 0x00921012 // [MMDC_MPDCCR] MMDC Duty Cycle Control Register
// Complete calibration by forced measurement:
DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================
//MMDC init:
DATA 4 0x021b0004 0x0002002D // MMDC0_MDPDC
DATA 4 0x021b0008 0x1B333030 // MMDC0_MDOTC
DATA 4 0x021b000c 0x676B52F3 // MMDC0_MDCFG0
DATA 4 0x021b0010 0xB66D0B63 // MMDC0_MDCFG1
DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021b0018 0x00201740 // MMDC0_MDMISC
DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD
DATA 4 0x021b0030 0x006B1023 // MMDC0_MDOR
DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END
DATA 4 0x021b0000 0x84180000 // MMDC0_MDCTL
DATA 4 0x021b0890 0x00400000 // MPPDCMPR2
//Mode register writes
DATA 4 0x021b001c 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021b001c 0x15208030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
//DATA 4 0x021b001c 0x0200803A // MMDC0_MDSCR, MR2 write, CS1
//DATA 4 0x021b001c 0x0000803B // MMDC0_MDSCR, MR3 write, CS1
//DATA 4 0x021b001c 0x00448039 // MMDC0_MDSCR, MR1 write, CS1
//DATA 4 0x021b001c 0x15208038 // MMDC0_MDSCR, MR0write, CS1
//DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1
DATA 4 0x021b0020 0x00000800 // MMDC0_MDREF
DATA 4 0x021b0818 0x00000227 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021b0004 0x0002552D // MMDC0_MDPDC now SDCTL power down enabled
DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* DDR type MT41K256M16TW-107 */
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4 0x020c4068 0xffffffff // CCM_CCGR0
DATA 4 0x020c406c 0xffffffff // CCM_CCGR1
DATA 4 0x020c4070 0xffffffff // CCM_CCGR2
DATA 4 0x020c4074 0xffffffff // CCM_CCGR3
DATA 4 0x020c4078 0xffffffff // CCM_CCGR4
DATA 4 0x020c407c 0xffffffff // CCM_CCGR5
DATA 4 0x020c4080 0xffffffff // CCM_CCGR6
//=============================================================================
// IOMUX IMX6UL - MCIMX6G3CV
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020E04B4 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020E04AC 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4 0x020E027C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
//ADDRESS:
DATA 4 0x020E0250 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B
DATA 4 0x020E024C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
DATA 4 0x020E0490 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4 0x020E0288 0x000C0030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020E0270 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
DATA 4 0x020E0260 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
DATA 4 0x020E0264 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
DATA 4 0x020E04A0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020E0494 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020E0280 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
DATA 4 0x020E0284 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
//Data:
DATA 4 0x020E04B0 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020E0498 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020E04A4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020E0244 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020E0248 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K256M16TW-107
// Clock Freq.: 933 MHz IMX6UL ensures data capture margin up to 400 Mhz
// Density per CS in Gb: 4 Gb
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 15
// Column address: 10
// Data bus width 16
//=============================================================================
DATA 4 0x021B001C 0x00008000 // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup. REVISAR
//=============================================================================
DATA 4 0x021B0800 0xA1390003 // MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
DATA 4 0x021B080C 0x00000000 // MMDC_MPWLDECTRL0
// Read DQS Gating calibration
DATA 4 0x021B083C 0x00000000 // MMDC_MPDGCTRL0
// Read Calibration
DATA 4 0x021B0848 0x40404040 // MMDC_MPRDDLCTL 0x40404244
// Write Calibration
DATA 4 0x021B0850 0x40404040 // MMDC_MPWRDLCTL 0x40405A58
// Read Data bit delay
DATA 4 0x021B081C 0x33333333 // MMDC_MPRDDQBY0DL
DATA 4 0x021B0820 0x33333333 // MMDC_MPRDDQBY1DL
DATA 4 0x021B082C 0xf3333333 // MMDC_MPWRDQBY0DL
DATA 4 0x021B0830 0xf3333333 // MMDC_MPWRDQBY1DL
// Control Duty Cicle DQS of and primary clock CK0
DATA 4 0x021B08C0 0x24922492 // MMDC_MPDCCR 0x00921012 24922492 0x00921012
// Complete Calibration by Forced Measurement
DATA 4 0x021B08b8 0x00008000 // MMDC_MPMUR0
//=============================================================================
// Calibration setup end
//=============================================================================
// MMCD Init
DATA 4 0x021B0004 0x00020036 // MMDC_MDPDC
DATA 4 0x021B0008 0x00333030 // MMDC_MDOTC
DATA 4 0x021B000C 0x676B52F3 // MMDC_MDCFG0
DATA 4 0x021B0010 0xB66D0B63 // MMDC_MDCFG1
DATA 4 0x021B0014 0x01FF00DB // MMDC_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021B0018 0x00201740 // MMDC_MDMISC
DATA 4 0x021B001C 0x00000800 // MMDC_MDSCR
DATA 4 0x021B002C 0x000026D2 // MMDC_MDRWD
DATA 4 0x021B0030 0x006B1023 // MMDC_MDOR
DATA 4 0x021B0040 0x0000003F // MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
DATA 4 0x021B0000 0x84180000 // MMDC_MDCTL
// ????
DATA 4 0x021B0890 0x00400000 // MMDC_MPPDCMPR2 DDR2 Only ???
// Mode Register writes
// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
DATA 4 0x021B001C 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021B001C 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021B001C 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021B001C 0x15208030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021B001C 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
DATA 4 0x021B0020 0x00000800 // MMDC0_MDREF
DATA 4 0x021B0818 0x00000227 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021B0004 0x0002556D // MMDC0_MDPDC
DATA 4 0x021B0404 0x00011006 // MMDC0_MAPSR
DATA 4 0x021B001C 0x00000000 // MMDC0_MDSCR
/*
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
/* IOMUX - DDR IO Type */
DATA 4 0x020e0618 0x000c0000
DATA 4 0x020e05fc 0x00000000
/* Clock */
DATA 4 0x020e032c 0x00000030
/* Address */
DATA 4 0x020e0300 0x00000020
DATA 4 0x020e02fc 0x00000020
DATA 4 0x020e05f4 0x00000020
/* Control */
DATA 4 0x020e0340 0x00000020
DATA 4 0x020e0320 0x00000000
DATA 4 0x020e0310 0x00000020
DATA 4 0x020e0314 0x00000020
DATA 4 0x020e0614 0x00000020
/* Data Strobe */
DATA 4 0x020e05f8 0x00020000
DATA 4 0x020e0330 0x00000028
DATA 4 0x020e0334 0x00000028
DATA 4 0x020e0338 0x00000028
DATA 4 0x020e033c 0x00000028
/* Data */
DATA 4 0x020e0608 0x00020000
DATA 4 0x020e060c 0x00000028
DATA 4 0x020e0610 0x00000028
DATA 4 0x020e061c 0x00000028
DATA 4 0x020e0620 0x00000028
DATA 4 0x020e02ec 0x00000028
DATA 4 0x020e02f0 0x00000028
DATA 4 0x020e02f4 0x00000028
DATA 4 0x020e02f8 0x00000028
/* Calibrations - ZQ */
DATA 4 0x021b0800 0xa1390003
/* Write leveling */
DATA 4 0x021b080c 0x00290025
DATA 4 0x021b0810 0x00220022
/* DQS Read Gate */
DATA 4 0x021b083c 0x41480144
DATA 4 0x021b0840 0x01340130
/* Read/Write Delay */
DATA 4 0x021b0848 0x3C3E4244
DATA 4 0x021b0850 0x34363638
/* Read data bit delay */
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
/* Complete calibration by forced measurement */
DATA 4 0x021b08b8 0x00000800
/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4 0x021b0004 0x0002002d
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x676b52f3
DATA 4 0x021b0010 0xb66d8b63
DATA 4 0x021b0014 0x01ff00db
DATA 4 0x021b0018 0x00011740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x006b1023
DATA 4 0x021b0040 0x0000005f
DATA 4 0x021b0000 0x84190000
/* Initialize MT41K256M16HA-125 - MR2 */
DATA 4 0x021b001c 0x04008032
/* MR3 */
DATA 4 0x021b001c 0x00008033
/* MR1 */
DATA 4 0x021b001c 0x00048031
/* MR0 */
DATA 4 0x021b001c 0x05208030
/* DDR device ZQ calibration */
DATA 4 0x021b001c 0x04008040
/* Final DDR setup, before operation start */
DATA 4 0x021b0020 0x00000800
DATA 4 0x021b0818 0x00011117
DATA 4 0x021b001c 0x00000000
#endif
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg,MX6UL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0146/mx6ul_igep0146_1x512.cfg,MX6UL"
CONFIG_ARM=y