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powerpc: remove MBX and MBX860T boards support

Enough time has passed since these boards were moved to Orphan. Remove.

 - Remove board/mbx8xx/*
 - Remove include/configs/{MBX.h,MBX860T.h}
 - Clean-up if defined(CONFIG_MBX)
 - Move the entries from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
imx_3.14.38_6ul_engr
Masahiro Yamada 7 years ago
committed by Tom Rini
parent
commit
d6b11fd1f0
23 changed files with 1 additions and 2411 deletions
  1. +0
    -16
      arch/powerpc/cpu/mpc8xx/cpu_init.c
  2. +0
    -4
      arch/powerpc/cpu/mpc8xx/scc.c
  3. +0
    -4
      arch/powerpc/cpu/mpc8xx/serial.c
  4. +0
    -1
      arch/powerpc/include/asm/immap_512x.h
  5. +0
    -8
      board/mbx8xx/Makefile
  6. +0
    -68
      board/mbx8xx/README
  7. +0
    -44
      board/mbx8xx/csr.h
  8. +0
    -98
      board/mbx8xx/dimm.h
  9. +0
    -392
      board/mbx8xx/flash.c
  10. +0
    -383
      board/mbx8xx/mbx8xx.c
  11. +0
    -156
      board/mbx8xx/pcmcia.c
  12. +0
    -82
      board/mbx8xx/u-boot.lds
  13. +0
    -122
      board/mbx8xx/u-boot.lds.debug
  14. +0
    -180
      board/mbx8xx/vpd.c
  15. +0
    -119
      board/mbx8xx/vpd.h
  16. +0
    -2
      boards.cfg
  17. +1
    -0
      doc/README.scrapyard
  18. +0
    -7
      include/common.h
  19. +0
    -32
      include/commproc.h
  20. +0
    -290
      include/configs/MBX.h
  21. +0
    -395
      include/configs/MBX860T.h
  22. +0
    -4
      post/cpu/mpc8xx/ether.c
  23. +0
    -4
      post/cpu/mpc8xx/uart.c

+ 0
- 16
arch/powerpc/cpu/mpc8xx/cpu_init.c View File

@ -29,12 +29,10 @@ void cpm_load_patch (volatile immap_t * immr);
*/
void cpu_init_f (volatile immap_t * immr)
{
#ifndef CONFIG_MBX
volatile memctl8xx_t *memctl = &immr->im_memctl;
# ifdef CONFIG_SYS_PLPRCR
ulong mfmask;
# endif
#endif
ulong reg;
/* SYPCR - contains watchdog control (11-9) */
@ -74,8 +72,6 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
#ifndef CONFIG_MBX /* MBX board does things different */
/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
* set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
* otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
@ -203,8 +199,6 @@ void cpu_init_f (volatile immap_t * immr)
memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#endif /* ! CONFIG_MBX */
/*
* Reset CPM
*/
@ -213,16 +207,6 @@ void cpu_init_f (volatile immap_t * immr)
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
#ifdef CONFIG_MBX
/*
* on the MBX, things are a little bit different:
* - we need to read the VPD to get board information
* - the plprcr is set up dynamically
* - the memory controller is set up dynamically
*/
mbx_init ();
#endif /* CONFIG_MBX */
#ifdef CONFIG_RPXCLASSIC
rpxclassic_init ();
#endif


+ 0
- 4
arch/powerpc/cpu/mpc8xx/scc.c View File

@ -492,10 +492,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
immr->im_cpm.cp_pbdat &= ~0x00000010;
#endif /* QS860T */
#ifdef CONFIG_MBX
board_ether_init ();
#endif
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;


+ 0
- 4
arch/powerpc/cpu/mpc8xx/serial.c View File

@ -225,10 +225,6 @@ static int smc_init (void)
up->smc_tstate = 0;
#endif
#if defined(CONFIG_MBX)
board_serial_init();
#endif /* CONFIG_MBX */
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/


+ 0
- 1
arch/powerpc/include/asm/immap_512x.h View File

@ -59,7 +59,6 @@ typedef struct sysconf512x {
u8 res2[0x28];
law512x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
u32 nfcbar; /* NFC Base Address */
u8 res4[0x34];


+ 0
- 8
board/mbx8xx/Makefile View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = mbx8xx.o flash.o vpd.o pcmcia.o

+ 0
- 68
board/mbx8xx/README View File

@ -1,68 +0,0 @@
IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board
config file!!!
WARNING: Wrong settings of this parameter have the potential to
damage hardware by running the MBX's CPU at frequencies that exceed
it's rating and/or overdriving the it's SPLL!
Ramblings:
1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s.
2) Of these 12 variants, only 2 were entry level boards.
3) I believe that the 2 entry level boards were the only ones that
used OSCM clocking. I can't be completely certain of this at this
point.
4) Motorola never offered an MBX that ran faster than 50Mhz.
5) The 10, non-entry level boards, ran at 40Mhz.
6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860.
7) Motorola no longer sells MBXs.
Based on this information, I can surmise that the default power-on
reset clocking was one of the following three options.
Multiplier SPLL Options
------------------------------------
513 OSCM is SPLL input
5 OSCM is SPLL input
1 EXTCLK is SPLL input
The forth option:
5 EXTCLK is SPLL input
is not possible on MBXs. This is because the minimum EXTCLK input
frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran
above 50 Mhz.
The board I have borrowed definitely uses a multiplier of 1 for
EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it.
One of the two default OSCM modes are most likely what was used on
the entry level boards to cheapen them by eliminating the external
crystal oscillator.
To add insult to injury, the stupid 860 PLPRCR register retains it's
multiplication factor through hard resets. You can't clear it out
because it is battery backed and once it is set wrong, it stays
wrong. The only way to reset it, so that it takes on it's default
multiplier is to disconnect all power including external, batteries,
as well discharging caps on the board. This precludes the fact that
your 860 may be quite DEAD by this time!
If you don't setup the multiplication factor for boards that use the
OSCM input, they won't run correctly, but at least they won't be
dead.
Addtionally, there is no good way to determine the clock input source
from CPU register data. The only way to deal with this is either hard
code it, determine the correct value with some rather NASTY timing
loops, or try to grok it from external data sources. Motorola
firmware opts for the NASTY timing loops, but needs to configure the
serial ports to do so.
You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your
MBX8xx board is using the OSCM clocking mode.
You better know what you are doing here.

+ 0
- 44
board/mbx8xx/csr.h View File

@ -1,44 +0,0 @@
#ifndef __csr_h
#define __csr_h
/*
* (C) Copyright 2000
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Control and Status Register definitions for the MBX
*
*--------------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
/* bits for control register #1 / status register #1 */
#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */
#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */
#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */
#define CSR1_TPEN 0x10 /* TP manually selected */
#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */
#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */
#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */
#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */
/* bits for control register #2 */
#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
#define CR2_BRDFAIL 0x08 /* Board fail */
#define CR2_SWS1 0x04 /* Software Status #2 LED */
#define CR2_SWS2 0x02 /* Software Status #2 LED */
#define CR2_QSPANRST 0x01 /* Reset QSPAN */
/* bits for status register #2 */
#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */
#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */
#define SR2_RDY 0x02 /* Flash programming status bit */
#define SR2_FT 0x01 /* Reserved for Factory test purposes */
#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE))
#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1))
#endif /* __csr_h */

+ 0
- 98
board/mbx8xx/dimm.h View File

@ -1,98 +0,0 @@
#ifndef __dimm_h
#define __dimm_h
/*
* Module name: %M%
* Description:
* Serial Presence Detect Definitions Module
* SCCS identification: %I%
* Branch: %B%
* Sequence: %S%
* Date newest applied delta was created (MM/DD/YY): %G%
* Time newest applied delta was created (HH:MM:SS): %U%
* SCCS file name %F%
* Fully qualified SCCS file name:
* %P%
* Copyright:
* (C) COPYRIGHT MOTOROLA, INC. 1996
* ALL RIGHTS RESERVED
* Notes:
* 1. All data was taken from an IBM application note titled
* "Serial Presence Detect Definitions".
* History:
* Date Who
*
* 10/24/96 Rob Baxter
* Initial release.
*
*/
/*
* serial PD byte assignment address map (256 byte EEPROM)
*/
typedef struct dimm
{
uchar n_bytes; /* 00 number of bytes written/used */
uchar t_bytes; /* 01 total number of bytes in serial PD device */
uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */
uchar n_row; /* 03 number of rows */
uchar n_col; /* 04 number of columns */
uchar n_banks; /* 05 number of banks */
uchar data_w_lo; /* 06 data width */
uchar data_w_hi; /* 07 data width */
uchar ifl; /* 08 interface levels */
uchar a_ras; /* 09 RAS access */
uchar a_cas; /* 0A CAS access */
uchar ct; /* 0B configuration type (non-parity/parity/ECC) */
uchar refresh_rt; /* 0C refresh rate/type */
uchar p_dram_o; /* 0D primary DRAM organization */
uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */
uchar reserved[17]; /* 0F reserved fields for future offerings */
uchar ss_info[32]; /* 20 superset information (may be used in the future) */
uchar m_info[64]; /* 40 manufacturer information (optional) */
uchar unused[128]; /* 80 unused storage locations */
} dimm_t;
/*
* memory type definitions
*/
#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */
#define DIMM_MT_EDO 2 /* EDO (extended data out) */
#define DIMM_MT_PN 3 /* pipelined nibble */
#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */
/*
* row addresses definitions
*/
#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */
#define DIMM_RA_MASK 0x7f /* number of row addresses mask */
/*
* module interface levels definitions
*/
#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */
#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */
#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */
#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */
#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */
/*
* DIMM configuration type definitions
*/
#define DIMM_CT_NONE 0 /* none */
#define DIMM_CT_PARITY 1 /* parity */
#define DIMM_CT_ECC 2 /* ECC */
/*
* row addresses definitions
*/
#define DIMM_RRT_SR (1<<7) /* self refresh flag */
#define DIMM_RRT_MASK 0x7f /* refresh rate mask */
#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */
#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */
#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */
#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */
#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */
#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */
#endif /* __dimm_h */

+ 0
- 392
board/mbx8xx/flash.c View File

@ -1,392 +0,0 @@
/*
* (C) Copyright 2000
* Marius Groeger <mgroeger@sysgo.de>
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Flash Routines for AM290[48]0B devices
*
*--------------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
#include "vpd.h"
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size, totsize;
int i;
ulong addr;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
totsize = 0;
addr = 0xfc000000;
for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
size = flash_get_size((vu_long *)addr, &flash_info[i]);
if (flash_info[i].flash_id == FLASH_UNKNOWN)
break;
totsize += size;
addr += size;
}
addr = 0xfe000000;
for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
size = flash_get_size((vu_long *)addr, &flash_info[i]);
if (flash_info[i].flash_id == FLASH_UNKNOWN)
break;
totsize += size;
addr += size;
}
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
return (totsize);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id >> 16) {
case 0x1:
printf ("AMD ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case AMD_ID_F040B:
printf ("AM29F040B (4 Mbit)\n");
break;
case AMD_ID_F080B:
printf ("AM29F080B (8 Mbit)\n");
break;
case AMD_ID_F016D:
printf ("AM29F016D (16 Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong vendor, devid;
ulong base = (ulong)addr;
/* Write auto select command: read Manufacturer ID */
addr[0x0555] = 0xAAAAAAAA;
addr[0x02AA] = 0x55555555;
addr[0x0555] = 0x90909090;
vendor = addr[0];
devid = addr[1] & 0xff;
/* only support AMD */
if (vendor != 0x01010101) {
return 0;
}
vendor &= 0xf;
devid &= 0xff;
if (devid == AMD_ID_F040B) {
info->flash_id = vendor << 16 | devid;
info->sector_count = 8;
info->size = info->sector_count * 0x10000;
}
else if (devid == AMD_ID_F080B) {
info->flash_id = vendor << 16 | devid;
info->sector_count = 16;
info->size = 4 * info->sector_count * 0x10000;
}
else if (devid == AMD_ID_F016D) {
info->flash_id = vendor << 16 | devid;
info->sector_count = 32;
info->size = 4 * info->sector_count * 0x10000;
}
else {
printf ("## Unknown Flash Type: %08lx\n", devid);
return 0;
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* sector base address */
info->start[i] = base + i * (info->size / info->sector_count);
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (vu_long *)info->start[0];
addr[0] = 0xF0; /* reset bank */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0XAAAAAAAA;
addr[0x02AA] = 0x55555555;
addr[0x0555] = 0x80808080;
addr[0x0555] = 0XAAAAAAAA;
addr[0x02AA] = 0x55555555;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long*)(info->start[sect]);
addr[0] = 0x30303030;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long*)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned long *)info->start[0];
addr[0] = 0xF0F0F0F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAAAAAAAA;
addr[0x02AA] = 0x55555555;
addr[0x0555] = 0xA0A0A0A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

+ 0
- 383
board/mbx8xx/mbx8xx.c View File

@ -1,383 +0,0 @@
/*
* (C) Copyright 2000
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Board specific routines for the MBX
*
* - initialisation
* - interface to VPD data (mac address, clock speeds)
* - memory controller
* - serial io initialisation
* - ethernet io initialisation
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <commproc.h>
#include <mpc8xx.h>
#include <net.h>
#include "dimm.h"
#include "vpd.h"
#include "csr.h"
/* ------------------------------------------------------------------------- */
static const uint sdram_table_40[] = {
/* DRAM - single read. (offset 0 in upm RAM)
*/
0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* DRAM - burst read. (offset 8 in upm RAM)
*/
0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* DRAM - single write. (offset 18 in upm RAM)
*/
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804,
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* DRAM - burst write. (offset 20 in upm RAM)
*/
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* refresh (offset 30 in upm RAM)
*/
0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* exception. (offset 3c in upm RAM)
*/
0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
};
static const uint sdram_table_50[] = {
/* DRAM - single read. (offset 0 in upm RAM)
*/
0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
/* DRAM - burst read. (offset 8 in upm RAM)
*/
0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
/* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */
0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
/* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */
0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
/* DRAM - single write. (offset 18 in upm RAM)
*/
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* DRAM - burst write. (offset 20 in upm RAM)
*/
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* refresh (offset 30 in upm RAM)
*/
0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
/* exception. (offset 3c in upm RAM)
*/
0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
};
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_SYS_USE_OSCCLK
static unsigned int get_reffreq(void);
#endif
static unsigned int board_get_cpufreq(void);
void mbx_init (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
ulong speed, plprcr, sccr;
ulong br0_32 = memctl->memc_br0 & 0x400;
/* real-time clock status and control register */
immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
immr->im_sit.sit_rtcsc = 0x00C3;
/* SIEL and SIMASK Registers (see MBX PRG 2-3) */
immr->im_siu_conf.sc_simask = 0x00000000;
immr->im_siu_conf.sc_siel = 0xAAAA0000;
immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
/*
* Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
* 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
* 2. RAM Specs (see dimm.h)
* 2. DIMM Specs (see dimm.h)
*/
vpd_init ();
/* system clock and reset control register */
immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
sccr = immr->im_clkrst.car_sccr;
sccr &= SCCR_MASK;
sccr |= CONFIG_SYS_SCCR;
immr->im_clkrst.car_sccr = sccr;
speed = board_get_cpufreq ();
#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
plprcr = CONFIG_SYS_PLPRCR;
#else
plprcr = immr->im_clkrst.car_plprcr;
plprcr &= PLPRCR_MF_MSK; /* isolate MF field */
plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */
#endif
#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */
plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20;
#endif
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
immr->im_clkrst.car_plprcr = plprcr;
/*
* preliminary setup of memory controller:
* - map Flash, otherwise configuration/status
* registers won't be accessible when read
* by board_init_f.
* - map NVRAM and configuation/status registers.
* - map pci registers.
* - DON'T map ram yet, this is done in initdram().
*/
switch (speed / 1000000) {
case 40:
memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
memctl->memc_or0 = 0xFF800930;
memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920;
memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
break;
case 50:
memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
memctl->memc_or0 = 0xFF800940;
memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930;
memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
break;
default:
hang ();
break;
}
#ifdef CONFIG_USE_PCI
memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR;
memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001;
memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR;
memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001;
#endif
/*
* FIXME: I do not understand why I have to call this to
* initialise the control register here before booting from
* the PCMCIA card but if I do not the Linux kernel falls
* over in a big heap. If you can answer this question I
* would like to know about it.
*/
board_ether_init();
}
void board_serial_init (void)
{
MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS);
}
void board_ether_init (void)
{
MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
}
static unsigned int board_get_cpufreq (void)
{
#ifndef CONFIG_8xx_GCLK_FREQ
vpd_packet_t *packet;
ulong *p;
packet = vpd_find_packet (VPD_PID_ICS);
p = (ulong *)packet->data;
return *p;
#else
return((unsigned int)CONFIG_8xx_GCLK_FREQ );
#endif /* CONFIG_8xx_GCLK_FREQ */
}
#ifdef CONFIG_SYS_USE_OSCCLK
static unsigned int get_reffreq (void)
{
vpd_packet_t *packet;
ulong *p;
packet = vpd_find_packet (VPD_PID_RCS);
p = (ulong *)packet->data;
return *p;
}
#endif
static void board_get_enetaddr(uchar *addr)
{
int i;
vpd_packet_t *packet;
packet = vpd_find_packet (VPD_PID_EA);
for (i = 0; i < 6; i++)
addr[i] = packet->data[i];
}
int misc_init_r(void)
{
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
board_get_enetaddr(enetaddr);
eth_setenv_enetaddr("ethaddr", enetaddr);
}
return 0;
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
vpd_packet_t *packet;
int i;
const char *const fmt =
"\n *** Warning: Low Battery Status - %s Battery ***";
puts ("Board: ");
packet = vpd_find_packet (VPD_PID_PID);
for (i = 0; i < packet->size; i++) {
serial_putc (packet->data[i]);
}
packet = vpd_find_packet (VPD_PID_MT);
for (i = 0; i < packet->size; i++) {
serial_putc (packet->data[i]);
}
serial_putc ('(');
packet = vpd_find_packet (VPD_PID_FAN);
for (i = 0; i < packet->size; i++) {
serial_putc (packet->data[i]);
}
serial_putc (')');
if (!(MBX_CSR2 & SR2_BATGD))
printf (fmt, "On-Board");
if (!(MBX_CSR2 & SR2_NVBATGD))
printf (fmt, "NVRAM");
serial_putc ('\n');
return (0);
}
/* ------------------------------------------------------------------------- */
static ulong get_ramsize (dimm_t * dimm)
{
ulong size = 0;
if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3
|| dimm->fmt == 4) {
size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks *
((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8);
}
return size;
}
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long ram_sz = 0;
unsigned long dimm_sz = 0;
dimm_t vpd_dimm, vpd_dram;
unsigned int speed = board_get_cpufreq () / 1000000;
if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) {
dimm_sz = get_ramsize (&vpd_dimm);
}
if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) {
ram_sz = get_ramsize (&vpd_dram);
}
/*
* Only initialize memory controller when running from FLASH.
* When running from RAM, don't touch it.
*/
if ((ulong) initdram & 0xff000000) {
ulong dimm_bank;
ulong br0_32 = memctl->memc_br0 & 0x400;
switch (speed) {
case 40:
upmconfig (UPMA, (uint *) sdram_table_40,
sizeof (sdram_table_40) / sizeof (uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
memctl->memc_or7 = 0xff800930;
memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
break;
case 50:
upmconfig (UPMA, (uint *) sdram_table_50,
sizeof (sdram_table_50) / sizeof (uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
memctl->memc_or7 = 0xff800940;
memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
break;
default:
hang ();
break;
}
/* now map ram and dimm, largest one first */
dimm_bank = dimm_sz / 2;
if (!dimm_sz) {
memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
memctl->memc_br2 = 0;
memctl->memc_br3 = 0;
} else if (ram_sz > dimm_bank) {
memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81;
memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \
| 0x81;
} else {
memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81;
memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81;
memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81;
}
}
return ram_sz + dimm_sz;
}

+ 0
- 156
board/mbx8xx/pcmcia.c View File

@ -1,156 +0,0 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include "csr.h"
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
/* A lot of this has been taken from the RPX code in this file it works from me.
I have added the voltage selection for the MBX board. */
/* MBX voltage bit in control register #2 */
#define CR2_VPP12 ((uchar)0x10)
#define CR2_VPPVDD ((uchar)0x20)
#define CR2_VDD5 ((uchar)0x40)
#define CR2_VDD3 ((uchar)0x80)
#define PCMCIA_BOARD_MSG "MBX860"
int pcmcia_voltage_set (int slot, int vcc, int vpp)
{
uchar reg = 0;
debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
switch (vcc) {
case 0:
break;
case 33:
reg |= CR2_VDD3;
break;
case 50:
reg |= CR2_VDD5;
break;
default:
return 1;
}
switch (vpp) {
case 0:
break;
case 33:
case 50:
if (vcc == vpp) {
reg |= CR2_VPPVDD;
} else {
return 1;
}
break;
case 120:
reg |= CR2_VPP12;
break;
default:
return 1;
}
/* first, turn off all power */
MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
/* enable new powersettings */
MBX_CSR2 |= reg;
debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
return (0);
}
int pcmcia_hardware_enable (int slot)
{
volatile pcmconf8xx_t *pcmp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
'A' + slot);
udelay (10000);
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (500);
/* remove all power */
pcmcia_voltage_set (slot, 0, 0);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
if ((reg & mask) == mask) {
pcmcia_voltage_set (_slot_, 50, 0);
printf (" 5.0V card found: ");
} else {
pcmcia_voltage_set (_slot_, 33, 0);
printf (" 3.3V card found: ");
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX (_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_hardware_disable (int slot)
{
return 0; /* No hardware to disable */
}
#endif
#endif /* CONFIG_PCMCIA */

+ 0
- 82
board/mbx8xx/u-boot.lds View File

@ -1,82 +0,0 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

+ 0
- 122
board/mbx8xx/u-boot.lds.debug View File

@ -1,122 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

+ 0
- 180
board/mbx8xx/vpd.c View File

@ -1,180 +0,0 @@
/*
* (C) Copyright 2000
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Code in faintly related to linux/arch/powerpc/8xx_io:
* MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
*
* This file implements functions to read the MBX's Vital Product Data
* (VPD). I can't use the more general i2c code in mpc8xx/... since I need
* the VPD at a time where there is no RAM available yet. Hence the VPD is
* read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD).
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_8xx
#include <commproc.h>
#endif
#include "vpd.h"
/* Location of receive/transmit buffer descriptors
* Allocate one transmit bd and one receive bd.
* IIC_BD_FREE points to free bd space which we'll use as tx buffer.
*/
#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t))
#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t))
#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t))
#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t))
/* FIXME -- replace 0x2000 with offsetof */
#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD))
/* transmit/receive buffers */
#define IIC_RX_LENGTH 128
#define WITH_MICROCODE_PATCH
vpd_packet_t * vpd_find_packet(u_char ident)
{
vpd_packet_t *packet;
vpd_t *vpd = VPD_P;
packet = (vpd_packet_t *)&vpd->packets;
while ((packet->identifier != ident) && packet->identifier != 0xFF)
{
packet = (vpd_packet_t *)((char *)packet + packet->size + 2);
}
return packet;
}
void vpd_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
volatile iic_t *iip;
#ifdef WITH_MICROCODE_PATCH
ulong reloc = 0;
#endif
iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
/*
* kludge: when running from flash, no microcode patch can be
* installed. However, the DPMEM usually contains non-zero
* garbage at the relocatable patch base location, so lets clear
* it now. This way the rest of the code can support the microcode
* patch dynamically.
*/
if ((ulong)vpd_init & 0xff000000)
iip->iic_rpbase = 0;
#ifdef WITH_MICROCODE_PATCH
/* Check for and use a microcode relocation patch. */
if ((reloc = iip->iic_rpbase))
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
/* Initialize Port B IIC pins */
cp->cp_pbpar |= 0x00000030;
cp->cp_pbdir |= 0x00000030;
cp->cp_pbodr |= 0x00000030;
i2c->i2c_i2mod = 0x04; /* filter clock */
i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */
i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */
i2c->i2c_i2cmr = 0x00; /* disable interrupts */
i2c->i2c_i2cer = 0x1f; /* clear events */
i2c->i2c_i2com = 0x01; /* configure i2c to work as master */
if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE)
{
hang();
}
}
/* Read from I2C.
* This is a two step process. First, we send the "dummy" write
* to set the device offset for the read. Second, we perform
* the read operation.
*/
int vpd_read(uint iic_device, uchar *buf, int count, int offset)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
volatile iic_t *iip;
volatile cbd_t *tbdf1, *tbdf2, *rbdf;
uchar *tb;
uchar event;
#ifdef WITH_MICROCODE_PATCH
ulong reloc = 0;
#endif
iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
#ifdef WITH_MICROCODE_PATCH
/* Check for and use a microcode relocation patch. */
if ((reloc = iip->iic_rpbase))
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1];
tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2];
rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX];
/* Send a "dummy write" operation. This is a write request with
* only the offset sent, followed by another start condition.
* This will ensure we start reading from the first location
* of the EEPROM.
*/
tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE];
tb[0] = iic_device & 0xfe; /* device address */
tb[1] = offset; /* offset */
tbdf1->cbd_bufaddr = (uint)tb;
tbdf1->cbd_datlen = 2;
tbdf1->cbd_sc = 0x8400;
tb += 2;
tb[0] = iic_device | 1; /* device address */
tbdf2->cbd_bufaddr = (uint)tb;
tbdf2->cbd_datlen = count+1;
tbdf2->cbd_sc = 0xbc00;
rbdf->cbd_bufaddr = (uint)buf;
rbdf->cbd_datlen = 0;
rbdf->cbd_sc = 0xb000;
iip->iic_tbase = IIC_BD_TX1;
iip->iic_tbptr = IIC_BD_TX1;
iip->iic_rbase = IIC_BD_RX;
iip->iic_rbptr = IIC_BD_RX;
iip->iic_rfcr = 0x15;
iip->iic_tfcr = 0x15;
iip->iic_mrblr = count;
iip->iic_rstate = 0;
iip->iic_tstate = 0;
i2c->i2c_i2cer = 0x1f; /* clear event mask */
i2c->i2c_i2mod |= 1; /* enable iic operation */
i2c->i2c_i2com |= 0x80; /* start master */
/* wait for IIC transfer */
do {
__asm__ volatile ("eieio");
event = i2c->i2c_i2cer;
} while (event == 0);
if ((event & 0x10) || (event & 0x04)) {
count = -1;
goto bailout;
}
bailout:
i2c->i2c_i2mod &= ~1; /* turn off iic operation */
i2c->i2c_i2cer = 0x1f; /* clear event mask */
return count;
}

+ 0
- 119
board/mbx8xx/vpd.h View File

@ -1,119 +0,0 @@
#ifndef __vpd_h
#define __vpd_h
/*
* Module name: %M%
* Description:
* Vital Product Data (VPD) Header Module
* SCCS identification: %I%
* Branch: %B%
* Sequence: %S%
* Date newest applied delta was created (MM/DD/YY): %G%
* Time newest applied delta was created (HH:MM:SS): %U%
* SCCS file name %F%
* Fully qualified SCCS file name:
* %P%
* Copyright:
* (C) COPYRIGHT MOTOROLA, INC. 1996
* ALL RIGHTS RESERVED
* Notes:
* History:
* Date Who
*
* 10/24/96 Rob Baxter
* Initial release.
*
*/