Browse Source

powerpc: mpc824x: remove MPC824X cpu support

All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>
imx_3.14.38_6ul_engr
Masahiro Yamada 6 years ago
committed by Tom Rini
parent
commit
d622ac3927
105 changed files with 12 additions and 16821 deletions
  1. +0
    -6
      MAKEALL
  2. +0
    -5
      README
  3. +0
    -4
      arch/powerpc/Kconfig
  4. +0
    -48
      arch/powerpc/cpu/mpc824x/Kconfig
  5. +0
    -11
      arch/powerpc/cpu/mpc824x/Makefile
  6. +0
    -8
      arch/powerpc/cpu/mpc824x/config.mk
  7. +0
    -262
      arch/powerpc/cpu/mpc824x/cpu.c
  8. +0
    -311
      arch/powerpc/cpu/mpc824x/cpu_init.c
  9. +0
    -1
      arch/powerpc/cpu/mpc824x/drivers/epic.h
  10. +0
    -102
      arch/powerpc/cpu/mpc824x/drivers/epic/README
  11. +0
    -163
      arch/powerpc/cpu/mpc824x/drivers/epic/epic.h
  12. +0
    -517
      arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c
  13. +0
    -196
      arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S
  14. +0
    -57
      arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S
  15. +0
    -212
      arch/powerpc/cpu/mpc824x/drivers/errors.h
  16. +0
    -254
      arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c
  17. +0
    -77
      arch/powerpc/cpu/mpc824x/interrupts.c
  18. +0
    -75
      arch/powerpc/cpu/mpc824x/pci.c
  19. +0
    -102
      arch/powerpc/cpu/mpc824x/speed.c
  20. +0
    -724
      arch/powerpc/cpu/mpc824x/start.S
  21. +0
    -194
      arch/powerpc/cpu/mpc824x/traps.c
  22. +0
    -76
      arch/powerpc/cpu/mpc824x/u-boot.lds
  23. +0
    -2
      arch/powerpc/include/asm/processor.h
  24. +0
    -9
      board/a3000/Kconfig
  25. +0
    -6
      board/a3000/MAINTAINERS
  26. +0
    -8
      board/a3000/Makefile
  27. +0
    -17
      board/a3000/README
  28. +0
    -101
      board/a3000/a3000.c
  29. +0
    -438
      board/a3000/flash.c
  30. +0
    -9
      board/cpc45/Kconfig
  31. +0
    -7
      board/cpc45/MAINTAINERS
  32. +0
    -8
      board/cpc45/Makefile
  33. +0
    -250
      board/cpc45/cpc45.c
  34. +0
    -506
      board/cpc45/flash.c
  35. +0
    -128
      board/cpc45/ide.c
  36. +0
    -797
      board/cpc45/pd67290.c
  37. +0
    -156
      board/cpc45/plx9030.c
  38. +0
    -9
      board/cu824/Kconfig
  39. +0
    -6
      board/cu824/MAINTAINERS
  40. +0
    -8
      board/cu824/Makefile
  41. +0
    -453
      board/cu824/README
  42. +0
    -83
      board/cu824/cu824.c
  43. +0
    -470
      board/cu824/flash.c
  44. +0
    -9
      board/eXalion/Kconfig
  45. +0
    -6
      board/eXalion/MAINTAINERS
  46. +0
    -8
      board/eXalion/Makefile
  47. +0
    -283
      board/eXalion/eXalion.c
  48. +0
    -36
      board/eXalion/eXalion.h
  49. +0
    -156
      board/eXalion/piix_pci.h
  50. +0
    -9
      board/musenki/Kconfig
  51. +0
    -6
      board/musenki/MAINTAINERS
  52. +0
    -8
      board/musenki/Makefile
  53. +0
    -298
      board/musenki/README
  54. +0
    -496
      board/musenki/flash.c
  55. +0
    -94
      board/musenki/musenki.c
  56. +0
    -9
      board/mvblue/Kconfig
  57. +0
    -6
      board/mvblue/MAINTAINERS
  58. +0
    -8
      board/mvblue/Makefile
  59. +0
    -570
      board/mvblue/flash.c
  60. +0
    -253
      board/mvblue/mvblue.c
  61. +0
    -86
      board/mvblue/u-boot.lds
  62. +0
    -19
      board/sandpoint/Kconfig
  63. +0
    -12
      board/sandpoint/MAINTAINERS
  64. +0
    -8
      board/sandpoint/Makefile
  65. +0
    -411
      board/sandpoint/README
  66. +0
    -2
      board/sandpoint/dinkdl
  67. +0
    -748
      board/sandpoint/flash.c
  68. +0
    -91
      board/sandpoint/sandpoint.c
  69. +0
    -84
      board/sandpoint/u-boot.lds
  70. +0
    -9
      board/utx8245/Kconfig
  71. +0
    -6
      board/utx8245/MAINTAINERS
  72. +0
    -13
      board/utx8245/Makefile
  73. +0
    -544
      board/utx8245/flash.c
  74. +0
    -119
      board/utx8245/utx8245.c
  75. +0
    -3
      common/cmd_pcmcia.c
  76. +0
    -3
      configs/A3000_defconfig
  77. +0
    -4
      configs/CPC45_ROMBOOT_defconfig
  78. +0
    -3
      configs/CPC45_defconfig
  79. +0
    -3
      configs/CU824_defconfig
  80. +0
    -3
      configs/MUSENKI_defconfig
  81. +0
    -3
      configs/MVBLUE_defconfig
  82. +0
    -3
      configs/Sandpoint8240_defconfig
  83. +0
    -3
      configs/Sandpoint8245_defconfig
  84. +0
    -3
      configs/eXalion_defconfig
  85. +0
    -3
      configs/utx8245_defconfig
  86. +9
    -0
      doc/README.scrapyard
  87. +0
    -1
      drivers/pcmcia/Makefile
  88. +0
    -989
      drivers/pcmcia/i82365.c
  89. +0
    -293
      include/configs/A3000.h
  90. +0
    -489
      include/configs/CPC45.h
  91. +0
    -286
      include/configs/CU824.h
  92. +0
    -275
      include/configs/MUSENKI.h
  93. +0
    -325
      include/configs/MVBLUE.h
  94. +0
    -398
      include/configs/Sandpoint8240.h
  95. +0
    -376
      include/configs/Sandpoint8245.h
  96. +0
    -433
      include/configs/eXalion.h
  97. +0
    -408
      include/configs/utx8245.h
  98. +0
    -523
      include/mpc824x.h
  99. +0
    -4
      include/pci.h
  100. +0
    -180
      include/pcmcia/cirrus.h

+ 0
- 6
MAKEALL View File

@ -291,12 +291,6 @@ LIST_8xx="$(targets_by_cpu mpc8xx)"
LIST_4xx="$(targets_by_cpu ppc4xx)"
#########################################################################
## MPC824x Systems
#########################################################################
LIST_824x="$(targets_by_cpu mpc824x)"
#########################################################################
## MPC8260 Systems (includes 8250, 8255 etc.)
#########################################################################


+ 0
- 5
README View File

@ -186,7 +186,6 @@ Directory Hierarchy:
/mpc5xx Files specific to Freescale MPC5xx CPUs
/mpc5xxx Files specific to Freescale MPC5xxx CPUs
/mpc8xx Files specific to Freescale MPC8xx CPUs
/mpc824x Files specific to Freescale MPC824x CPUs
/mpc8260 Files specific to Freescale MPC8260 CPUs
/mpc85xx Files specific to Freescale MPC85xx CPUs
/ppc4xx Files specific to AMCC PowerPC 4xx CPUs
@ -326,10 +325,6 @@ The following options need to be configured:
multiple fs option at one time
for marvell soc family
- MPC824X Family Member (if CONFIG_MPC824X is defined)
Define exactly one of
CONFIG_MPC8240, CONFIG_MPC8245
- 8xx CPU Options: (if using an MPC8xx CPU)
CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
get_gclk_freq() cannot work


+ 0
- 4
arch/powerpc/Kconfig View File

@ -19,9 +19,6 @@ config 5xx
config MPC5xxx
bool "MPC5xxx"
config MPC824X
bool "MPC824X"
config MPC8260
bool "MPC8260"
@ -46,7 +43,6 @@ source "arch/powerpc/cpu/74xx_7xx/Kconfig"
source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xx/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
source "arch/powerpc/cpu/mpc824x/Kconfig"
source "arch/powerpc/cpu/mpc8260/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"


+ 0
- 48
arch/powerpc/cpu/mpc824x/Kconfig View File

@ -1,48 +0,0 @@
menu "mpc824x CPU"
depends on MPC824X
config SYS_CPU
default "mpc824x"
choice
prompt "Target select"
config TARGET_A3000
bool "Support A3000"
config TARGET_CPC45
bool "Support CPC45"
config TARGET_CU824
bool "Support CU824"
config TARGET_EXALION
bool "Support eXalion"
config TARGET_MUSENKI
bool "Support MUSENKI"
config TARGET_MVBLUE
bool "Support MVBLUE"
config TARGET_SANDPOINT8240
bool "Support Sandpoint8240"
config TARGET_SANDPOINT8245
bool "Support Sandpoint8245"
config TARGET_UTX8245
bool "Support utx8245"
endchoice
source "board/a3000/Kconfig"
source "board/cpc45/Kconfig"
source "board/cu824/Kconfig"
source "board/eXalion/Kconfig"
source "board/musenki/Kconfig"
source "board/mvblue/Kconfig"
source "board/sandpoint/Kconfig"
source "board/utx8245/Kconfig"
endmenu

+ 0
- 11
arch/powerpc/cpu/mpc824x/Makefile View File

@ -1,11 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \
drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
obj-y += ../mpc8260/bedbug_603e.o

+ 0
- 8
arch/powerpc/cpu/mpc824x/config.mk View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -mstring -mcpu=603e -msoft-float

+ 0
- 262
arch/powerpc/cpu/mpc824x/cpu.c View File

@ -1,262 +0,0 @@
/*
* (C) Copyright 2000 - 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <mpc824x.h>
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
unsigned int pvr = get_pvr ();
unsigned int version = pvr >> 16;
unsigned char revision;
ulong clock = gd->cpu_clk;
char buf[32];
puts ("CPU: ");
switch (version) {
case CPU_TYPE_8240:
puts ("MPC8240");
break;
case CPU_TYPE_8245:
puts ("MPC8245");
break;
default:
return -1; /*not valid for this source */
}
CONFIG_READ_BYTE (REVID, revision);
if (revision) {
printf (" Revision %d.%d",
(revision & 0xf0) >> 4,
(revision & 0x0f));
} else {
return -1; /* no valid CPU revision info */
}
printf(" at %s MHz: ", strmhz(buf, clock));
print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache\n");
return 0;
}
/* ------------------------------------------------------------------------- */
/* L1 i-cache */
int checkicache (void)
{
/*TODO*/
return 128 * 4 * 32;
};
/* ------------------------------------------------------------------------- */
/* L1 d-cache */
int checkdcache (void)
{
/*TODO*/
return 128 * 4 * 32;
};
/*------------------------------------------------------------------- */
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;
/* Interrupts and MMU off */
__asm__ ("mtspr 81, 0");
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~0x1030;
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
#ifdef CONFIG_SYS_RESET_ADDRESS
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
* address. Better pick an address known to be invalid on
* your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
}
/* ------------------------------------------------------------------------- */
/*
* Get timebase clock frequency (like cpu_clk in Hz)
* This is the sys_logic_clk (memory bus) divided by 4
*/
unsigned long get_tbclk (void)
{
return ((get_bus_freq (0) + 2L) / 4L);
}
/* ------------------------------------------------------------------------- */
/*
* The MPC824x has an integrated PCI controller known as the MPC107.
* The following are MPC107 Bridge Controller and PCI Support functions
*
*/
/*
* This procedure reads a 32-bit address MPC107 register, and returns
* a 32 bit value. It swaps the address to little endian before
* writing it to config address, and swaps the value to big endian
* before returning to the caller.
*/
unsigned int mpc824x_mpc107_getreg (unsigned int regNum)
{
unsigned int temp;
/* swap the addr. to little endian */
*(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum);
temp = *(volatile unsigned int *) CHRP_REG_DATA;
return PCISWAP (temp); /* swap the data upon return */
}
/*
* This procedure writes a 32-bit address MPC107 register. It swaps
* the address to little endian before writing it to config address.
*/
void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal)
{
/* swap the addr. to little endian */
*(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum);
*(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal);
return;
}
/*
* Write a byte (8 bits) to a memory location.
*/
void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data)
{
*(unsigned char *) addr = data;
__asm__ ("sync");
}
/*
* Write a word (16 bits) to a memory location after the value
* has been byte swapped (big to little endian or vice versa)
*/
void mpc824x_mpc107_write16 (unsigned int address, unsigned short data)
{
*(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data);
__asm__ ("sync");
}
/*
* Write a long word (32 bits) to a memory location after the value
* has been byte swapped (big to little endian or vice versa)
*/
void mpc824x_mpc107_write32 (unsigned int address, unsigned int data)
{
*(volatile unsigned int *) address = LONGSWAP (data);
__asm__ ("sync");
}
/*
* Read a byte (8 bits) from a memory location.
*/
unsigned char mpc824x_mpc107_read8 (unsigned int addr)
{
return *(volatile unsigned char *) addr;
}
/*
* Read a word (16 bits) from a memory location, and byte swap the
* value before returning to the caller.
*/
unsigned short mpc824x_mpc107_read16 (unsigned int address)
{
unsigned short retVal;
retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address);
return retVal;
}
/*
* Read a long word (32 bits) from a memory location, and byte
* swap the value before returning to the caller.
*/
unsigned int mpc824x_mpc107_read32 (unsigned int address)
{
unsigned int retVal;
retVal = LONGSWAP (*(unsigned int *) address);
return (retVal);
}
/*
* Read a register in the Embedded Utilities Memory Block address
* space.
* Input: regNum - register number + utility base address. Example,
* the base address of EPIC is 0x40000, the register number
* being passed is 0x40000+the address of the target register.
* (See epic.h for register addresses).
* Output: The 32 bit little endian value of the register.
*/
unsigned int mpc824x_eummbar_read (unsigned int regNum)
{
unsigned int temp;
temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum);
temp = PCISWAP (temp);
return temp;
}
/*
* Write a value to a register in the Embedded Utilities Memory
* Block address space.
* Input: regNum - register number + utility base address. Example,
* the base address of EPIC is 0x40000, the register
* number is 0x40000+the address of the target register.
* (See epic.h for register addresses).
* regVal - value to be written to the register.
*/
void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal)
{
*(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal);
return;
}
/* ------------------------------------------------------------------------- */

+ 0
- 311
arch/powerpc/cpu/mpc824x/cpu_init.c View File

@ -1,311 +0,0 @@
/*
* (C) Copyright 2000
* Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <mpc824x.h>
#ifndef CONFIG_SYS_BANK0_ROW
#define CONFIG_SYS_BANK0_ROW 0
#endif
#ifndef CONFIG_SYS_BANK1_ROW
#define CONFIG_SYS_BANK1_ROW 0
#endif
#ifndef CONFIG_SYS_BANK2_ROW
#define CONFIG_SYS_BANK2_ROW 0
#endif
#ifndef CONFIG_SYS_BANK3_ROW
#define CONFIG_SYS_BANK3_ROW 0
#endif
#ifndef CONFIG_SYS_BANK4_ROW
#define CONFIG_SYS_BANK4_ROW 0
#endif
#ifndef CONFIG_SYS_BANK5_ROW
#define CONFIG_SYS_BANK5_ROW 0
#endif
#ifndef CONFIG_SYS_BANK6_ROW
#define CONFIG_SYS_BANK6_ROW 0
#endif
#ifndef CONFIG_SYS_BANK7_ROW
#define CONFIG_SYS_BANK7_ROW 0
#endif
#ifndef CONFIG_SYS_DBUS_SIZE2
#define CONFIG_SYS_DBUS_SIZE2 0
#endif
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
*/
void
cpu_init_f (void)
{
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
#if defined(CONFIG_MUSENKI)
/* Why is this here, you ask? Try, just try setting 0x8000
* in PCIACR with CONFIG_WRITE_HALFWORD()
* this one was a stumper, and we are annoyed
*/
#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
__asm__ __volatile__(" \
stw %2,0(%0)\n \
sync\n \
sth %3,2(%1)\n \
sync\n \
" \
: /* no output */ \
: "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
);
M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
#endif
CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
/*
* Note that although this bit is cleared after a hard reset, it
* must be explicitly set and then cleared by software during
* initialization in order to guarantee correct operation of the
* DLL and the SDRAM_CLK[0:3] signals (if they are used).
*/
CONFIG_READ_BYTE (AMBOR, val);
CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
#ifdef CONFIG_MPC8245
/* silicon bug 28 MPC8245 */
CONFIG_READ_BYTE(AMBOR,val);
CONFIG_WRITE_BYTE(AMBOR,val|0x1);
#if 0
/*
* The following bug only affects older (XPC8245) processors.
* DMA transfers initiated by external devices get corrupted due
* to a hardware scheduling problem.
*
* The effect is:
* when transferring X words, the first 32 words are transferred
* OK, the next 3 x 32 words are 'old' data (from previous DMA)
* while the rest of the X words is xferred fine.
*
* Disabling 3 of the 4 32 word hardware buffers solves the problem
* with no significant performance loss.
*/
CONFIG_READ_BYTE(PCMBCR,val);
/* in order not to corrupt data which is being read over the PCI bus
* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
* 4.11 in the processor user manual
* */
#if 1
CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
#else
CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
/* default, 4 PCMRBs are used */
#endif
#endif
#endif
CONFIG_READ_WORD(PICR1, val);
#if defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD( PICR1,
(val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
PIRC1_MSK | PICR1_PROC_TYPE_603E |
PICR1_FLASH_WR_EN | PICR1_MCP_EN |
PICR1_CF_DPARK | PICR1_EN_PCS |
PICR1_CF_APARK );
#elif defined(CONFIG_MPC8245)
CONFIG_WRITE_WORD( PICR1,
(val & (PICR1_RCS0)) |
PICR1_PROC_TYPE_603E |
PICR1_FLASH_WR_EN | PICR1_MCP_EN |
PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
CONFIG_READ_WORD(PICR2, val);
val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
CONFIG_WRITE_WORD(PICR2, val);
CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
#ifndef CONFIG_SYS_RAMBOOT
CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
(CONFIG_SYS_BANK0_ROW) |
(CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
(CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
(CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
(CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
(CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
(CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
(CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
(CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif
#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
#else
CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
#endif
#if defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD(MCCR3,
(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
(CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
#elif defined(CONFIG_MPC8245)
CONFIG_WRITE_WORD(MCCR3,
(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
/* this is gross. We think these should all be the same, and various boards
* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
* its not set, we define it to zero in this file
*/
#if defined(CONFIG_CU824)
CONFIG_WRITE_WORD(MCCR4,
(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
MCCR4_BIT21 |
(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
#elif defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD(MCCR4,
(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
MCCR4_BIT21 |
(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
(CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#elif defined(CONFIG_MPC8245)
CONFIG_READ_WORD(MCCR1, val);
val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
CONFIG_WRITE_WORD(MCCR4,
(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
(val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
CONFIG_WRITE_WORD(MSAR1,
( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMSAR1,
( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(MSAR2,
( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMSAR2,
( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(MEAR1,
( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMEAR1,
( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(MEAR2,
( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMEAR2,
( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
#ifdef CONFIG_SYS_DLL_MAX_DELAY
CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
#endif
#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
#endif
#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
#endif /* setup & hold time */
CONFIG_WRITE_BYTE(MBER,
CONFIG_SYS_BANK0_ENABLE |
(CONFIG_SYS_BANK1_ENABLE << 1) |
(CONFIG_SYS_BANK2_ENABLE << 2) |
(CONFIG_SYS_BANK3_ENABLE << 3) |
(CONFIG_SYS_BANK4_ENABLE << 4) |
(CONFIG_SYS_BANK5_ENABLE << 5) |
(CONFIG_SYS_BANK6_ENABLE << 6) |
(CONFIG_SYS_BANK7_ENABLE << 7));
#ifdef CONFIG_SYS_PGMAX
CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
#endif
/* ! Wait 200us before initialize other registers */
/*FIXME: write a decent udelay wait */
__asm__ __volatile__(
" mtctr %0 \n \
0: bdnz 0b\n"
:
: "r" (0x10000));
CONFIG_READ_WORD(MCCR1, val);
CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
__asm__ __volatile__("eieio");
}
/*
* initialize higher level parts of CPU like time base and timers
*/
int cpu_init_r (void)
{
return (0);
}

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- 1
arch/powerpc/cpu/mpc824x/drivers/epic.h View File

@ -1 +0,0 @@
#include "epic/epic.h"

+ 0
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arch/powerpc/cpu/mpc824x/drivers/epic/README View File

@ -1,102 +0,0 @@
CONTENT:
epic.h
epic1.c
epic2.s
WHAT ARE THESE FILES:
These files contain MPC8240 (Kahlua) EPIC
driver routines. The driver routines are not
written for any specific operating system.
They serves the purpose of code sample, and
jump-start for using the MPC8240 EPIC unit.
For the reason of correctness of C language
syntax, these files are compiled by Metaware
C compiler and assembler.
ENDIAN NOTATION:
The algorithm is designed for big-endian mode,
software is responsible for byte swapping.
USAGE:
1. The host system that is running on MPC8240
shall link the files listed here. The memory
location of driver routines shall take into
account of that driver routines need to run
in supervisor mode and they process external
interrupts.
The routine epic_exception shall be called by
exception vector at location 0x500, i.e.,
603e core external exception vector.
2. The host system is responsible for configuring
the MPC8240 including Embedded Utilities Memory
Block. All EPIC driver functions require the
content of Embedded Utilities Memory Block
Base Address Register, EUMBBAR, as the first
parameter.
3. Before EPIC unit of MPC8240 can be used,
initialize EPIC unit by calling epicInit
with the corresponding parameters.
The initialization shall disable the 603e
core External Exception by calling CoreExtIntDisable( ).
Next, call epicInit( ). Last, enable the 603e core
External Exception by calling CoreExtIntEnable( ).
4. After EPIC unit has been successfully initialized,
epicIntSourceSet( ) shall be used to register each
external interrupt source. Anytime, an external
interrupt source can be disabled or enabled by
calling corresponding function, epicIntDisable( ),
or epicIntEnable( ).
Global Timers' resource, base count and frequency,
can be changed by calling epicTmFrequencySet( )
and epicTmBaseSet( ).
To stop counting a specific global timer, use
the function, epicTmInhibit while epicTmEnable
can be used to start counting a timer.
5. To mask a set of external interrupts that are
are certain level below, epicIntPrioritySet( )
can be used. For example, if the processor's
current task priority register is set to 0x7,
only interrupts of priority 0x8 or higher will
be passed to the processor.
Be careful when using this function. It may
corrupt the current interrupt pending, selector,
and request registers, resulting an invalid vetor.
After enabling an interrupt, disable it may also
cause an invalid vector. User may consider using
the spurious vector interrupt service routine to
handle this case.
6. The EPIC driver routines contains a set
of utilities, Set and Get, for host system
to query and modify the desired EPIC source
registers.
7. Each external interrupt source shall register
its interrupt service routine. The routine
shall contain all interrupt source specific
processes and keep as short as possible.
Special customized end of interrupt routine
is optional. If it is needed, it shall contain
the external interrupt source specific end of
interrupt process.
External interrupt exception vector at 0x500
shall always call the epicEOI just before
rfi instruction. Refer to the routine,
epic_exception, for a code sample.

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arch/powerpc/cpu/mpc824x/drivers/epic/epic.h View File

@ -1,163 +0,0 @@
/*********************************************************************
* mpc8240epic.h - EPIC module of the MPC8240 micro-controller
*
* Copyrigh 1999 Motorola Inc.
*
* Modification History:
* =====================
* 01a,04Feb99,My Created.
* 15Nov200, robt -modified to use in U-Boot
*
*/
#ifndef __INCEPICh
#define __INCEPICh
#define ULONG unsigned long
#define MAXVEC 20
#define MAXIRQ 5 /* IRQs */
#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */
/* EPIC register addresses */
#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */
#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */
#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */
#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */
#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */
#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */
#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */
#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */
#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/
#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/
#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/
#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */
#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/
#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/
#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/
#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */
#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/
#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/
#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/
#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */
#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/
#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/
#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/
#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */
#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */
#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/
#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */
#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/
#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */
#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/
#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */
#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/
#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */
#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/
#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */
#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */
#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */
#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/
#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */
#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/
#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */
#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/
#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */
#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/
#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */
#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/
#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */
#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/
#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */
#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/
#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */
#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/
#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */
#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/
#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */
#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/
#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */
#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/
#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */
#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/
#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */
#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/
#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */
#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/
#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */
#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/
#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/
#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */
#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/
#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */
#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/
#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */
#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/
#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */
#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/
#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */
#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */
/* Error code */
#define OK 0
#define ERROR -1
/* function prototypes */
void epicVendorId( unsigned int *step,
unsigned int *devId,
unsigned int *venId
);
void epicFeatures( unsigned int *noIRQs,
unsigned int *noCPUs,
unsigned int *VerId );
extern void epicInit( unsigned int IRQType, unsigned int clkRatio);
ULONG sysEUMBBARRead ( ULONG regNum );
void sysEUMBBARWrite ( ULONG regNum, ULONG regVal);
extern void epicTmFrequencySet( unsigned int frq );
extern unsigned int epicTmFrequencyGet(void);
extern unsigned int epicTmBaseSet( ULONG srcAddr,
unsigned int cnt,
unsigned int inhibit );
extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val );
extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val );
extern unsigned int epicTmInhibit( unsigned int timer );
extern unsigned int epicTmEnable( ULONG srcAdr );
extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */
extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */
extern unsigned char epicIntTaskGet(void);
extern void epicIntTaskSet( unsigned char val );
extern unsigned int epicIntAck(void);
extern void epicSprSet( unsigned int eumbbar, unsigned char );
extern void epicConfigGet( unsigned int *clkRatio,
unsigned int *serEnable );
extern void SrcVecTableInit(void);
extern unsigned int epicModeGet(void);
extern void epicIntEnable(int Vect);
extern void epicIntDisable(int Vect);
extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio);
extern unsigned int epicIntAck(void);
extern void epicEOI(void);
extern int epicCurTaskPrioSet(int Vect);
struct SrcVecTable
{
ULONG srcAddr;
char srcName[40];
};
#endif /* EPIC_H */

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arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c View File

@ -1,517 +0,0 @@
/**************************************************
*
* copyright @ motorola, 1999
*
*************************************************/
#include <mpc824x.h>
#include <common.h>
#include "epic.h"
#define PRINT(format, args...) printf(format , ## args)
typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */
struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */
{
{ EPIC_EX_INT0_VEC_REG, "External Direct/Serial Source 0"},
{ EPIC_EX_INT1_VEC_REG, "External Direct/Serial Source 1"},
{ EPIC_EX_INT2_VEC_REG, "External Direct/Serial Source 2"},
{ EPIC_EX_INT3_VEC_REG, "External Direct/Serial Source 3"},
{ EPIC_EX_INT4_VEC_REG, "External Direct/Serial Source 4"},
{ EPIC_SR_INT5_VEC_REG, "External Serial Source 5"},
{ EPIC_SR_INT6_VEC_REG, "External Serial Source 6"},
{ EPIC_SR_INT7_VEC_REG, "External Serial Source 7"},
{ EPIC_SR_INT8_VEC_REG, "External Serial Source 8"},
{ EPIC_SR_INT9_VEC_REG, "External Serial Source 9"},
{ EPIC_SR_INT10_VEC_REG, "External Serial Source 10"},
{ EPIC_SR_INT11_VEC_REG, "External Serial Source 11"},
{ EPIC_SR_INT12_VEC_REG, "External Serial Source 12"},
{ EPIC_SR_INT13_VEC_REG, "External Serial Source 13"},
{ EPIC_SR_INT14_VEC_REG, "External Serial Source 14"},
{ EPIC_SR_INT15_VEC_REG, "External Serial Source 15"},
{ EPIC_I2C_INT_VEC_REG, "Internal I2C Source"},
{ EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"},
{ EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"},
{ EPIC_MSG_INT_VEC_REG, "Internal Message Source"},
};
VOIDFUNCPTR intVecTbl[MAXVEC]; /* Interrupt vector table */
/****************************************************************************
* epicInit - Initialize the EPIC registers
*
* This routine resets the Global Configuration Register, thus it:
* - Disables all interrupts
* - Sets epic registers to reset values
* - Sets the value of the Processor Current Task Priority to the
* highest priority (0xF).
* epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass
* Through or 8259 compatible mode).
*
* If IRQType (input) is Direct IRQs:
* - IRQType is written to the SIE bit of the EPIC Interrupt
* Configuration register (ICR).
* - clkRatio is ignored.
* If IRQType is Serial IRQs:
* - both IRQType and clkRatio will be written to the ICR register
*/
void epicInit
(
unsigned int IRQType, /* Direct or Serial */
unsigned int clkRatio /* Clk Ratio for Serial IRQs */
)
{
ULONG tmp;
tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
tmp |= 0xa0000000; /* Set the Global Conf. register */
sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
/*
* Wait for EPIC to reset - CLH
*/
while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */
if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */
sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
else /* Serial mode */
{
tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */
sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
}
while (epicIntAck() != 0xff) /* Clear all pending interrupts */
epicEOI();
}
/****************************************************************************
* epicIntEnable - Enable an interrupt source
*
* This routine clears the mask bit of an external, an internal or
* a Timer register to enable the interrupt.
*
* RETURNS: None
*/
void epicIntEnable(int intVec)
{
ULONG tmp;
ULONG srAddr;
srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */
tmp = sysEUMBBARRead(srAddr);
tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */
tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */
tmp |= intVec; /* Set Vector number */
sysEUMBBARWrite(srAddr, tmp);
return;
}
/****************************************************************************
* epicIntDisable - Disable an interrupt source
*
* This routine sets the mask bit of an external, an internal or
* a Timer register to disable the interrupt.
*
* RETURNS: OK or ERROR
*
*/
void epicIntDisable
(
int intVec /* Interrupt vector number */
)
{
ULONG tmp, srAddr;
srAddr = SrcVecTable[intVec].srcAddr;
tmp = sysEUMBBARRead(srAddr);
tmp |= 0x80000000; /* Set the mask bit */
sysEUMBBARWrite(srAddr, tmp);
return;
}
/****************************************************************************
* epicIntSourceConfig - Set properties of an interrupt source
*
* This function sets interrupt properites (Polarity, Sense, Interrupt
* Prority, and Interrupt Vector) of an Interrupt Source. The properties
* can be set when the current source is not in-request or in-service,
* which is determined by the Activity bit. This routine return ERROR
* if the the Activity bit is 1 (in-request or in-service).
*
* This function assumes that the Source Vector/Priority register (input)
* is a valid address.
*
* RETURNS: OK or ERROR
*/
int epicIntSourceConfig
(
int Vect, /* interrupt source vector number */
int Polarity, /* interrupt source polarity */
int Sense, /* interrupt source Sense */
int Prio /* interrupt source priority */
)
{
ULONG tmp, newVal;
ULONG actBit, srAddr;
srAddr = SrcVecTable[Vect].srcAddr;
tmp = sysEUMBBARRead(srAddr);
actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */
if (actBit == 1)
return ERROR;
tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */
newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect;
sysEUMBBARWrite(srAddr, tmp | newVal );
return (OK);
}
/****************************************************************************
* epicIntAck - acknowledge an interrupt
*
* This function reads the Interrupt acknowldge register and return
* the vector number of the highest pending interrupt.
*
* RETURNS: Interrupt Vector number.
*/
unsigned int epicIntAck(void)
{
return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG ));
}
/****************************************************************************
* epicEOI - signal an end of interrupt
*
* This function writes 0x0 to the EOI register to signal end of interrupt.
* It is usually called after an interrupt routine is served.
*
* RETURNS: None
*/
void epicEOI(void)
{
sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0);
}
/****************************************************************************
* epicCurTaskPrioSet - sets the priority of the Processor Current Task
*
* This function should be called after epicInit() to lower the priority
* of the processor current task.
*
* RETURNS: OK or ERROR
*/
int epicCurTaskPrioSet
(
int prioNum /* New priority value */
)
{
if ( (prioNum < 0) || (prioNum > 0xF))
return ERROR;
sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum);
return OK;
}
/************************************************************************
* function: epicIntTaskGet
*
* description: Get value of processor current interrupt task priority register
*
* note:
***********************************************************************/
unsigned char epicIntTaskGet()
{
/* get the interrupt task priority register */
ULONG reg;
unsigned char rec;
reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG );
rec = ( reg & 0x0F );
return rec;
}
/**************************************************************
* function: epicISR
*
* description: EPIC service routine called by the core exception
* at 0x500
*
* note:
**************************************************************/
unsigned int epicISR(void)
{
return 0;
}
/************************************************************
* function: epicModeGet
*
* description: query EPIC mode, return 0 if pass through mode
* return 1 if mixed mode
*
* note:
*************************************************************/
unsigned int epicModeGet(void)
{
ULONG val;
val = sysEUMBBARRead( EPIC_GLOBAL_REG );
return (( val & 0x20000000 ) >> 29);
}
/*********************************************
* function: epicConfigGet
*
* description: Get the EPIC interrupt Configuration
* return 0 if not error, otherwise return 1
*
* note:
********************************************/
void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable)
{
ULONG val;
val = sysEUMBBARRead( EPIC_INT_CONF_REG );
*clkRatio = ( val & 0x70000000 ) >> 28;
*serEnable = ( val & 0x8000000 ) >> 27;
}
/*******************************************************************
* sysEUMBBARRead - Read a 32-bit EUMBBAR register
*
* This routine reads the content of a register in the Embedded
* Utilities Memory Block, and swaps to big endian before returning
* the value.
*
* RETURNS: The content of the specified EUMBBAR register.
*/
ULONG sysEUMBBARRead
(
ULONG regNum
)
{
ULONG temp;
temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum);
return ( LONGSWAP(temp));
}
/*******************************************************************
* sysEUMBBARWrite - Write a 32-bit EUMBBAR register
*
* This routine swaps the value to little endian then writes it to
* a register in the Embedded Utilities Memory Block address space.
*
* RETURNS: N/A
*/
void sysEUMBBARWrite
(
ULONG regNum, /* EUMBBAR register address */
ULONG regVal /* Value to be written */
)
{
*(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal);
return ;
}
/********************************************************
* function: epicVendorId
*
* description: return the EPIC Vendor Identification
* register:
*
* siliccon version, device id, and vendor id
*
* note:
********************************************************/
void epicVendorId
(
unsigned int *step,
unsigned int *devId,
unsigned int *venId
)
{
ULONG val;
val = sysEUMBBARRead( EPIC_VENDOR_ID_REG );
*step = ( val & 0x00FF0000 ) >> 16;
*devId = ( val & 0x0000FF00 ) >> 8;
*venId = ( val & 0x000000FF );
}
/**************************************************
* function: epicFeatures
*
* description: return the number of IRQ supported,
* number of CPU, and the version of the
* OpenEPIC
*
* note:
*************************************************/
void epicFeatures
(
unsigned int *noIRQs,
unsigned int *noCPUs,
unsigned int *verId
)
{
ULONG val;
val = sysEUMBBARRead( EPIC_FEATURES_REG );
*noIRQs = ( val & 0x07FF0000 ) >> 16;
*noCPUs = ( val & 0x00001F00 ) >> 8;
*verId = ( val & 0x000000FF );
}
/*********************************************************
* function: epciTmFrequncySet
*
* description: Set the timer frequency reporting register
********************************************************/
void epicTmFrequencySet( unsigned int frq )
{
sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq);
}
/*******************************************************
* function: epicTmFrequncyGet
*
* description: Get the current value of the Timer Frequency
* Reporting register
*
******************************************************/
unsigned int epicTmFrequencyGet(void)
{
return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ;
}
/****************************************************
* function: epicTmBaseSet
*
* description: Set the #n global timer base count register
* return 0 if no error, otherwise return 1.
*
* note:
****************************************************/
unsigned int epicTmBaseSet
(
ULONG srcAddr, /* Address of the Timer Base register */
unsigned int cnt, /* Base count */
unsigned int inhibit /* 1 - count inhibit */
)
{
unsigned int val = 0x80000000;
/* First inhibit counting the timer */
sysEUMBBARWrite(srcAddr, val) ;
/* set the new value */
val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31);
sysEUMBBARWrite(srcAddr, val) ;
return 0;
}
/***********************************************************************
* function: epicTmBaseGet
*
* description: Get the current value of the global timer base count register
* return 0 if no error, otherwise return 1.
*
* note:
***********************************************************************/
unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val )
{
*val = sysEUMBBARRead( srcAddr );
*val = *val & 0x7fffffff;
return 0;
}
/***********************************************************
* function: epicTmCountGet
*
* description: Get the value of a given global timer
* current count register
* return 0 if no error, otherwise return 1
* note:
**********************************************************/
unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val )
{
*val = sysEUMBBARRead( srcAddr );
*val = *val & 0x7fffffff;
return 0;
}
/***********************************************************
* function: epicTmInhibit
*
* description: Stop counting of a given global timer
* return 0 if no error, otherwise return 1
*
* note:
***********************************************************/
unsigned int epicTmInhibit( unsigned int srcAddr )
{
ULONG val;
val = sysEUMBBARRead( srcAddr );
val |= 0x80000000;
sysEUMBBARWrite( srcAddr, val );
return 0;
}
/******************************************************************
* function: epicTmEnable
*
* description: Enable counting of a given global timer
* return 0 if no error, otherwise return 1
*
* note:
*****************************************************************/
unsigned int epicTmEnable( ULONG srcAddr )
{
ULONG val;
val = sysEUMBBARRead( srcAddr );
val &= 0x7fffffff;
sysEUMBBARWrite( srcAddr, val );
return 0;
}
void epicSourcePrint(int Vect)
{
ULONG srcVal;
srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr);
PRINT("%s\n", SrcVecTable[Vect].srcName);
PRINT("Address = 0x%lx\n", SrcVecTable[Vect].srcAddr);
PRINT("Vector = %ld\n", (srcVal & 0x000000FF) );
PRINT("Mask = %ld\n", srcVal >> 31);
PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30);
PRINT("Polarity = %ld\n", (srcVal & 0x00800000) >> 23);
PRINT("Sense = %ld\n", (srcVal & 0x00400000) >> 22);
PRINT("Priority = %ld\n", (srcVal & 0x000F0000) >> 16);
}

+ 0
- 196
arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S View File

@ -1,196 +0,0 @@
/**************************************
*
* copyright @ Motorola, 1999
*
**************************************/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/processor.h>
/*********************************************
* function: CoreExtIntEnable
*
* description: Enable 603e core external interrupt
*
* note: mtmsr is context-synchronization
**********************************************/
.text
.align 2
.global CoreExtIntEnable
CoreExtIntEnable:
mfmsr r3
ori r3,r3,0x8000 /* enable external interrupt */
mtmsr r3
bclr 20, 0
/*******************************************
* function: CoreExtIntDisable
*
* description: Disable 603e core external interrupt
*
* note:
*******************************************/
.text
.align 2
.global CoreExtIntDisable
CoreExtIntDisable:
mfmsr r4
xor r3,r3,r3
or r3,r3,r4
andis. r4,r4,0xffff
andi. r3,r3,0x7fff /* disable external interrupt */
or r3,r3,r4
mtmsr r3
bclr 20, 0
/*********************************************************
* function: epicEOI
*
* description: signal the EOI and restore machine status
* Input: r3 - value of eumbbar
* Output: r3 - value of eumbbar
* r4 - ISR vector value
* note:
****************************