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HMI1001: add support for MPC5200 Rev. B processors.

Signed-off-by: Wolfgang Denk <wd@denx.de>
imx_v2009.08_10.04.01
Wolfgang Denk 13 years ago
parent
commit
c6dc21c84d
1 changed files with 18 additions and 0 deletions
  1. +18
    -0
      board/hmi1001/hmi1001.c

+ 18
- 0
board/hmi1001/hmi1001.c View File

@ -147,6 +147,24 @@ long int initdram (int board_type)
#endif /* CFG_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
}
/* return dramsize + dramsize2; */
return dramsize;
}


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