Commit c4fcc045 by Jose Miquel Sanabria

Added support for:

* MMC * Ethernet * Eeprom * USB OTG * USB Host * DRAM Samsung 4 Gb
parent 9df58728
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* Common resources for igep boards
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __COMMON_HEADER__
#define __COMMON_HEADER__
struct igep_mf_setup {
u32 magic_id; /* eeprom magic id */
u32 crc32; /* eeprom crc32 */
char board_uuid [37]; /* board identifier */
char board_pid [20]; /* product identifier */
char name [20]; /* board name */
char model [10]; /* board model */
char pcb_version [10]; /* board version */
char assembly_rev[10]; /* board revision */
char board_manufacturer[30]; /* board manufacturer */
char manf_of[10]; /* manufacturer order of fabrication */
char manf_timestamp[16]; /* manufacturer timestamp */
char bmac0[6]; /* MAC 0 - default */
char bmac1[6]; /* MAC 1 */
}__attribute__((packet));
#endif
......@@ -6,5 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_IGEP0046_CFG_EEPROM) += igep0046_eeprom.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-y += igep0046.o
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* EEPROM support source file for igep0046
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/sys_proto.h>
int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_write(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
udelay(5000);
}
if(remain > 0){
if(i2c_write(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
else
udelay(5000);
}
return 0;
}
int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_read(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
}
if(remain > 0)
if(i2c_read(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
return 0;
}
int check_eeprom (void)
{
i2c_set_bus_num(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_NUM);
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR)) {
debug("Could not probe the EEPROM at 0x%x\n",
CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR);
return -1;
}
return 0;
}
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* 0046 EEPROM Definitions
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EEPROM_BOARD_HELPER__
#define __EEPROM_BOARD_HELPER__
int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
int check_eeprom (void);
#endif
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e0774 0x000C0000
DATA 4 0x020e0754 0x00000000
DATA 4 0x020e04ac 0x00020030
DATA 4 0x020e04b0 0x00020030
DATA 4 0x020e0464 0x00020030
DATA 4 0x020e0490 0x00020030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e0494 0x00020030
DATA 4 0x020e04a0 0x00000000
DATA 4 0x020e04b4 0x00003030
DATA 4 0x020e04b8 0x00003030
DATA 4 0x020e076c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e04bc 0x00000030
DATA 4 0x020e04c0 0x00000030
DATA 4 0x020e04c4 0x00000030
DATA 4 0x020e04c8 0x00000030
DATA 4 0x020e04cc 0x00000030
DATA 4 0x020e04d0 0x00000030
DATA 4 0x020e04d4 0x00000030
DATA 4 0x020e04d8 0x00000030
DATA 4 0x020e0760 0x00020000
DATA 4 0x020e0764 0x00000030
DATA 4 0x020e0770 0x00000030
DATA 4 0x020e0778 0x00000030
DATA 4 0x020e077c 0x00000030
DATA 4 0x020e0780 0x00000030
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e0470 0x00020030
DATA 4 0x020e0474 0x00020030
DATA 4 0x020e0478 0x00020030
DATA 4 0x020e047c 0x00020030
DATA 4 0x020e0480 0x00020030
DATA 4 0x020e0484 0x00020030
DATA 4 0x020e0488 0x00020030
DATA 4 0x020e048c 0x00020030
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x001F001F
DATA 4 0x021b4810 0x001F001F
DATA 4 0x021b083c 0x4220021F
DATA 4 0x021b0840 0x0207017E
DATA 4 0x021b483c 0x4201020C
DATA 4 0x021b4840 0x01660172
DATA 4 0x021b0848 0x4A4D4E4D
DATA 4 0x021b4848 0x4A4F5049
DATA 4 0x021b0850 0x3F3C3D31
DATA 4 0x021b4850 0x3238372B
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b0004 0x0002002D
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x696C5323
DATA 4 0x021b0010 0xB66E8B63
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x006C1023
DATA 4 0x021b0040 0x00000047
DATA 4 0x021b0000 0x841A0000
DATA 4 0x021b001c 0x04008032
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x00048031
DATA 4 0x021b001c 0x13208030
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b0020 0x00007800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b4818 0x00022227
DATA 4 0x021b0004 0x0002556D
DATA 4 0x021b0404 0x00011006
DATA 4 0x021b001c 0x00000000
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020e0774 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020e0754 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4 0x020e04ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
DATA 4 0x020e04b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//ADDRESS:
DATA 4 0x020e0464 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DATA 4 0x020e0490 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4 0x020e0494 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020e04a0 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4 0x020e04b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
DATA 4 0x020e04b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
DATA 4 0x020e076c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020e04bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
DATA 4 0x020e04c0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
DATA 4 0x020e04c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
DATA 4 0x020e04c8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
DATA 4 0x020e04cc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
DATA 4 0x020e04d0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
DATA 4 0x020e04d4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
DATA 4 0x020e04d8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
DATA 4 0x020e0760 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020e0764 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020e0770 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020e0778 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS
DATA 4 0x020e077c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS
DATA 4 0x020e0780 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
DATA 4 0x020e0470 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020e0474 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DATA 4 0x020e0478 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DATA 4 0x020e047c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
DATA 4 0x020e0480 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
DATA 4 0x020e0484 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
DATA 4 0x020e0488 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
DATA 4 0x020e048c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Samsung
// Device Part Number: K4B4G1646D-BMK00CV
// Clock Freq.: MHz
// Density per CS in Gb: 16
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 15
// Column address: 10
// Data bus width 64
//=============================================================================
DATA 4 0x021b001c 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup.
//=============================================================================
DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
DATA 4 0x021b080c 0x00530056
DATA 4 0x021b0810 0x00440053
DATA 4 0x021b480c 0x002B002B
DATA 4 0x021b4810 0x0028003F
////Read DQS Gating calibration
DATA 4 0x021b083c 0x021C021C // MPDGCTRL0 PHY0
DATA 4 0x021b0840 0x02140214 // MPDGCTRL1 PHY0
DATA 4 0x021b483c 0x0178017C // MPDGCTRL0 PHY1
DATA 4 0x021b4840 0x016C0170 // MPDGCTRL1 PHY1
//Read calibration
DATA 4 0x021b0848 0x46484C48 // MPRDDLCTL PHY0
DATA 4 0x021b4848 0x42424842 // MPRDDLCTL PHY1
//Write calibration
DATA 4 0x021b0850 0x3434302E // MPWRDLCTL PHY0
DATA 4 0x021b4850 0x3A303830 // MPWRDLCTL PHY1
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
//DATA 4 0x021b08c0 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
//DATA 4 0x021b48c0 0x24911492
// Complete calibration by forced measurement:
DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================
//MMDC init:
DATA 4 0x021b0004 0x0002002D // MMDC0_MDPDC
DATA 4 0x021b0008 0x00333040 // MMDC0_MDOTC
DATA 4 0x021b000c 0x676B52F3 // MMDC0_MDCFG0
DATA 4 0x021b0010 0xB66D8B63 // MMDC0_MDCFG1
DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021b0018 0x00011740 // MMDC0_MDMISC
DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD
DATA 4 0x021b0030 0x006B1023 // MMDC0_MDOR
DATA 4 0x021b0040 0x00000047 // Chan0 CS0_END
DATA 4 0x021b0000 0x841A0000 // MMDC0_MDCTL
//Mode register writes
DATA 4 0x021b001c 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021b001c 0x15208030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
//DATA 4 0x021b001c 0x0200803A // MMDC0_MDSCR, MR2 write, CS1
//DATA 4 0x021b001c 0x0000803B // MMDC0_MDSCR, MR3 write, CS1
//DATA 4 0x021b001c 0x00048039 // MMDC0_MDSCR, MR1 write, CS1
//DATA 4 0x021b001c 0x15208038 // MMDC0_MDSCR, MR0write, CS1
//DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1
DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF
DATA 4 0x021b0818 0x00022227 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021b4818 0x00022227 // DDR_PHY_P1_MPODTCTRL
DATA 4 0x021b0004 0x0002556D // MMDC0_MDPDC now SDCTL power down enabled
DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
......@@ -3,7 +3,10 @@ CONFIG_ARCH_MX6=y
CONFIG_TARGET_IGEP0046=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0046/mx6dl_igep0046_4x512.cfg,MX6DL,ENV_IS_NOWHERE"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg,MX6DL,ENV_IS_NOWHERE"
CONFIG_BOOTDELAY=2
CONFIG_CMD_BOOTM=n
CONFIG_CMD_BOOTD=n
CONFIG_CMD_CACHE=y
CONFIG_SPLASH_SCREEN=n
CONFIG_BASE0040=y
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* Configuration settings for the IGEP0046 board
* Header file for IGEP0046 board
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
......@@ -13,6 +13,9 @@
#include "mx6_common.h"
/* CPU */
#define CONFIG_IMX_THERMAL
/* GPIO */
#define CONFIG_MXC_GPIO
......@@ -52,7 +55,7 @@
/* Miscellaneous configurable options */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT "Press ESC to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_PROMPT "Press ESC to abort autoboot in 3 seconds\n"
#define CONFIG_AUTOBOOT_STOP_STR "\x1b"
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
......@@ -78,12 +81,74 @@
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* MMC Configs */
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
/* EEPROM Configs */
#define CONFIG_IGEP0046_CFG_EEPROM
#define CONFIG_SYS_I2C_IGEP0046_CFG_BUS_NUM 2
#define CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR 0x50
/* NET Configs */
#define CONFIG_ENV_OVERWRITE /* To allow write MAC into ethaddr variable */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
/* USB Configs */
/* Host */
#define CONFIG_USB
#define CONFIG_CMD_USB /* Enable USB Commands */
#define CONFIG_USB_EHCI /* EHCI driver */
#define CONFIG_USB_EHCI_MX6 /* iMX6 EHCI driver */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* OTG Core Init after Reset*/
#define CONFIG_USB_HOST_ETHER /* USB Ethernet support */
#define CONFIG_USB_ETHER_ASIX /* USB Ethernet support hardware adapter */
#define CONFIG_USB_KEYBOARD /* USB Keyboard support */
#define CONFIG_USB_STORAGE /* USB Storage support */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* MACRO non-ehci registers in the FSL SOC USB controller */
#define CONFIG_MXC_USB_FLAGS 0 /* MXC Flag for ehci_hcd_init ?? */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number (core 0 + core 1) */
/* Device */
#define CONFIG_CI_UDC /* USB ChipIdea Device driver */
#define CONFIG_USBD_HS /* USB Device High speed support */
#define CONFIG_USB_GADGET /* USB Device Gadget Layer support */
#define CONFIG_USB_GADGET_DUALSPEED /* USB Device High speed support Ethernet */
#define CONFIG_USB_FUNCTION_MASS_STORAGE /* USB Device Mass Storage support */
#define CONFIG_CMD_USB_MASS_STORAGE /* USB CMD Mass Storage suppor */
#define CONFIG_USB_GADGET_DOWNLOAD /* USB Download Gadget support */
#define CONFIG_USB_GADGET_VBUS_DRAW 2 /* Maximum VBUS power usage (2-500 mA) */
#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* Vendor ID of USB Device */
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 /* Product ID of USB Device */
#define CONFIG_G_DNL_MANUFACTURER "FSL" /* Manufacturer of USB Device */
/* Environment */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#endif /* __IGEP0046_CONFIG_H */
......
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