Commit c43b4032 by Jose Miquel Sanabria

IGEP0146: Initial commit

Structure folders defconfig initial ram config only UART will be configured for basic printf Signed-off-by: Jose Miquel Sanabria's avatarJose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
parent 576e625e
......@@ -153,12 +153,19 @@ config TARGET_GW_VENTANA
config TARGET_IGEP0046
bool "Support IMX6 igep0046"
select CPU_V7
select DM
select DM_THERMAL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
config TARGET_IGEP0146
bool "Support IMX6 igep0146"
select DM
select DM_THERMAL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
......@@ -511,6 +518,7 @@ source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/isee/igep0046/Kconfig"
source "board/isee/igep0146/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
......
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* EEPROM support source file for IGEP0046 board
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/sys_proto.h>
int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
udelay(5000);
}
if(remain > 0){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
else
udelay(5000);
}
return 0;
}
int eeprom_read_setup (uint8_t s_addr, char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
}
if(remain > 0)
if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
return 0;
}
int check_eeprom (void)
{
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
printf("Could not probe the EEPROM at 0x%x\n",
CONFIG_SYS_I2C_EEPROM_ADDR);
return -1;
}
return 0;
}
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* 0046 EEPROM Definitions
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EEPROM_BOARD_HELPER__
#define __EEPROM_BOARD_HELPER__
int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size);
int eeprom_read_setup (uint8_t s_addr, char* data, u32 size);
int check_eeprom (void);
#endif
if TARGET_IGEP0146
config SYS_BOARD
default "igep0146"
config SYS_VENDOR
default "isee"
config SYS_CONFIG_NAME
default "igep0146"
endif
IGEP0046 BOARD
M: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
S: Maintained
F: board/isee/igep0146/igep0146.c
F: include/configs/igep0146.h
F: configs/mx6ul_igep0146_512M_defconfig
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += igep0146.o
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* Source file for IGEP0046 board
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mx6-ddr.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx6/sys_proto.h>
#include <asm/io.h>
#include "../common/igep_common.h"
DECLARE_GLOBAL_DATA_PTR;
/* MACRO MUX defines */
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define GPIO_LED_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST )
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
}
/* UART MUX */
static iomux_v3_cfg_t const uart3_pads[] =
{
MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const led_pads[] = {
MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
static void setup_iomux_leds(void)
{
imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
}
int checkboard(void)
{
return 0;
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_leds();
/* configure LEDS */
gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
return 0;
}
int board_init(void)
{
return 0;
}
int board_late_init(void)
{
checkboard();
puts("\n");
return 0;
}
#ifdef CONFIG_LDO_BYPASS_CHECK
/* TODO, use external pmic, for now always ldo_enable */
void ldo_mode_set(int ldo_bypass)
{
return;
}
#endif
\ No newline at end of file
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* EEPROM support source file for IGEP0046 board
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/sys_proto.h>
int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
udelay(5000);
}
if(remain > 0){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
else
udelay(5000);
}
return 0;
}
int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
}
if(remain > 0)
if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
return 0;
}
int check_eeprom (void)
{
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
printf("Could not probe the EEPROM at 0x%x\n",
CONFIG_SYS_I2C_EEPROM_ADDR);
return -1;
}
return 0;
}
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* 0046 EEPROM Definitions
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EEPROM_BOARD_HELPER__
#define __EEPROM_BOARD_HELPER__
int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
int check_eeprom (void);
#endif
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* New DDR type MT41K64M16TW-107 */
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4 0x020c4068 0xffffffff // CCM_CCGR0
DATA 4 0x020c406c 0xffffffff // CCM_CCGR1
DATA 4 0x020c4070 0xffffffff // CCM_CCGR2
DATA 4 0x020c4074 0xffffffff // CCM_CCGR3
DATA 4 0x020c4078 0xffffffff // CCM_CCGR4
DATA 4 0x020c407c 0xffffffff // CCM_CCGR5
DATA 4 0x020c4080 0xffffffff // CCM_CCGR6
//=============================================================================
// IOMUX IMX6UL - MCIMX6G3CV
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020E04B4 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020E04AC 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4 0x020E027C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
//ADDRESS:
DATA 4 0x020E0250 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B
DATA 4 0x020E024C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
DATA 4 0x020E0490 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4 0x020E0288 0x000C0030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020E0270 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
DATA 4 0x020E0260 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
DATA 4 0x020E0264 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
DATA 4 0x020E04A0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020E0494 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020E0280 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
DATA 4 0x020E0284 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
//Data:
DATA 4 0x020E04B0 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020E0498 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020E04A4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020E0244 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020E0248 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K64M16TW-107
// Clock Freq.: 933 MHz IMX6UL ensures data capture margin up to 400 Mhz
// Density per CS in Gb: 1 Gb
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 13
// Column address: 10
// Data bus width 16
//=============================================================================
DATA 4 0x021B001C 0x00008000 // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup. REVISAR
//=============================================================================
DATA 4 0x021B0800 0xA1390003 // MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
DATA 4 0x021B080C 0x00000000 // MMDC_MPWLDECTRL0
// Read DQS Gating calibration
DATA 4 0x021B083C 0x415C015C // MMDC_MPDGCTRL0
// Read Calibration
DATA 4 0x021B0848 0x40404040 // MMDC_MPRDDLCTL 0x40404244
// Write Calibration
DATA 4 0x021B0850 0x40404040 // MMDC_MPWRDLCTL 0x40405A58
// Read Data bit delay
DATA 4 0x021B081C 0x33333333 // MMDC_MPRDDQBY0DL
DATA 4 0x021B0820 0x33333333 // MMDC_MPRDDQBY1DL
DATA 4 0x021B082C 0xf3333333 // MMDC_MPWRDQBY0DL
DATA 4 0x021B0830 0xf3333333 // MMDC_MPWRDQBY1DL
// Control Duty Cicle DQS of and primary clock CK0
DATA 4 0x021B08C0 0x24922492 // MMDC_MPDCCR 0x00921012 24922492 0x00921012
// Complete Calibration by Forced Measurement
DATA 4 0x021B08b8 0x00008000 // MMDC_MPMUR0
//=============================================================================
// Calibration setup end
//=============================================================================
// MMCD Init
DATA 4 0x021B0004 0x00020036 // MMDC_MDPDC
DATA 4 0x021B0008 0x1B333030 // MMDC_MDOTC
DATA 4 0x021B000C 0x676B52F3 // MMDC_MDCFG0
DATA 4 0x021B0010 0xB66D0B63 // MMDC_MDCFG1
DATA 4 0x021B0014 0x01FF00DB // MMDC_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021B0018 0x00201740 // MMDC_MDMISC
DATA 4 0x021B001C 0x00000800 // MMDC_MDSCR
DATA 4 0x021B002C 0x000026D2 // MMDC_MDRWD
DATA 4 0x021B0030 0x006B1023 // MMDC_MDOR
DATA 4 0x021B0040 0x0000004F // MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
DATA 4 0x021B0000 0x82180000 // MMDC_MDCTL
// ????
DATA 4 0x021B0890 0x00400000 // MMDC_MPPDCMPR2 DDR2 Only ???
// Mode Register writes
// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
DATA 4 0x021B001C 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021B001C 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021B001C 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021B001C 0x15208030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021B001C 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
DATA 4 0x021B0020 0x00000800 // MMDC0_MDREF
DATA 4 0x021B0818 0x00000227 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021B0004 0x0002552D // MMDC0_MDPDC
DATA 4 0x021B0404 0x00011006 // MMDC0_MAPSR
DATA 4 0x021B001C 0x00000000 // MMDC0_MDSCR
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* DDR type MT41K256M16TW-107 */
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4 0x020c4068 0xffffffff // CCM_CCGR0
DATA 4 0x020c406c 0xffffffff // CCM_CCGR1
DATA 4 0x020c4070 0xffffffff // CCM_CCGR2
DATA 4 0x020c4074 0xffffffff // CCM_CCGR3
DATA 4 0x020c4078 0xffffffff // CCM_CCGR4
DATA 4 0x020c407c 0xffffffff // CCM_CCGR5
DATA 4 0x020c4080 0xffffffff // CCM_CCGR6
//=============================================================================
// IOMUX IMX6UL - MCIMX6G3CV
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020E04B4 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020E04AC 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4 0x020E027C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
//ADDRESS:
DATA 4 0x020E0250 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B
DATA 4 0x020E024C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
DATA 4 0x020E0490 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4 0x020E0288 0x000C0030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020E0270 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
DATA 4 0x020E0260 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
DATA 4 0x020E0264 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
DATA 4 0x020E04A0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020E0494 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020E0280 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
DATA 4 0x020E0284 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
//Data:
DATA 4 0x020E04B0 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020E0498 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020E04A4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020E0244 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020E0248 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K256M16TW-107
// Clock Freq.: 933 MHz IMX6UL ensures data capture margin up to 400 Mhz
// Density per CS in Gb: 4 Gb
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 15
// Column address: 10
// Data bus width 16
//=============================================================================
DATA 4 0x021B001C 0x00008000 // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup. REVISAR
//=============================================================================
DATA 4 0x021B0800 0xA1390003 // MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
DATA 4 0x021B080C 0x00000000 // MMDC_MPWLDECTRL0
// Read DQS Gating calibration
DATA 4 0x021B083C 0x00000000 // MMDC_MPDGCTRL0
// Read Calibration
DATA 4 0x021B0848 0x40404040 // MMDC_MPRDDLCTL 0x40404244
// Write Calibration
DATA 4 0x021B0850 0x40404040 // MMDC_MPWRDLCTL 0x40405A58
// Read Data bit delay
DATA 4 0x021B081C 0x33333333 // MMDC_MPRDDQBY0DL
DATA 4 0x021B0820 0x33333333 // MMDC_MPRDDQBY1DL
DATA 4 0x021B082C 0xf3333333 // MMDC_MPWRDQBY0DL
DATA 4 0x021B0830 0xf3333333 // MMDC_MPWRDQBY1DL
// Control Duty Cicle DQS of and primary clock CK0
DATA 4 0x021B08C0 0x24922492 // MMDC_MPDCCR 0x00921012 24922492 0x00921012
// Complete Calibration by Forced Measurement
DATA 4 0x021B08b8 0x00008000 // MMDC_MPMUR0
//=============================================================================
// Calibration setup end
//=============================================================================
// MMCD Init
DATA 4 0x021B0004 0x00020036 // MMDC_MDPDC
DATA 4 0x021B0008 0x00333030 // MMDC_MDOTC
DATA 4 0x021B000C 0x676B52F3 // MMDC_MDCFG0
DATA 4 0x021B0010 0xB66D0B63 // MMDC_MDCFG1
DATA 4 0x021B0014 0x01FF00DB // MMDC_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021B0018 0x00201740 // MMDC_MDMISC
DATA 4 0x021B001C 0x00000800 // MMDC_MDSCR
DATA 4 0x021B002C 0x000026D2 // MMDC_MDRWD
DATA 4 0x021B0030 0x006B1023 // MMDC_MDOR
DATA 4 0x021B0040 0x0000003F // MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
DATA 4 0x021B0000 0x84180000 // MMDC_MDCTL
// ????
DATA 4 0x021B0890 0x00400000 // MMDC_MPPDCMPR2 DDR2 Only ???
// Mode Register writes
// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
DATA 4 0x021B001C 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021B001C 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021B001C 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021B001C 0x15208030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021B001C 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
DATA 4 0x021B0020 0x00000800 // MMDC0_MDREF
DATA 4 0x021B0818 0x00000227 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021B0004 0x0002556D // MMDC0_MDPDC
DATA 4 0x021B0404 0x00011006 // MMDC0_MAPSR
DATA 4 0x021B001C 0x00000000 // MMDC0_MDSCR
/*
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff