Browse Source

Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master

master
Wolfgang Denk 10 years ago
parent
commit
c163f4478c
170 changed files with 6790 additions and 9323 deletions
  1. +5
    -4
      MAINTAINERS
  2. +5
    -27
      MAKEALL
  3. +0
    -82
      Makefile
  4. +72
    -77
      arch/arm/cpu/pxa/start.S
  5. +8
    -11
      arch/arm/cpu/pxa/u-boot.lds
  6. +11
    -0
      arch/arm/include/asm/arch-mx5/crm_regs.h
  7. +3
    -0
      arch/arm/lib/board.c
  8. +1
    -1
      arch/sh/config.mk
  9. +65
    -1
      arch/sh/lib/bootm.c
  10. +23
    -39
      board/a4m072/a4m072.c
  11. +4
    -6
      board/cerf250/Makefile
  12. +11
    -11
      board/cerf250/cerf250.c
  13. +0
    -5
      board/cerf250/config.mk
  14. +0
    -411
      board/cerf250/lowlevel_init.S
  15. +4
    -6
      board/colibri_pxa270/Makefile
  16. +12
    -6
      board/colibri_pxa270/colibri_pxa270.c
  17. +0
    -1
      board/colibri_pxa270/config.mk
  18. +0
    -36
      board/colibri_pxa270/lowlevel_init.S
  19. +4
    -6
      board/cradle/Makefile
  20. +0
    -2
      board/cradle/config.mk
  21. +14
    -16
      board/cradle/cradle.c
  22. +0
    -515
      board/cradle/lowlevel_init.S
  23. +4
    -6
      board/csb226/Makefile
  24. +0
    -15
      board/csb226/config.mk
  25. +11
    -11
      board/csb226/csb226.c
  26. +0
    -437
      board/csb226/lowlevel_init.S
  27. +0
    -52
      board/delta/Makefile
  28. +0
    -1
      board/delta/config.mk
  29. +0
    -378
      board/delta/delta.c
  30. +0
    -146
      board/delta/lowlevel_init.S
  31. +0
    -558
      board/delta/nand.c
  32. +4
    -6
      board/innokom/Makefile
  33. +0
    -15
      board/innokom/config.mk
  34. +11
    -12
      board/innokom/innokom.c
  35. +0
    -437
      board/innokom/lowlevel_init.S
  36. +4
    -6
      board/lubbock/Makefile
  37. +0
    -3
      board/lubbock/config.mk
  38. +0
    -411
      board/lubbock/lowlevel_init.S
  39. +11
    -11
      board/lubbock/lubbock.c
  40. +4
    -6
      board/palmld/Makefile
  41. +0
    -1
      board/palmld/config.mk
  42. +0
    -45
      board/palmld/lowlevel_init.S
  43. +13
    -3
      board/palmld/palmld.c
  44. +0
    -56
      board/palmld/u-boot.lds
  45. +4
    -5
      board/palmtc/Makefile
  46. +0
    -1
      board/palmtc/config.mk
  47. +0
    -39
      board/palmtc/lowlevel_init.S
  48. +12
    -1
      board/palmtc/palmtc.c
  49. +0
    -56
      board/palmtc/u-boot.lds
  50. +4
    -6
      board/pleb2/Makefile
  51. +0
    -3
      board/pleb2/config.mk
  52. +0
    -488
      board/pleb2/lowlevel_init.S
  53. +11
    -11
      board/pleb2/pleb2.c
  54. +4
    -6
      board/pxa255_idp/Makefile
  55. +0
    -3
      board/pxa255_idp/config.mk
  56. +0
    -496
      board/pxa255_idp/lowlevel_init.S
  57. +11
    -12
      board/pxa255_idp/pxa_idp.c
  58. +3
    -1
      board/renesas/sh7785lcr/config.mk
  59. +4
    -6
      board/trizepsiv/Makefile
  60. +0
    -3
      board/trizepsiv/config.mk
  61. +12
    -11
      board/trizepsiv/conxs.c
  62. +0
    -503
      board/trizepsiv/lowlevel_init.S
  63. +68
    -0
      board/ttcontrol/vision2/vision2.c
  64. +0
    -51
      board/wepep250/Makefile
  65. +0
    -11
      board/wepep250/config.mk
  66. +0
    -324
      board/wepep250/flash.c
  67. +0
    -99
      board/wepep250/intel.h
  68. +0
    -145
      board/wepep250/lowlevel_init.S
  69. +0
    -68
      board/wepep250/wepep250.c
  70. +4
    -6
      board/xaeniax/Makefile
  71. +0
    -2
      board/xaeniax/config.mk
  72. +0
    -424
      board/xaeniax/lowlevel_init.S
  73. +11
    -11
      board/xaeniax/xaeniax.c
  74. +4
    -0
      board/xes/common/Makefile
  75. +64
    -0
      board/xes/common/board.c
  76. +11
    -0
      board/xes/common/fsl_8xxx_clk.c
  77. +62
    -0
      board/xes/common/fsl_8xxx_misc.c
  78. +6
    -7
      board/xes/common/fsl_8xxx_misc.h
  79. +49
    -279
      board/xes/common/fsl_8xxx_pci.c
  80. +0
    -0
      board/xes/xpedite517x/Makefile
  81. +0
    -0
      board/xes/xpedite517x/ddr.c
  82. +0
    -0
      board/xes/xpedite517x/law.c
  83. +1
    -19
      board/xes/xpedite517x/xpedite517x.c
  84. +0
    -0
      board/xes/xpedite520x/Makefile
  85. +0
    -0
      board/xes/xpedite520x/ddr.c
  86. +0
    -0
      board/xes/xpedite520x/law.c
  87. +0
    -0
      board/xes/xpedite520x/tlb.c
  88. +0
    -27
      board/xes/xpedite520x/xpedite520x.c
  89. +0
    -0
      board/xes/xpedite537x/Makefile
  90. +0
    -0
      board/xes/xpedite537x/ddr.c
  91. +0
    -0
      board/xes/xpedite537x/law.c
  92. +0
    -0
      board/xes/xpedite537x/tlb.c
  93. +0
    -20
      board/xes/xpedite537x/xpedite537x.c
  94. +39
    -0
      board/xes/xpedite550x/Makefile
  95. +165
    -0
      board/xes/xpedite550x/ddr.c
  96. +54
    -0
      board/xes/xpedite550x/law.c
  97. +98
    -0
      board/xes/xpedite550x/tlb.c
  98. +107
    -0
      board/xes/xpedite550x/xpedite550x.c
  99. +4
    -6
      board/xm250/Makefile
  100. +0
    -35
      board/xm250/config.mk

+ 5
- 4
MAINTAINERS View File

@ -462,10 +462,11 @@ Rune Torgersen <runet@innovsys.com>
Peter Tyser <ptyser@xes-inc.com>
XPEDITE1000 PPC440GX
XPEDITE5170 MPC8640
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
xpedite1000 PPC440GX
xpedite5170 MPC8640
xpedite5200 MPC8548
xpedite5370 MPC8572
xpedite5500 P2020
David Updegraff <dave@cray.com>


+ 5
- 27
MAKEALL View File

@ -554,9 +554,7 @@ LIST_mips_el=" \
## i386 Systems
#########################################################################
LIST_x86="$(boards_by_arch i386)
sc520_eNET \
"
LIST_x86="$(boards_by_arch i386)"
#########################################################################
## Nios-II Systems
@ -609,31 +607,11 @@ LIST_blackfin="$(boards_by_arch blackfin)
## SH Systems
#########################################################################
LIST_sh2=" \
rsk7203 \
"
LIST_sh3=" \
mpr2 \
ms7720se \
"
LIST_sh4=" \
ms7750se \
ms7722se \
MigoR \
r7780mp \
r2dplus \
sh7763rdp \
sh7785lcr \
ap325rxa \
espt \
"
LIST_sh2="$(boards_by_cpu sh2)"
LIST_sh3="$(boards_by_cpu sh3)"
LIST_sh4="$(boards_by_cpu sh4)"
LIST_sh=" \
${LIST_sh2} \
${LIST_sh3} \
${LIST_sh4} \
"
LIST_sh="$(boards_by_arch sh)"
#########################################################################
## SPARC Systems


+ 0
- 82
Makefile View File

@ -1184,88 +1184,6 @@ bf527-ezkit-v2_config : unconfig
@$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
bf527-ezkit blackfin blackfin bf527-ezkit
#========================================================================
# SH3 (SuperH)
#========================================================================
#########################################################################
## sh2 (Renesas SuperH)
#########################################################################
rsk7203_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_RSK7203 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh2 rsk7203 renesas
#########################################################################
## sh3 (Renesas SuperH)
#########################################################################
mpr2_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MPR2 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh3 mpr2
ms7720se_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh3 ms7720se
#########################################################################
## sh4 (Renesas SuperH)
#########################################################################
MigoR_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 MigoR renesas
ms7750se_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 ms7750se
ms7722se_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 ms7722se
r2dplus_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 r2dplus renesas
r7780mp_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 r7780mp renesas
sh7763rdp_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 sh7763rdp renesas
sh7785lcr_32bit_config \
sh7785lcr_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/renesas/sh7785lcr
@echo "#define CONFIG_SH7785LCR 1" > $(obj)include/config.h
@if [ "$(findstring 32bit, $@)" ] ; then \
echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
echo "CONFIG_SYS_TEXT_BASE = 0x8ff80000" > \
$(obj)board/renesas/sh7785lcr/config.tmp ; \
fi
@$(MKCONFIG) -n $@ -a sh7785lcr sh sh4 sh7785lcr renesas
ap325rxa_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 ap325rxa renesas
espt_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 espt
#########################################################################
#########################################################################


+ 72
- 77
arch/arm/cpu/pxa/start.S View File

@ -8,6 +8,7 @@
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -94,20 +95,16 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl _armboot_start
_armboot_start:
.word _start
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end
_bss_end:
.word _end
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@ -127,30 +124,6 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _got_start
_got_start:
.word __got_start
.globl _got_end
_got_end:
.word __got_end
/*
* the actual reset code
*/
@ -272,9 +245,8 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
@ -288,36 +260,54 @@ copy_loop:
ldmfd sp!, {r0-r12}
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE /* Text base */
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -332,24 +322,33 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
#ifdef CONFIG_ONENAND_IPL
ldr pc, _start_oneboot
ldr r0, _start_oneboot_ofs
mov pc, r0
_start_oneboot: .word start_oneboot
_start_oneboot_ofs
: .word start_oneboot
#else
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
_board_init_r_ofs:
.word board_init_r - _start
#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/****************************************************************************/
@ -567,13 +566,7 @@ fiq:
/* */
/****************************************************************************/
/* Operating System Timer */
OSTIMER_BASE: .word 0x40a00000
#define OSMR3 0x0C
#define OSCR 0x10
#define OWER 0x18
#define OIER 0x1C
.align 5
.align 5
.globl reset_cpu
/* FIXME: this code is PXA250 specific. How is this handled on */
@ -583,18 +576,20 @@ reset_cpu:
/* We set OWE:WME (watchdog enable) and wait until timeout happens */
ldr r0, OSTIMER_BASE
ldr r1, [r0, #OWER]
ldr r0, =OWER
ldr r1, [r0]
orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0, #OWER]
str r1, [r0]
/* OS timer does only wrap every 1165 seconds, so we have to set */
/* the match register as well. */
ldr r1, [r0, #OSCR] /* read OS timer */
ldr r0, =OSCR
ldr r1, [r0] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
str r1, [r0, #OSMR3]
ldr r0, =OSMR3
str r1, [r0]
reset_endless:


+ 8
- 11
arch/arm/cpu/pxa/u-boot.lds View File

@ -41,21 +41,18 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
__datarel_start = .;
*(.data.rel)
__datarelrolocal_start = .;
*(.data.rel.ro.local)
__datarellocal_start = .;
*(.data.rel.local)
__datarelro_start = .;
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
. = ALIGN(4);
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }


+ 11
- 0
arch/arm/include/asm/arch-mx5/crm_regs.h View File

@ -189,4 +189,15 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR5_CG5_OFFSET 10
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */

+ 3
- 0
arch/arm/lib/board.c View File

@ -716,6 +716,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
#if defined(CONFIG_CMD_I2C)
i2c_reloc();
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_reloc();
#endif
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
#ifdef CONFIG_LOGBUFFER


+ 1
- 1
arch/sh/config.mk View File

@ -29,6 +29,6 @@ STANDALONE_LOAD_ADDR += -EB
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds

+ 65
- 1
arch/sh/lib/bootm.c View File

@ -43,6 +43,41 @@ static void hexdump(unsigned char *buf, int len)
}
#endif
#define MOUNT_ROOT_RDONLY 0x000
#define RAMDISK_FLAGS 0x004
#define ORIG_ROOT_DEV 0x008
#define LOADER_TYPE 0x00c
#define INITRD_START 0x010
#define INITRD_SIZE 0x014
#define COMMAND_LINE 0x100
#define RD_PROMPT (1<<15)
#define RD_DOLOAD (1<<14)
#define CMD_ARG_RD_PROMPT "prompt_ramdisk="
#define CMD_ARG_RD_DOLOAD "load_ramdisk="
#ifdef CONFIG_SH_SDRAM_OFFSET
#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
#else
#define GET_INITRD_START(initrd, linux) (initrd - linux)
#endif
static void set_sh_linux_param(unsigned long param_addr, unsigned long data)
{
*(unsigned long *)(param_addr) = data;
}
static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base)
{
unsigned long val = 0;
char *p = strstr(cmdline, key);
if (p) {
p += strlen(key);
val = simple_strtol(p, NULL, base);
}
return val;
}
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
/* Linux kernel load address */
@ -51,7 +86,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
unsigned char *param
= (unsigned char *)image_get_load(images->legacy_hdr_os);
/* Linux kernel command line */
char *cmdline = (char *)param + 0x100;
char *cmdline = (char *)param + COMMAND_LINE;
/* PAGE_SIZE */
unsigned long size = images->ep - (unsigned long)param;
char *bootargs = getenv("bootargs");
@ -61,8 +96,37 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
/* Setup parameters */
memset(param, 0, size); /* Clear zero page */
/* Set commandline */
strcpy(cmdline, bootargs);
sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
/* Initrd */
if (images->rd_start || images->rd_end) {
unsigned long ramdisk_flags = 0;
int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10);
if (val == 1)
ramdisk_flags |= RD_PROMPT;
else
ramdisk_flags &= ~RD_PROMPT;
val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
if (val == 1)
ramdisk_flags |= RD_DOLOAD;
else
ramdisk_flags &= ~RD_DOLOAD;
set_sh_linux_param((unsigned long)param + MOUNT_ROOT_RDONLY, 0x0001);
set_sh_linux_param((unsigned long)param + RAMDISK_FLAGS, ramdisk_flags);
set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
set_sh_linux_param((unsigned long)param + INITRD_START,
GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
set_sh_linux_param((unsigned long)param + INITRD_SIZE,
images->rd_end - images->rd_start);
}
/* Boot kernel */
kernel();
/* does not return */


+ 23
- 39
board/a4m072/a4m072.c View File

@ -270,8 +270,6 @@ static u8 display_buf[DISPLAY_BUF_SIZE];
static u8 display_putc_pos;
static u8 display_out_pos;
static u8 display_dot_enable;
void display_set(int cmd) {
if (cmd & DISPLAY_CLEAR) {
@ -281,12 +279,6 @@ void display_set(int cmd) {
if (cmd & DISPLAY_HOME) {
display_putc_pos = 0;
}
if (cmd & DISPLAY_MARK) {
display_dot_enable = 1;
} else {
display_dot_enable = 0;
}
}
#define SEG_A (1<<0)
@ -314,10 +306,12 @@ void display_set(int cmd) {
* A..Z index 10..35
* - index 36
* _ index 37
* . index 38
*/
#define SYMBOL_DASH (36)
#define SYMBOL_UNDERLINE (37)
#define SYMBOL_DOT (38)
static u8 display_char2seg7_tbl[]=
{
@ -337,28 +331,29 @@ static u8 display_char2seg7_tbl[]=
SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
SEG_A | SEG_E | SEG_F | SEG_G, /* F */
SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* g */
0, /* g - not displayed */
SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
SEG_E | SEG_F, /* I */
SEG_B | SEG_C | SEG_D | SEG_E, /* J */
SEG_A, /* K - special 1 */
SEG_B | SEG_C, /* I */
0, /* J - not displayed */
0, /* K - not displayed */
SEG_D | SEG_E | SEG_F, /* L */
SEG_B, /* m - special 2 */
SEG_C | SEG_E | SEG_G, /* n */
SEG_C | SEG_D | SEG_E | SEG_G, /* o */
0, /* m - not displayed */
0, /* n - not displayed */
SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
SEG_A | SEG_B | SEG_C | SEG_F | SEG_G, /* q */
SEG_E | SEG_G, /* r */
0, /* q - not displayed */
0, /* r - not displayed */
SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
SEG_D | SEG_E | SEG_F | SEG_G, /* t */
SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
SEG_C | SEG_D | SEG_E | SEG_F, /* V */
SEG_C, /* w - special 3 */
SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* X */
0, /* V - not displayed */
0, /* w - not displayed */
0, /* X - not displayed */
SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* Z */
0, /* Z - not displayed */
SEG_G, /* - */
SEG_D /* _ */
SEG_D, /* _ */
SEG_P /* . */
};
/* Convert char to the LED segments representation */
@ -374,23 +369,20 @@ static u8 display_char2seg7(char c)
c -= 'A' - 10;
else if (c == '-')
c = SYMBOL_DASH;
else if ((c == '_') || (c == '.'))
else if (c == '_')
c = SYMBOL_UNDERLINE;
else if (c == '.')
c = SYMBOL_DOT;
else
c = ' '; /* display unsupported symbols as space */
if (c != ' ')
val = display_char2seg7_tbl[(int)c];
/* Handle DP LED here */
if (display_dot_enable) {
val |= SEG_P;
}
return val;
}
static inline int display_putc_nomark(char c)
int display_putc(char c)
{
if (display_putc_pos >= DISPLAY_BUF_SIZE)
return -1;
@ -403,13 +395,6 @@ static inline int display_putc_nomark(char c)
return c;
}
int display_putc(char c)
{
/* Mark the codes from the "display" command with the DP LED */
display_set(DISPLAY_MARK);
return display_putc_nomark(c);
}
/*
* Flush current symbol to the LED display hardware
*/
@ -493,9 +478,8 @@ void show_boot_progress(int status)
if (a4m072_status2code(status, buf) < 0)
return;
display_set(0); /* Clear DP Led */
display_putc_nomark(buf[0]);
display_putc_nomark(buf[1]);
display_putc(buf[0]);
display_putc(buf[1]);
display_set(DISPLAY_HOME);
display_out_pos = 0; /* reset output position */


+ 4
- 6
board/cerf250/Makefile View File

@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := cerf250.o flash.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend


+ 11
- 11
board/cerf250/cerf250.c View File

@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
/* arch number of cerf PXA Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
@ -58,19 +59,18 @@ int board_late_init(void)
return 0;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init (void)
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
return 0;
}
#ifdef CONFIG_CMD_NET


+ 0
- 5
board/cerf250/config.mk View File

@ -1,5 +0,0 @@
#
# Cerf board with PXA250 cpu
#
#
CONFIG_SYS_TEXT_BASE = 0xa3080000

+ 0
- 411
board/cerf250/lowlevel_init.S View File

@ -1,411 +0,0 @@
/*
* Most of this taken from Redboot hal_platform_setup.h with cleanup
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
* board/cradle/lowlevel_init.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
/*
* Memory setup
*/
.globl lowlevel_init
lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
ldr r1, =CONFIG_SYS_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CONFIG_SYS_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CONFIG_SYS_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CONFIG_SYS_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =CONFIG_SYS_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =CONFIG_SYS_GPCR2_VAL
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =CONFIG_SYS_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =CONFIG_SYS_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =CONFIG_SYS_GPDR2_VAL
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =CONFIG_SYS_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =CONFIG_SYS_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =CONFIG_SYS_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =CONFIG_SYS_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =CONFIG_SYS_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =CONFIG_SYS_GAFR2_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
ldr r1, =CONFIG_SYS_PSSR_VAL
str r1, [r0]
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
/* Chapter 10. */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
mem_init:
ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
/* ---------------------------------------------------------------- */
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
ldr r2, =CONFIG_SYS_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
ldr r2, =CONFIG_SYS_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
ldr r2, =CONFIG_SYS_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
ldr r2, =CONFIG_SYS_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
ldr r2, =CONFIG_SYS_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
ldr r2, =CONFIG_SYS_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
ldr r2, =CONFIG_SYS_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
ldr r2, =CONFIG_SYS_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
ldr r2, =CONFIG_SYS_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
ldr r2, =CONFIG_SYS_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
/* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field, set SDRAM clocks free running */
ldr r3, =CONFIG_SYS_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r0, [r1, #MDREFR_OFFSET]
bic r0, r0, r2
bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
orr r0, r0, r3
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
/* ---------------------------------------------------------------- */
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
/* ---------------------------------------------------------------- */
/* Initialize SXCNFG register. Assert the enable bits */
/* Write SXMRS to cause an MRS command to all enabled banks of */
/* synchronous static memory. Note that SXLCR need not be written */
/* at this time. */
/* FIXME: we use async mode for now */
/* ---------------------------------------------------------------- */
/* Step 4: Initialize SDRAM */
/* ---------------------------------------------------------------- */
/* set MDREFR according to user define with exception of a few bits */
ldr r4, =CONFIG_SYS_MDREFR_VAL
ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
MDREFR_K2RUN |MDREFR_K2DB2)
and r4, r4, r2
bic r0, r0, r2
orr r0, r0, r4
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r0, [r1, #MDREFR_OFFSET]
/* Step 4b: de-assert MDREFR:SLFRSH. */
bic r0, r0, #(MDREFR_SLFRSH)
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r0, [r1, #MDREFR_OFFSET]
/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
ldr r4, =CONFIG_SYS_MDREFR_VAL
ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
MDREFR_K1FREE | MDREFR_K2FREE)
and r4, r4, r2
orr r0, r0, r4
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r0, [r1, #MDREFR_OFFSET]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
ldr r4, =CONFIG_SYS_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
/* 100..200 µsec. */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */
/* SDRAM, as commonly specified in the power up sequence */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CONFIG_SYS_DRAM_BASE
.rept 8
str r2, [r3]
.endr
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
ldr r3, [r1, #MDCNFG_OFFSET]
orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
str r3, [r1, #MDCNFG_OFFSET]
/* Step 4h: Write MDMRS. */
ldr r2, =CONFIG_SYS_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
initirqs:
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
ldr r2, =ICLR
str r1, [r2]
ldr r2, =ICMR /* mask all interrupts at the controller */
str r1, [r2]
/* ---------------------------------------------------------------- */
/* Clock initialisation */
/* ---------------------------------------------------------------- */
initclks:
/* Disable the peripheral clocks, and set the core clock frequency */
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
ldr r1, =CKEN
mov r2, #0
str r2, [r1]
/* default value in case no valid rotary switch setting is found */
ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
/* ... and write the core clock config register */
ldr r1, =CCCR
str r2, [r1]
#ifdef RTC
/* enable the 32Khz oscillator for RTC and PowerManager */
ldr r1, =OSCC
mov r2, #OSCC_OON
str r2, [r1]
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
ldr r2, [r1]
ands r2, r2, #1
beq 60b
#endif
/* ---------------------------------------------------------------- */
/* */
/* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
str r8, [r1]
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
mov r1, #0
str r1, [r0]
/* FIXME */
#define NODEBUG
#ifdef NODEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
endlowlevel_init:
mov pc, lr

+ 4
- 6
board/colibri_pxa270/Makefile View File

@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := colibri_pxa270.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend


+ 12
- 6
board/colibri_pxa270/colibri_pxa270.c View File

@ -42,8 +42,9 @@ struct serial_device *default_serial_console (void)
int board_init (void)
{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
/* arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
@ -54,13 +55,18 @@ int board_init (void)
return 0;
}
int dram_init (void)
extern void pxa_dram_init(void);
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_USB


+ 0
- 1
board/colibri_pxa270/config.mk View File

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0xa1000000

+ 0
- 36
board/colibri_pxa270/lowlevel_init.S View File

@ -1,36 +0,0 @@
/*
* Toradex Colibri PXA270 Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
.globl lowlevel_init
lowlevel_init:
pxa_gpio_setup
pxa_wait_ticks 0x8000
pxa_mem_setup
pxa_wakeup
pxa_intr_setup
pxa_clock_setup
mov pc, lr

+ 4
- 6
board/cradle/Makefile View File

@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := cradle.o flash.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend


+ 0
- 2
board/cradle/config.mk View File

@ -1,2 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0xa0f80000
#CONFIG_SYS_TEXT_BASE = 0

+ 14
- 16
board/cradle/cradle.c View File

@ -185,6 +185,10 @@ int
board_init (void)
/**********************************************************/
{
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
led_code (0xf, YELLOW);
/* arch number of HHP Cradle */
@ -206,24 +210,18 @@ board_init (void)
return 1;
}
int
/**********************************************************/
dram_init (void)
/**********************************************************/
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
return (PHYS_SDRAM_1_SIZE +
PHYS_SDRAM_2_SIZE +
PHYS_SDRAM_3_SIZE +
PHYS_SDRAM_4_SIZE );
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET


+ 0
- 515
board/cradle/lowlevel_init.S View File

@ -1,515 +0,0 @@
/*
* Most of this taken from Redboot hal_platform_setup.h with cleanup
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.macro SET_LED val
ldr r6, =GPCR2
ldr r7, =0
str r7, [r6]
ldr r6, =GPSR2
ldr r7, =\val
str r7, [r6]
.endm
.globl lowlevel_init
lowlevel_init:
mov r10, lr
/* Set up GPIO pins first */
ldr r0, =GPSR0
ldr r1, =CONFIG_SYS_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CONFIG_SYS_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CONFIG_SYS_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CONFIG_SYS_GPCR0_VAL
str r1, [r0]